· 9 years ago · Nov 21, 2016, 11:24 AM
1
2// K1
3
4#include "stdafx.h"
5#include <winsock2.h>
6
7
8
9
10
11#pragma comment(lib, "wsock32.lib")
12
13
14#define STUDENT_NUMBER "7654321"
15
16#define IP_ADDRESS_SERVER "127.0.0.1"
17
18#define PORT_SERVER 0x1984 // We define a port that we are going to use.
19#define PORT_CLIENT 0x1985 // We define a port that we are going to use.
20
21#define WORD unsigned short
22#define DWORD unsigned long
23#define BYTE unsigned char
24
25#define MAX_FILENAME_SIZE 500
26#define MAX_BUFFER_SIZE 500
27
28SOCKADDR_IN server_addr;
29SOCKADDR_IN client_addr;
30
31SOCKET sock; // This is our socket, it is the handle to the IO address to read/write packets
32
33WSADATA data;
34
35char InputBuffer[MAX_BUFFER_SIZE];
36
37char hex_file[MAX_BUFFER_SIZE];
38char trc_file[MAX_BUFFER_SIZE];
39
40//////////////////////////
41// Registers //
42//////////////////////////
43
44#define FLAG_I 0x10
45#define FLAG_Z 0x04
46#define FLAG_N 0x02
47#define FLAG_C 0x01
48#define REGISTER_M 4
49#define REGISTER_A 3
50#define REGISTER_B 2
51#define REGISTER_H 1
52#define REGISTER_L 0
53#define REGISTER_X 0
54#define REGISTER_Y 1
55BYTE Index_Registers[2];
56
57BYTE Registers[5];
58BYTE Flags;
59WORD ProgramCounter;
60WORD StackPointer;
61
62
63////////////
64// Memory //
65////////////
66
67#define MEMORY_SIZE 65536
68
69BYTE Memory[MEMORY_SIZE];
70
71#define TEST_ADDRESS_1 0x01FA
72#define TEST_ADDRESS_2 0x01FB
73#define TEST_ADDRESS_3 0x01FC
74#define TEST_ADDRESS_4 0x01FD
75#define TEST_ADDRESS_5 0x01FE
76#define TEST_ADDRESS_6 0x01FF
77#define TEST_ADDRESS_7 0x0200
78#define TEST_ADDRESS_8 0x0201
79#define TEST_ADDRESS_9 0x0202
80#define TEST_ADDRESS_10 0x0203
81#define TEST_ADDRESS_11 0x0204
82#define TEST_ADDRESS_12 0x0205
83
84
85///////////////////////
86// Control variables //
87///////////////////////
88
89bool memory_in_range = true;
90bool halt = false;
91
92
93///////////////////////
94// Disassembly table //
95///////////////////////
96
97char opcode_mneumonics[][14] =
98{
99 "ILLEGAL ",
100 "DECX impl ",
101 "INCX impl ",
102 "DEY impl ",
103 "INCY impl ",
104 "CLC impl ",
105 "STC impl ",
106 "CLI impl ",
107 "STI impl ",
108 "ILLEGAL ",
109 "LDAA # ",
110 "LDAB # ",
111 "LX #,L ",
112 "LX #,L ",
113 "LDX # ",
114 "LDY # ",
115
116 "JMP abs ",
117 "JCC abs ",
118 "JCS abs ",
119 "JNE abs ",
120 "JEQ abs ",
121 "JMI abs ",
122 "JPL abs ",
123 "JHI abs ",
124 "JLE abs ",
125 "ILLEGAL ",
126 "LDAA abs ",
127 "LDAB abs ",
128 "MVI #,L ",
129 "MVI #,H ",
130 "LDX abs ",
131 "LDY abs ",
132
133 "LODS # ",
134 "JSR abs ",
135 "CCC abs ",
136 "CCS abs ",
137 "CNE abs ",
138 "CEQ abs ",
139 "CMI abs ",
140 "CPL abs ",
141 "CHI abs ",
142 "CLE abs ",
143 "LDAA abs,X ",
144 "LDAB abs,X ",
145 "NOP impl ",
146 "HLT impl ",
147 "LDX abs,X ",
148 "LDY abs,X ",
149
150 "LODS abs ",
151 "ADC A,L ",
152 "SBC A,L ",
153 "ADD A,L ",
154 "SUB A,L ",
155 "CMP A,L ",
156 "OR A,L ",
157 "AND A,L ",
158 "XOR A,L ",
159 "BIT A,L ",
160 "LDAA abs,Y ",
161 "LDAB abs,Y ",
162 "ILLEGAL ",
163 "ILLEGAL ",
164 "LDX abs,Y ",
165 "LDY abs,Y ",
166
167 "LODS abs,X ",
168 "ADC A,H ",
169 "SBC A,H ",
170 "ADD A,H ",
171 "SUB A,H ",
172 "CMP A,H ",
173 "OR A,H ",
174 "AND A,H ",
175 "XOR A,H ",
176 "BIT A,H ",
177 "LDAA (ind) ",
178 "LDAB (ind) ",
179 "RET impl ",
180 "ILLEGAL ",
181 "LDX (ind) ",
182 "LDY (ind) ",
183
184 "LODS abs,Y ",
185 "ADC A,M ",
186 "SBC A,M ",
187 "ADD A,M ",
188 "SUB A,M ",
189 "CMP A,M ",
190 "OR A,M ",
191 "AND A,M ",
192 "XOR A,M ",
193 "BIT A,M ",
194 "LDAA (ind,X) ",
195 "LDAB (ind,X) ",
196 "SWI impl ",
197 "RTI impl ",
198 "LDX (ind,X) ",
199 "LDY (ind,X) ",
200
201 "LODS (ind) ",
202 "ADC B,L ",
203 "SBC B,L ",
204 "ADD B,L ",
205 "SUB B,L ",
206 "CMP B,L ",
207 "OR B,L ",
208 "AND B,L ",
209 "XOR B,L ",
210 "BIT B,L ",
211 "STOS abs ",
212 "MOVE A,A ",
213 "MOVE B,A ",
214 "MOVE L,A ",
215 "MOVE H,A ",
216 "MOVE M,A ",
217
218 "LODS (ind,X) ",
219 "ADC B,H ",
220 "SBC B,H ",
221 "ADD B,H ",
222 "SUB B,H ",
223 "CMP B,H ",
224 "OR B,H ",
225 "AND B,H ",
226 "XOR B,H ",
227 "BIT B,H ",
228 "STOS abs,X ",
229 "MOVE A,B ",
230 "MOVE B,B ",
231 "MOVE L,B ",
232 "MOVE H,B ",
233 "MOVE M,B ",
234
235 "ILLEGAL ",
236 "ADC B,M ",
237 "SBC B,M ",
238 "ADD B,M ",
239 "SUB B,M ",
240 "CMP B,M ",
241 "OR B,M ",
242 "AND B,M ",
243 "XOR B,M ",
244 "BIT B,M ",
245 "STOS abs,Y ",
246 "MOVE A,L ",
247 "MOVE B,L ",
248 "MOVE L,L ",
249 "MOVE H,L ",
250 "MOVE M,L ",
251
252 "ILLEGAL ",
253 "ILLEGAL ",
254 "ILLEGAL ",
255 "SBIA # ",
256 "SBIB # ",
257 "CPIA # ",
258 "CPIB # ",
259 "ORIA # ",
260 "ORIB # ",
261 "ILLEGAL ",
262 "STOS (ind) ",
263 "MOVE A,H ",
264 "MOVE B,H ",
265 "MOVE L,H ",
266 "MOVE H,H ",
267 "MOVE M,H ",
268
269 "INC abs ",
270 "DEC abs ",
271 "RRC abs ",
272 "RLC abs ",
273 "SAL abs ",
274 "SAR abs ",
275 "LSR abs ",
276 "COM abs ",
277 "ROL abs ",
278 "RR abs ",
279 "STOS (ind,X) ",
280 "MOVE A,M ",
281 "MOVE B,M ",
282 "MOVE L,M ",
283 "MOVE H,M ",
284 "MOVE -,- ",
285
286 "INC abs,X ",
287 "DEC abs,X ",
288 "RRC abs,X ",
289 "RLC abs,X ",
290 "SAL abs,X ",
291 "SAR abs,X ",
292 "LSR abs,X ",
293 "COM abs,X ",
294 "ROL abs,X ",
295 "RR abs,X ",
296 "STORA abs ",
297 "STORB abs ",
298 "STOX abs ",
299 "STOY abs ",
300 "PUSH ,A ",
301 "POP A, ",
302
303 "INC abs,Y ",
304 "DEC abs,Y ",
305 "RRC abs,Y ",
306 "RLC abs,Y ",
307 "SAL abs,Y ",
308 "SAR abs,Y ",
309 "LSR abs,Y ",
310 "COM abs,Y ",
311 "ROL abs,Y ",
312 "RR abs,Y ",
313 "STORA abs,X ",
314 "STORB abs,X ",
315 "STOX abs,X ",
316 "STOY abs,X ",
317 "PUSH ,B ",
318 "POP B, ",
319
320 "INCA A,A ",
321 "DECA A,A ",
322 "RRCA A,A ",
323 "RLCA A,A ",
324 "SALA A,A ",
325 "SARA A,A ",
326 "LSRA A,A ",
327 "COMA A,A ",
328 "ROLA A,A ",
329 "RRA A,A ",
330 "STORA abs,Y ",
331 "STORB abs,Y ",
332 "STOX abs,Y ",
333 "STOY abs,Y ",
334 "PUSH ,s ",
335 "POP s, ",
336
337 "INCB B,B ",
338 "DECB B,B ",
339 "RRCB B,B ",
340 "RLCB B,B ",
341 "SALB B,B ",
342 "SARB B,B ",
343 "LSRB B,B ",
344 "COMB B,B ",
345 "ROLB B,B ",
346 "RRB B,B ",
347 "STORA (ind) ",
348 "STORB (ind) ",
349 "STOX (ind) ",
350 "STOY (ind) ",
351 "PUSH ,L ",
352 "POP L, ",
353
354 "CAY impl ",
355 "MYA impl ",
356 "CSA impl ",
357 "ABA impl ",
358 "SBA impl ",
359 "AAB impl ",
360 "SAB impl ",
361 "ADCP A,L ",
362 "SBCP A,L ",
363 "XCHG A,L ",
364 "STORA (ind,X)",
365 "STORB (ind,X)",
366 "STOX (ind,X) ",
367 "STOY (ind,X) ",
368 "PUSH ,H ",
369 "POP H, ",
370
371};
372
373////////////////////////////////////////////////////////////////////////////////
374// Simulator/Emulator (Start) //
375////////////////////////////////////////////////////////////////////////////////
376
377BYTE fetch()
378{
379 BYTE byte = 0;
380
381 if ((ProgramCounter >= 0) && (ProgramCounter <= MEMORY_SIZE))
382 {
383 memory_in_range = true;
384 byte = Memory[ProgramCounter];
385 ProgramCounter++;
386 }
387 else
388 {
389 memory_in_range = false;
390 }
391 return byte;
392}
393void set_flag_n(BYTE inReg) {
394 BYTE reg;
395 reg = inReg;
396
397 if ((reg & 0x80) != 0) // msbit set
398 {
399 Flags = Flags | FLAG_N;
400 }
401 else
402 {
403 Flags = Flags & (0xFF - FLAG_N);
404 }
405}
406
407void set_flag_z(BYTE inReg) {
408 BYTE reg;
409 reg = inReg;
410
411 if (reg == 0) // msbit set
412 {
413 Flags = Flags | FLAG_Z;
414 }
415 else
416 {
417 Flags = Flags & (0xFF - FLAG_Z);
418 }
419}
420
421
422void Group_1(BYTE opcode) {
423 BYTE LB = 0;
424 BYTE HB = 0;
425 WORD address = 0;
426 WORD data = 0;
427 WORD temp_word = 0;
428
429 // added these 21 nov
430
431 BYTE param1 = 0;
432 BYTE param2 = 0;
433
434 switch (opcode) {
435 case 0x0A: //LDAA Immidiate
436 data = fetch();
437 Registers[REGISTER_A] = data;
438 break;
439 case 0x1A: //LDAA Absolute
440 HB = fetch();
441 LB = fetch();
442 address += (WORD)((WORD)HB << 8) + LB;
443 if (address >= 0 && address < MEMORY_SIZE) {
444 Registers[REGISTER_A] = Memory[address];
445 }
446 break;
447 case 0x2A: //LDAA Absolute with Index X
448 address += Index_Registers[REGISTER_X];
449 HB = fetch();
450 LB = fetch();
451 address += (WORD)((WORD)HB << 8) + LB;
452 if (address >= 0 && address < MEMORY_SIZE) {
453 Registers[REGISTER_A] = Memory[address];
454 }
455 break;
456 case 0x3A: //LDAA Absolute with Index Y
457 address += Index_Registers[REGISTER_Y];
458 HB = fetch();
459 LB = fetch();
460 address += (WORD)((WORD)HB << 8) + LB;
461 if (address >= 0 && address < MEMORY_SIZE) {
462 Registers[REGISTER_A] = Memory[address];
463 }
464 break;
465 case 0x4A: //LDAA Indirect
466 HB = fetch();
467 LB = fetch();
468 address = (WORD)((WORD)HB << 8) + LB;
469 HB = Memory[address];
470 LB = Memory[address + 1];
471 address = (WORD)((WORD)HB << 8) + LB;
472 if (address >= 0 && address < MEMORY_SIZE) {
473 Registers[REGISTER_A] = Memory[address];
474 }
475 break;
476 case 0x5A: //LDAA Indirect with Index X
477 HB = fetch();
478 LB = fetch();
479 address = (WORD)((WORD)HB << 8) + LB;
480 HB = Memory[address];
481 LB = Memory[address + 1];
482 address = (WORD)((WORD)HB << 8) + LB;
483 address += Index_Registers[REGISTER_X];
484 if (address >= 0 && address < MEMORY_SIZE) {
485 Registers[REGISTER_A] = Memory[address];
486 }
487 break;
488 case 0x0B: //LDAB Immidiate
489 data = fetch();
490 Registers[REGISTER_B] = data;
491 break;
492 case 0x1B: //LDAB Absolute
493 HB = fetch();
494 LB = fetch();
495 address += (WORD)((WORD)HB << 8) + LB;
496 if (address >= 0 && address < MEMORY_SIZE) {
497 Registers[REGISTER_B] = Memory[address];
498 }
499 break;
500 case 0x2B: //LDAB Absolute with Index X
501 address += Index_Registers[REGISTER_X];
502 HB = fetch();
503 LB = fetch();
504 address += (WORD)((WORD)HB << 8) + LB;
505 if (address >= 0 && address < MEMORY_SIZE) {
506 Registers[REGISTER_B] = Memory[address];
507 }
508 break;
509 case 0x3B: //LDAB Absolute with Index Y
510 address += Index_Registers[REGISTER_Y];
511 HB = fetch();
512 LB = fetch();
513 address += (WORD)((WORD)HB << 8) + LB;
514 if (address >= 0 && address < MEMORY_SIZE) {
515 Registers[REGISTER_B] = Memory[address];
516 }
517 break;
518 case 0x4B: //LDAB Indirect
519 HB = fetch();
520 LB = fetch();
521 address = (WORD)((WORD)HB << 8) + LB;
522 HB = Memory[address];
523 LB = Memory[address + 1];
524 address = (WORD)((WORD)HB << 8) + LB;
525 if (address >= 0 && address < MEMORY_SIZE) {
526 Registers[REGISTER_B] = Memory[address];
527 }
528 break;
529 case 0x5B: //LDAB Indirect with Index X
530 HB = fetch();
531 LB = fetch();
532 address = (WORD)((WORD)HB << 8) + LB;
533 HB = Memory[address];
534 LB = Memory[address + 1];
535 address = (WORD)((WORD)HB << 8) + LB;
536 address += Index_Registers[REGISTER_X];
537 if (address >= 0 && address < MEMORY_SIZE) {
538 Registers[REGISTER_B] = Memory[address];
539 }
540 break;
541 case 0xBA: //STORA Absolute
542 HB = fetch();
543 LB = fetch();
544 address += (WORD)((WORD)HB << 8) + LB;
545 if (address >= 0 && address < MEMORY_SIZE) {
546 Memory[address] = Registers[REGISTER_A];
547 }
548 break;
549 case 0xCA: //STORA Absolute with Index X
550 address += Index_Registers[REGISTER_X];
551 HB = fetch();
552 LB = fetch();
553 address += (WORD)((WORD)HB << 8) + LB;
554 if (address >= 0 && address < MEMORY_SIZE) {
555 Memory[address] = Registers[REGISTER_A];
556 }
557 break;
558 case 0xDA: //STORA Absolute with Index Y
559 address += Index_Registers[REGISTER_Y];
560 HB = fetch();
561 LB = fetch();
562 address += (WORD)((WORD)HB << 8) + LB;
563 if (address >= 0 && address < MEMORY_SIZE) {
564 Memory[address] = Registers[REGISTER_A];
565 }
566 break;
567 case 0xEA: //STORA Indirect
568 HB = fetch();
569 LB = fetch();
570 address = (WORD)((WORD)HB << 8) + LB;
571 HB = Memory[address];
572 LB = Memory[address + 1];
573 address = (WORD)((WORD)HB << 8) + LB;
574 if (address >= 0 && address < MEMORY_SIZE) {
575 Memory[address] = Registers[REGISTER_A];
576 }
577 break;
578 case 0xFA: //STORA Indirect with Index X
579 HB = fetch();
580 LB = fetch();
581 address = (WORD)((WORD)HB << 8) + LB;
582 HB = Memory[address];
583 LB = Memory[address + 1];
584 address = (WORD)((WORD)HB << 8) + LB;
585 address += Index_Registers[REGISTER_X];
586 if (address >= 0 && address < MEMORY_SIZE) {
587 Memory[address] = Registers[REGISTER_A];
588 }
589 break;
590 case 0xBB: //STORB Absolute
591 HB = fetch();
592 LB = fetch();
593 address += (WORD)((WORD)HB << 8) + LB;
594 if (address >= 0 && address < MEMORY_SIZE) {
595 Memory[address] = Registers[REGISTER_B];
596 }
597 break;
598 case 0xCB: //STORB Absolute with Index X
599 address += Index_Registers[REGISTER_X];
600 HB = fetch();
601 LB = fetch();
602 address += (WORD)((WORD)HB << 8) + LB;
603 if (address >= 0 && address < MEMORY_SIZE) {
604 Memory[address] = Registers[REGISTER_B];
605 }
606 break;
607 case 0xDB: //STORB Absolute with Index Y
608 address += Index_Registers[REGISTER_Y];
609 HB = fetch();
610 LB = fetch();
611 address += (WORD)((WORD)HB << 8) + LB;
612 if (address >= 0 && address < MEMORY_SIZE) {
613 Memory[address] = Registers[REGISTER_B];
614 }
615 break;
616 case 0xEB: //STORB Indirect
617 HB = fetch();
618 LB = fetch();
619 address = (WORD)((WORD)HB << 8) + LB;
620 HB = Memory[address];
621 LB = Memory[address + 1];
622 address = (WORD)((WORD)HB << 8) + LB;
623 if (address >= 0 && address < MEMORY_SIZE) {
624 Memory[address] = Registers[REGISTER_B];
625 }
626 break;
627 case 0xFB: //STORB Indirect with Index X
628 HB = fetch();
629 LB = fetch();
630 address = (WORD)((WORD)HB << 8) + LB;
631 HB = Memory[address];
632 LB = Memory[address + 1];
633 address = (WORD)((WORD)HB << 8) + LB;
634 address += Index_Registers[REGISTER_X];
635 if (address >= 0 && address < MEMORY_SIZE) {
636 Memory[address] = Registers[REGISTER_B];
637 }
638 break;
639 case 0xBC: //STOX Absolute
640 HB = fetch();
641 LB = fetch();
642 address += (WORD)((WORD)HB << 8) + LB;
643 if (address >= 0 && address < MEMORY_SIZE) {
644 Memory[address] = Registers[REGISTER_X];
645 }
646 break;
647 case 0xCC: //STOX Absolute with Index X
648 address += Index_Registers[REGISTER_X];
649 HB = fetch();
650 LB = fetch();
651 address += (WORD)((WORD)HB << 8) + LB;
652 if (address >= 0 && address < MEMORY_SIZE) {
653 Memory[address] = Registers[REGISTER_X];
654 }
655 break;
656 case 0xDC: //STOX Absolute with Index Y
657 address += Index_Registers[REGISTER_Y];
658 HB = fetch();
659 LB = fetch();
660 address += (WORD)((WORD)HB << 8) + LB;
661 if (address >= 0 && address < MEMORY_SIZE) {
662 Memory[address] = Registers[REGISTER_X];
663 }
664 break;
665 case 0xEC: //STOX Indirect
666 HB = fetch();
667 LB = fetch();
668 address = (WORD)((WORD)HB << 8) + LB;
669 HB = Memory[address];
670 LB = Memory[address + 1];
671 address = (WORD)((WORD)HB << 8) + LB;
672 if (address >= 0 && address < MEMORY_SIZE) {
673 Memory[address] = Registers[REGISTER_X];
674 }
675 break;
676 case 0xFC: //STOX Indirect with Index X
677 HB = fetch();
678 LB = fetch();
679 address = (WORD)((WORD)HB << 8) + LB;
680 HB = Memory[address];
681 LB = Memory[address + 1];
682 address = (WORD)((WORD)HB << 8) + LB;
683 address += Index_Registers[REGISTER_X];
684 if (address >= 0 && address < MEMORY_SIZE) {
685 Memory[address] = Registers[REGISTER_X];
686 }
687 break;
688 case 0xBD: //STOY Absolute
689 HB = fetch();
690 LB = fetch();
691 address += (WORD)((WORD)HB << 8) + LB;
692 if (address >= 0 && address < MEMORY_SIZE) {
693 Memory[address] = Registers[REGISTER_Y];
694 }
695 break;
696 case 0xCD: //STOY Absolute with Index X
697 address += Index_Registers[REGISTER_X];
698 HB = fetch();
699 LB = fetch();
700 address += (WORD)((WORD)HB << 8) + LB;
701 if (address >= 0 && address < MEMORY_SIZE) {
702 Memory[address] = Registers[REGISTER_Y];
703 }
704 break;
705 case 0xDD: //STOY Absolute with Index Y
706 address += Index_Registers[REGISTER_Y];
707 HB = fetch();
708 LB = fetch();
709 address += (WORD)((WORD)HB << 8) + LB;
710 if (address >= 0 && address < MEMORY_SIZE) {
711 Memory[address] = Registers[REGISTER_Y];
712 }
713 break;
714 case 0xED: //STOY Indirect
715 HB = fetch();
716 LB = fetch();
717 address = (WORD)((WORD)HB << 8) + LB;
718 HB = Memory[address];
719 LB = Memory[address + 1];
720 address = (WORD)((WORD)HB << 8) + LB;
721 if (address >= 0 && address < MEMORY_SIZE) {
722 Memory[address] = Registers[REGISTER_Y];
723 }
724 break;
725 case 0xFD: //STOY Indirect with Index X
726 HB = fetch();
727 LB = fetch();
728 address = (WORD)((WORD)HB << 8) + LB;
729 HB = Memory[address];
730 LB = Memory[address + 1];
731 address = (WORD)((WORD)HB << 8) + LB;
732 address += Index_Registers[REGISTER_X];
733 if (address >= 0 && address < MEMORY_SIZE) {
734 Memory[address] = Registers[REGISTER_Y];
735 }
736 break;
737 case 0xF2: //CSA
738 Registers[REGISTER_A] = Flags;
739 break;
740
741 case 0x1C: //MVI Loads Memory into register L
742 data = fetch();
743 Registers[REGISTER_L] = data;
744 break;
745 case 0x1D: //MVI Loads Memory into register L
746 data = fetch();
747 Registers[REGISTER_H] = data;
748 break;
749 case 0x20: // LODS Immediate
750 data = fetch();
751 StackPointer = data << 8; StackPointer += fetch();
752 break;
753 case 0x30: // LODS Immediate
754 HB = fetch();
755 LB = fetch();
756 address += (WORD)((WORD)HB << 8) + LB;
757 if (address >= 0 && address < MEMORY_SIZE) {
758 StackPointer = (WORD)Memory[address] << 8;
759 StackPointer += Memory[address + 1];
760 }
761 break;
762
763 case 0x31: // ADC A:L
764 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_L];
765 if ((Flags & FLAG_C) != 0)
766 {
767 temp_word++;
768 }
769 if (temp_word >= 0x100)
770 {
771 //Set carry flag
772 Flags = Flags | FLAG_C;
773 }
774 else
775 {
776 //Clear carry flag
777 Flags = Flags & (0xFF - FLAG_C);
778 }
779 set_flag_n((BYTE)temp_word);
780 set_flag_z((BYTE)temp_word);
781 Registers[REGISTER_A] = (BYTE)temp_word;
782 break;
783 case 0x41: // ADC A:H
784 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_H];
785 if ((Flags & FLAG_C) != 0)
786 {
787 temp_word++;
788 }
789 if (temp_word >= 0x100)
790 {
791 //Set carry flag
792 Flags = Flags | FLAG_C;
793 }
794 else
795 {
796 //Clear carry flag
797 Flags = Flags & (0xFF - FLAG_C);
798 }
799 set_flag_n((BYTE)temp_word);
800 set_flag_z((BYTE)temp_word);
801 Registers[REGISTER_A] = (BYTE)temp_word;
802 break;
803 case 0x51: // ADC A:M
804 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_M];
805 if ((Flags & FLAG_C) != 0)
806 {
807 temp_word++;
808 }
809 if (temp_word >= 0x100)
810 {
811 //Set carry flag
812 Flags = Flags | FLAG_C;
813 }
814 else
815 {
816 //Clear carry flag
817 Flags = Flags & (0xFF - FLAG_C);
818 }
819 set_flag_n((BYTE)temp_word);
820 set_flag_z((BYTE)temp_word);
821 Registers[REGISTER_A] = (BYTE)temp_word;
822 break;
823 case 0x61: // ADC B:L
824 temp_word = (WORD)Registers[REGISTER_B] + (WORD)Registers[REGISTER_L];
825 if ((Flags & FLAG_C) != 0)
826 {
827 temp_word++;
828 }
829 if (temp_word >= 0x100)
830 {
831 //Set carry flag
832 Flags = Flags | FLAG_C;
833 }
834 else
835 {
836 //Clear carry flag
837 Flags = Flags & (0xFF - FLAG_C);
838 }
839 set_flag_n((BYTE)temp_word);
840 set_flag_z((BYTE)temp_word);
841 Registers[REGISTER_B] = (BYTE)temp_word;
842 break;
843 case 0x71: // ADC B:H
844 temp_word = (WORD)Registers[REGISTER_B] + (WORD)Registers[REGISTER_H];
845 if ((Flags & FLAG_C) != 0)
846 {
847 temp_word++;
848 }
849 if (temp_word >= 0x100)
850 {
851 //Set carry flag
852 Flags = Flags | FLAG_C;
853 }
854 else
855 {
856 //Clear carry flag
857 Flags = Flags & (0xFF - FLAG_C);
858 }
859 set_flag_n((BYTE)temp_word);
860 set_flag_z((BYTE)temp_word);
861 Registers[REGISTER_B] = (BYTE)temp_word;
862 break;
863 case 0x81: // ADC B:M
864 temp_word = (WORD)Registers[REGISTER_B] + (WORD)Registers[REGISTER_M];
865 if ((Flags & FLAG_C) != 0)
866 {
867 temp_word++;
868 }
869 if (temp_word >= 0x100)
870 {
871 //Set carry flag
872 Flags = Flags | FLAG_C;
873 }
874 else
875 {
876 //Clear carry flag
877 Flags = Flags & (0xFF - FLAG_C);
878 }
879 set_flag_n((BYTE)temp_word);
880 set_flag_z((BYTE)temp_word);
881 Registers[REGISTER_B] = (BYTE)temp_word;
882 break;
883
884
885
886 case 0x32: // SBC A:L
887 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_L];
888 if ((Flags & FLAG_C) != 0)
889 {
890 temp_word--;
891 }
892 if (temp_word >= 0x100)
893 {
894 //Set carry flag
895 Flags = Flags | FLAG_C;
896 }
897 else
898 {
899 //Clear carry flag
900 Flags = Flags & (0xFF - FLAG_C);
901 }
902 set_flag_n((BYTE)temp_word);
903 set_flag_z((BYTE)temp_word);
904 Registers[REGISTER_A] = (BYTE)temp_word;
905 break;
906 case 0x42: // SBC A:H
907 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_H];
908 if ((Flags & FLAG_C) != 0)
909 {
910 temp_word--;
911 }
912 if (temp_word >= 0x100)
913 {
914 //Set carry flag
915 Flags = Flags | FLAG_C;
916 }
917 else
918 {
919 //Clear carry flag
920 Flags = Flags & (0xFF - FLAG_C);
921 }
922 set_flag_n((BYTE)temp_word);
923 set_flag_z((BYTE)temp_word);
924 Registers[REGISTER_A] = (BYTE)temp_word;
925 break;
926 case 0x52: // SBC A:M
927 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_M];
928 if ((Flags & FLAG_C) != 0)
929 {
930 temp_word--;
931 }
932 if (temp_word >= 0x100)
933 {
934 //Set carry flag
935 Flags = Flags | FLAG_C;
936 }
937 else
938 {
939 //Clear carry flag
940 Flags = Flags & (0xFF - FLAG_C);
941 }
942 set_flag_n((BYTE)temp_word);
943 set_flag_z((BYTE)temp_word);
944 Registers[REGISTER_A] = (BYTE)temp_word;
945 break;
946 case 0x62: // SBC B:L
947 temp_word = (WORD)Registers[REGISTER_B] - (WORD)Registers[REGISTER_L];
948 if ((Flags & FLAG_C) != 0)
949 {
950 temp_word--;
951 }
952 if (temp_word >= 0x100)
953 {
954 //Set carry flag
955 Flags = Flags | FLAG_C;
956 }
957 else
958 {
959 //Clear carry flag
960 Flags = Flags & (0xFF - FLAG_C);
961 }
962 set_flag_n((BYTE)temp_word);
963 set_flag_z((BYTE)temp_word);
964 Registers[REGISTER_B] = (BYTE)temp_word;
965 break;
966 case 0x72: // SBC B:H
967 temp_word = (WORD)Registers[REGISTER_B] - (WORD)Registers[REGISTER_H];
968 if ((Flags & FLAG_C) != 0)
969 {
970 temp_word--;
971 }
972 if (temp_word >= 0x100)
973 {
974 //Set carry flag
975 Flags = Flags | FLAG_C;
976 }
977 else
978 {
979 //Clear carry flag
980 Flags = Flags & (0xFF - FLAG_C);
981 }
982 set_flag_n((BYTE)temp_word);
983 set_flag_z((BYTE)temp_word);
984 Registers[REGISTER_B] = (BYTE)temp_word;
985 break;
986 case 0x82: // SBC B:M
987 temp_word = (WORD)Registers[REGISTER_B] - (WORD)Registers[REGISTER_M];
988 if ((Flags & FLAG_C) != 0)
989 {
990 temp_word--;
991 }
992 if (temp_word >= 0x100)
993 {
994 //Set carry flag
995 Flags = Flags | FLAG_C;
996 }
997 else
998 {
999 //Clear carry flag
1000 Flags = Flags & (0xFF - FLAG_C);
1001 }
1002 set_flag_n((BYTE)temp_word);
1003 set_flag_z((BYTE)temp_word);
1004 Registers[REGISTER_B] = (BYTE)temp_word;
1005 break;
1006
1007 case 0x33: // ADD A:L
1008 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_L];
1009
1010 if (temp_word >= 0x100)
1011 {
1012 Flags = Flags | FLAG_C; //Set
1013 }
1014 else
1015 {
1016 //Clear carry flag
1017 Flags = Flags & (0xFF - FLAG_C);
1018 }
1019
1020
1021 set_flag_n((BYTE)temp_word);
1022 set_flag_z((BYTE)temp_word);
1023 Registers[REGISTER_A] = (BYTE)temp_word;
1024 break;
1025
1026 case 0x43: // ADD A:H
1027 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_H];
1028
1029 if (temp_word >= 0x100)
1030 {
1031 Flags = Flags | FLAG_C; //Set
1032 }
1033 else
1034 {
1035 //Clear carry flag
1036 Flags = Flags & (0xFF - FLAG_C);
1037 }
1038
1039 set_flag_n((BYTE)temp_word);
1040 set_flag_z((BYTE)temp_word);
1041 Registers[REGISTER_A] = (BYTE)temp_word;
1042 break;
1043
1044 case 0x53: // ADD A:M
1045 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_M];
1046
1047 if (temp_word >= 0x100)
1048 {
1049 Flags = Flags | FLAG_C; //Set
1050 }
1051 else
1052 {
1053 //Clear carry flag
1054 Flags = Flags & (0xFF - FLAG_C);
1055 }
1056
1057 set_flag_n((BYTE)temp_word);
1058 set_flag_z((BYTE)temp_word);
1059 Registers[REGISTER_A] = (BYTE)temp_word;
1060 break;
1061
1062 case 0x63: // ADD B:L
1063 temp_word = (WORD)Registers[REGISTER_B] + (WORD)Registers[REGISTER_L];
1064
1065 if (temp_word >= 0x100)
1066 {
1067 Flags = Flags | FLAG_C; //Set
1068 }
1069 else
1070 {
1071 //Clear carry flag
1072 Flags = Flags & (0xFF - FLAG_C);
1073 }
1074
1075 set_flag_n((BYTE)temp_word);
1076 set_flag_z((BYTE)temp_word);
1077 Registers[REGISTER_B] = (BYTE)temp_word;
1078 break;
1079
1080 case 0x73: // ADD B:H
1081 temp_word = (WORD)Registers[REGISTER_B] + (WORD)Registers[REGISTER_H];
1082
1083 if (temp_word >= 0x100)
1084 {
1085 Flags = Flags | FLAG_C; //Set
1086 }
1087 else
1088 {
1089 //Clear carry flag
1090 Flags = Flags & (0xFF - FLAG_C);
1091 }
1092
1093 set_flag_n((BYTE)temp_word);
1094 set_flag_z((BYTE)temp_word);
1095 Registers[REGISTER_B] = (BYTE)temp_word;
1096 break;
1097 case 0x83: // ADD B:M
1098 temp_word = (WORD)Registers[REGISTER_B] + (WORD)Registers[REGISTER_M];
1099
1100 if (temp_word >= 0x100)
1101 {
1102 Flags = Flags | FLAG_C; //Set
1103 }
1104 else
1105 {
1106 //Clear carry flag
1107 Flags = Flags & (0xFF - FLAG_C);
1108 }
1109
1110 set_flag_n((BYTE)temp_word);
1111 set_flag_z((BYTE)temp_word);
1112 Registers[REGISTER_B] = (BYTE)temp_word;
1113 break;
1114
1115 case 0x34: // SUB A:L
1116 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_L];
1117
1118 if (temp_word >= 0x100)
1119 {
1120 Flags = Flags | FLAG_C; //Set
1121 }
1122 else
1123 {
1124 //Clear carry flag
1125 Flags = Flags & (0xFF - FLAG_C);
1126 }
1127
1128 set_flag_n((BYTE)temp_word);
1129 set_flag_z((BYTE)temp_word);
1130 Registers[REGISTER_A] = (BYTE)temp_word;
1131 break;
1132
1133 case 0x44: // SUB A:H
1134 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_H];
1135
1136 if (temp_word >= 0x100)
1137 {
1138 Flags = Flags | FLAG_C; //Set
1139 }
1140 else
1141 {
1142 //Clear carry flag
1143 Flags = Flags & (0xFF - FLAG_C);
1144 }
1145
1146 set_flag_n((BYTE)temp_word);
1147 set_flag_z((BYTE)temp_word);
1148 Registers[REGISTER_A] = (BYTE)temp_word;
1149 break;
1150
1151 case 0x54: // SUB A:M
1152 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_M];
1153
1154 if (temp_word >= 0x100)
1155 {
1156 Flags = Flags | FLAG_C; //Set
1157 }
1158 else
1159 {
1160 //Clear carry flag
1161 Flags = Flags & (0xFF - FLAG_C);
1162 }
1163
1164 set_flag_n((BYTE)temp_word);
1165 set_flag_z((BYTE)temp_word);
1166 Registers[REGISTER_A] = (BYTE)temp_word;
1167 break;
1168
1169 case 0x64: // SUB B:L
1170 temp_word = (WORD)Registers[REGISTER_B] - (WORD)Registers[REGISTER_L];
1171
1172 if (temp_word >= 0x100)
1173 {
1174 Flags = Flags | FLAG_C; //Set
1175 }
1176 else
1177 {
1178 //Clear carry flag
1179 Flags = Flags & (0xFF - FLAG_C);
1180 }
1181
1182 set_flag_n((BYTE)temp_word);
1183 set_flag_z((BYTE)temp_word);
1184 Registers[REGISTER_B] = (BYTE)temp_word;
1185 break;
1186
1187 case 0x74: // SUB B:H
1188 temp_word = (WORD)Registers[REGISTER_B] - (WORD)Registers[REGISTER_H];
1189
1190 if (temp_word >= 0x100)
1191 {
1192 Flags = Flags | FLAG_C; //Set
1193 }
1194 else
1195 {
1196 //Clear carry flag
1197 Flags = Flags & (0xFF - FLAG_C);
1198 }
1199
1200 set_flag_n((BYTE)temp_word);
1201 set_flag_z((BYTE)temp_word);
1202 Registers[REGISTER_B] = (BYTE)temp_word;
1203 break;
1204
1205 case 0x84: // SUB B:M
1206 temp_word = (WORD)Registers[REGISTER_B] - (WORD)Registers[REGISTER_M];
1207
1208 if (temp_word >= 0x100)
1209 {
1210 Flags = Flags | FLAG_C; //Set
1211 }
1212 else
1213 {
1214 //Clear carry flag
1215 Flags = Flags & (0xFF - FLAG_C);
1216 }
1217
1218 set_flag_n((BYTE)temp_word);
1219 set_flag_z((BYTE)temp_word);
1220 Registers[REGISTER_B] = (BYTE)temp_word;
1221 break;
1222
1223
1224 case 0x35: // CMP A:L
1225 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_L];
1226 if (temp_word >= 0x100)
1227 {
1228 Flags = Flags | FLAG_C; //Set
1229 }
1230 else
1231 {
1232 //Clear carry flag
1233 Flags = Flags & (0xFF - FLAG_C);
1234 }
1235 set_flag_n((BYTE)temp_word);
1236 set_flag_z((BYTE)temp_word);
1237 break;
1238 case 0x45: // CMP A:H
1239 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_H];
1240 if (temp_word >= 0x100)
1241 {
1242 Flags = Flags | FLAG_C; //Set
1243 }
1244 else
1245 {
1246 //Clear carry flag
1247 Flags = Flags & (0xFF - FLAG_C);
1248 }
1249 set_flag_n((BYTE)temp_word);
1250 set_flag_z((BYTE)temp_word);
1251 break;
1252
1253 case 0x55: // CMP A:M
1254 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_M];
1255 if (temp_word >= 0x100)
1256 {
1257 Flags = Flags | FLAG_C; //Set
1258 }
1259 else
1260 {
1261 //Clear carry flag
1262 Flags = Flags & (0xFF - FLAG_C);
1263 }
1264 set_flag_n((BYTE)temp_word);
1265 set_flag_z((BYTE)temp_word);
1266 break;
1267
1268 case 0x65: // CMP B:L
1269 temp_word = (WORD)Registers[REGISTER_B] - (WORD)Registers[REGISTER_L];
1270 if (temp_word >= 0x100)
1271 {
1272 Flags = Flags | FLAG_C; //Set
1273 }
1274 else
1275 {
1276 //Clear carry flag
1277 Flags = Flags & (0xFF - FLAG_C);
1278 }
1279 set_flag_n((BYTE)temp_word);
1280 set_flag_z((BYTE)temp_word);
1281 break;
1282
1283 case 0x75: // CMP B:H
1284 temp_word = (WORD)Registers[REGISTER_B] - (WORD)Registers[REGISTER_H];
1285 if (temp_word >= 0x100)
1286 {
1287 Flags = Flags | FLAG_C; //Set
1288 }
1289 else
1290 {
1291 //Clear carry flag
1292 Flags = Flags & (0xFF - FLAG_C);
1293 }
1294 set_flag_n((BYTE)temp_word);
1295 set_flag_z((BYTE)temp_word);
1296 break;
1297
1298 case 0x85: // CMP B:M
1299 temp_word = (WORD)Registers[REGISTER_B] - (WORD)Registers[REGISTER_M];
1300 if (temp_word >= 0x100)
1301 {
1302 Flags = Flags | FLAG_C; //Set
1303 }
1304 else
1305 {
1306 //Clear carry flag
1307 Flags = Flags & (0xFF - FLAG_C);
1308 }
1309 set_flag_n((BYTE)temp_word);
1310 set_flag_z((BYTE)temp_word);
1311 break;
1312
1313 case 0x36: // OR A:L
1314 temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_L];
1315
1316 set_flag_n((BYTE)temp_word);
1317 set_flag_z((BYTE)temp_word);
1318 Registers[REGISTER_A] = (BYTE)temp_word;
1319 break;
1320
1321 case 0x46: // OR A:H
1322 temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_H];
1323
1324 set_flag_n((BYTE)temp_word);
1325 set_flag_z((BYTE)temp_word);
1326 Registers[REGISTER_A] = (BYTE)temp_word;
1327 break;
1328
1329 case 0x56: // COR A:M
1330 temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_M];
1331
1332 set_flag_n((BYTE)temp_word);
1333 set_flag_z((BYTE)temp_word);
1334 Registers[REGISTER_A] = (BYTE)temp_word;
1335 break;
1336
1337 case 0x66: // OR B:L
1338 temp_word = (WORD)Registers[REGISTER_B] | (WORD)Registers[REGISTER_L];
1339
1340 set_flag_n((BYTE)temp_word);
1341 set_flag_z((BYTE)temp_word);
1342 Registers[REGISTER_B] = (BYTE)temp_word;
1343 break;
1344
1345 case 0x76: // OR B:H
1346 temp_word = (WORD)Registers[REGISTER_B] | (WORD)Registers[REGISTER_H];
1347
1348 set_flag_n((BYTE)temp_word);
1349 set_flag_z((BYTE)temp_word);
1350 Registers[REGISTER_B] = (BYTE)temp_word;
1351 break;
1352
1353 case 0x86: // OR B:M
1354 temp_word = (WORD)Registers[REGISTER_B] | (WORD)Registers[REGISTER_M];
1355
1356 set_flag_n((BYTE)temp_word);
1357 set_flag_z((BYTE)temp_word);
1358 Registers[REGISTER_B] = (BYTE)temp_word;
1359 break;
1360
1361 case 0x37: // AND A:L
1362 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_L];
1363
1364 set_flag_n((BYTE)temp_word);
1365 set_flag_z((BYTE)temp_word);
1366 Registers[REGISTER_A] = (BYTE)temp_word;
1367 break;
1368
1369 case 0x47: // AND A:H
1370 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_H];
1371
1372 set_flag_n((BYTE)temp_word);
1373 set_flag_z((BYTE)temp_word);
1374 Registers[REGISTER_A] = (BYTE)temp_word;
1375 break;
1376
1377 case 0x57: // AND A:M
1378 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_M];
1379
1380 set_flag_n((BYTE)temp_word);
1381 set_flag_z((BYTE)temp_word);
1382 Registers[REGISTER_A] = (BYTE)temp_word;
1383 break;
1384
1385 case 0x67: // AND B:L
1386 temp_word = (WORD)Registers[REGISTER_B] & (WORD)Registers[REGISTER_L];
1387
1388 set_flag_n((BYTE)temp_word);
1389 set_flag_z((BYTE)temp_word);
1390 Registers[REGISTER_B] = (BYTE)temp_word;
1391 break;
1392
1393 case 0x77: // AND B:H
1394 temp_word = (WORD)Registers[REGISTER_B] & (WORD)Registers[REGISTER_H];
1395
1396 set_flag_n((BYTE)temp_word);
1397 set_flag_z((BYTE)temp_word);
1398 Registers[REGISTER_B] = (BYTE)temp_word;
1399 break;
1400
1401 case 0x87: // AND B:M
1402 temp_word = (WORD)Registers[REGISTER_B] & (WORD)Registers[REGISTER_M];
1403
1404 set_flag_n((BYTE)temp_word);
1405 set_flag_z((BYTE)temp_word);
1406 Registers[REGISTER_B] = (BYTE)temp_word;
1407 break;
1408
1409 case 0x38: // XOR A:L
1410 temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_L];
1411
1412 set_flag_n((BYTE)temp_word);
1413 set_flag_z((BYTE)temp_word);
1414 Registers[REGISTER_A] = (BYTE)temp_word;
1415 break;
1416
1417 case 0x48: // OR A:H
1418 temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_H];
1419
1420 set_flag_n((BYTE)temp_word);
1421 set_flag_z((BYTE)temp_word);
1422 Registers[REGISTER_A] = (BYTE)temp_word;
1423 break;
1424
1425 case 0x58: // XOR A:M
1426 temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_M];
1427
1428 set_flag_n((BYTE)temp_word);
1429 set_flag_z((BYTE)temp_word);
1430 Registers[REGISTER_A] = (BYTE)temp_word;
1431 break;
1432
1433 case 0x68: // XOR B:L
1434 temp_word = (WORD)Registers[REGISTER_B] ^ (WORD)Registers[REGISTER_L];
1435
1436 set_flag_n((BYTE)temp_word);
1437 set_flag_z((BYTE)temp_word);
1438 Registers[REGISTER_B] = (BYTE)temp_word;
1439 break;
1440
1441 case 0x78: // XOR B:H
1442 temp_word = (WORD)Registers[REGISTER_B] ^ (WORD)Registers[REGISTER_H];
1443
1444 set_flag_n((BYTE)temp_word);
1445 set_flag_z((BYTE)temp_word);
1446 Registers[REGISTER_B] = (BYTE)temp_word;
1447 break;
1448
1449 case 0x88: // XOR B:M
1450 temp_word = (WORD)Registers[REGISTER_B] ^ (WORD)Registers[REGISTER_M];
1451
1452 set_flag_n((BYTE)temp_word);
1453 set_flag_z((BYTE)temp_word);
1454 Registers[REGISTER_B] = (BYTE)temp_word;
1455 break;
1456
1457 case 0x40: // LODS Absoulte with Index X
1458 address += Index_Registers[REGISTER_X];
1459 HB = fetch();
1460 LB = fetch();
1461 address += (WORD)((WORD)HB << 8) + LB;
1462 if (address >= 0 && address < MEMORY_SIZE) {
1463 StackPointer = (WORD)Memory[address] << 8;
1464 StackPointer += Memory[address + 1];
1465 }
1466 break;
1467 case 0x50: // LODS Absoulte with Index Y
1468 address += Index_Registers[REGISTER_Y];
1469 HB = fetch();
1470 LB = fetch();
1471 address += (WORD)((WORD)HB << 8) + LB;
1472 if (address >= 0 && address < MEMORY_SIZE) {
1473 StackPointer = (WORD)Memory[address] << 8;
1474 StackPointer += Memory[address + 1];
1475 }
1476 break;
1477 case 0x60: // LODS Indirect
1478 HB = fetch();
1479 LB = fetch();
1480 address = (WORD)((WORD)HB << 8) + LB;
1481 HB = Memory[address];
1482 LB = Memory[address + 1];
1483 address = (WORD)((WORD)HB << 8) + LB;
1484 if (address >= 0 && address < MEMORY_SIZE - 1) {
1485 StackPointer = (WORD)Memory[address] << 8;
1486 StackPointer += Memory[address + 1];
1487 }
1488 break;
1489 case 0x70: // LODS Indirect with Index X
1490 HB = fetch();
1491 LB = fetch();
1492 address = (WORD)((WORD)HB << 8) + LB;
1493 HB = Memory[address];
1494 LB = Memory[address + 1];
1495 address = (WORD)((WORD)HB << 8) + LB;
1496 address += Index_Registers[REGISTER_X];
1497 if (address >= 0 && address < MEMORY_SIZE - 1) {
1498 StackPointer = (WORD)Memory[address] << 8;
1499 StackPointer += Memory[address + 1];
1500 }
1501 break;
1502
1503 case 0x6A: //STOX Absolute
1504
1505 data = fetch();
1506 data = StackPointer << 8; StackPointer += fetch();
1507
1508 break;
1509
1510 case 0x7A: //STOX Absolute with Index X
1511
1512 HB = fetch();
1513 LB = fetch();
1514 address += (WORD)((WORD)HB << 8) + LB;
1515 if (address >= 0 && address < MEMORY_SIZE) {
1516 data = (WORD)StackPointer << 8;
1517 StackPointer += Memory[address + 1];
1518 }
1519
1520 break;
1521
1522 case 0x8A: //STOX Absolute with Index Y
1523
1524 address += Index_Registers[REGISTER_X];
1525 HB = fetch();
1526 LB = fetch();
1527 address += (WORD)((WORD)HB << 8) + LB;
1528 if (address >= 0 && address < MEMORY_SIZE) {
1529 StackPointer = (WORD)Memory[address] << 8;
1530 StackPointer += Memory[address + 1];
1531 }
1532
1533
1534 break;
1535
1536 case 0x9A: //STOX Indirect
1537
1538 address += Index_Registers[REGISTER_Y];
1539 HB = fetch();
1540 LB = fetch();
1541 address += (WORD)((WORD)HB << 8) + LB;
1542 if (address >= 0 && address < MEMORY_SIZE) {
1543 StackPointer = (WORD)Memory[address] << 8;
1544 StackPointer += Memory[address + 1];
1545 }
1546
1547
1548 break;
1549
1550 case 0xAA: //STOX Indirect with Index X
1551
1552 HB = fetch();
1553 LB = fetch();
1554 address = (WORD)((WORD)HB << 8) + LB;
1555 HB = Memory[address];
1556 LB = Memory[address + 1];
1557 address = (WORD)((WORD)HB << 8) + LB;
1558 address += Index_Registers[REGISTER_X];
1559 if (address >= 0 && address < MEMORY_SIZE - 1) {
1560 StackPointer = (WORD)Memory[address] << 8;
1561 StackPointer += Memory[address + 1];
1562 }
1563
1564 break;
1565
1566
1567
1568
1569
1570
1571
1572
1573 case 0x0E: //LDX Immidiate
1574 data = fetch();
1575 Registers[REGISTER_X] = data;
1576 break;
1577
1578 case 0x1E: //LDX absolute
1579 HB = fetch();
1580 LB = fetch();
1581 address += (WORD)((WORD)HB << 8) + LB;
1582 if (address >= 0 && address < MEMORY_SIZE) {
1583 Registers[REGISTER_X] = Memory[address];
1584 }
1585
1586 break;
1587
1588 case 0x2E: //LDX index x absolute
1589 address += Index_Registers[REGISTER_X];
1590 HB = fetch();
1591 LB = fetch();
1592 address += (WORD)((WORD)HB << 8) + LB;
1593 if (address >= 0 && address < MEMORY_SIZE) {
1594 Registers[REGISTER_X] = Memory[address];
1595 }
1596 break;
1597
1598 case 0x3E: //LDX index y absolute
1599 address += Index_Registers[REGISTER_Y];
1600 HB = fetch();
1601 LB = fetch();
1602 address += (WORD)((WORD)HB << 8) + LB;
1603 if (address >= 0 && address < MEMORY_SIZE) {
1604 Registers[REGISTER_X] = Memory[address];
1605 }
1606 break;
1607
1608 case 0x4E: //LDX indirect addressing
1609 HB = fetch();
1610 LB = fetch();
1611 address = (WORD)((WORD)HB << 8) + LB;
1612 HB = Memory[address];
1613 LB = Memory[address];
1614 address = (WORD)((WORD)HB << 8) + LB;
1615 if (address >= 0 && address < MEMORY_SIZE) {
1616 Registers[REGISTER_X] = Memory[address];
1617 }
1618 break;
1619
1620
1621 case 0x5E: //LDX indexed indrect adressing
1622 HB = fetch();
1623 LB = fetch();
1624 address = (WORD)((WORD)HB << 8) + LB;
1625 HB = Memory[address];
1626 LB = Memory[address + 1];
1627 address = (WORD)((WORD)HB << 8) + LB;
1628 address += Index_Registers[REGISTER_X];
1629 if (address >= 0 && address < MEMORY_SIZE) {
1630 Registers[REGISTER_X] = Memory[address];
1631 }
1632 break;
1633
1634 case 0x0F: //LDY Immidiate
1635 data = fetch();
1636 Registers[REGISTER_Y] = data;
1637
1638 case 0x1F: //LDY absolute
1639 HB = fetch();
1640 LB = fetch();
1641 address += (WORD)((WORD)HB << 8) + LB;
1642 if (address >= 0 && address < MEMORY_SIZE) {
1643 Registers[REGISTER_Y] = Memory[address];
1644 }
1645
1646 break;
1647
1648 case 0x2F: //LDY index x absolute
1649 address += Index_Registers[REGISTER_X];
1650 HB = fetch();
1651 LB = fetch();
1652 address += (WORD)((WORD)HB << 8) + LB;
1653 if (address >= 0 && address < MEMORY_SIZE) {
1654 Registers[REGISTER_Y] = Memory[address];
1655 }
1656 break;
1657
1658 case 0x3F: //LDY index y absolute
1659 address += Index_Registers[REGISTER_Y];
1660 HB = fetch();
1661 LB = fetch();
1662 address += (WORD)((WORD)HB << 8) + LB;
1663 if (address >= 0 && address < MEMORY_SIZE) {
1664 Registers[REGISTER_Y] = Memory[address];
1665 }
1666 break;
1667
1668 case 0x4F: //LDY indirect addressing
1669 HB = fetch();
1670 LB = fetch();
1671 address = (WORD)((WORD)HB << 8) + LB;
1672 HB = Memory[address];
1673 LB = Memory[address];
1674 address = (WORD)((WORD)HB << 8) + LB;
1675 if (address >= 0 && address < MEMORY_SIZE) {
1676 Registers[REGISTER_Y] = Memory[address];
1677 }
1678 break;
1679
1680
1681 case 0x5F: //LDY indexed indrect adressing
1682 HB = fetch();
1683 LB = fetch();
1684 address = (WORD)((WORD)HB << 8) + LB;
1685 HB = Memory[address];
1686 LB = Memory[address + 1];
1687 address = (WORD)((WORD)HB << 8) + LB;
1688 address += Index_Registers[REGISTER_X];
1689 if (address >= 0 && address < MEMORY_SIZE) {
1690 Registers[REGISTER_Y] = Memory[address];
1691 }
1692 break;
1693
1694
1695
1696 address = (WORD)((WORD)HB << 8) + LB;
1697 address += Index_Registers[REGISTER_X];
1698 if (address >= 0 && address < MEMORY_SIZE) {
1699 Registers[REGISTER_B] = Memory[address];
1700 }
1701 break;
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714 case 0x0c: //LX LH Immidiate
1715 data = fetch();
1716 Registers[REGISTER_H] = data;
1717 data = fetch();
1718 Registers[REGISTER_L] = data;
1719 break;
1720
1721 case 0x0d: //LX LH Immidiate
1722 data = fetch();
1723 Registers[REGISTER_H] = data;
1724 data = fetch();
1725 Registers[REGISTER_L] = data;
1726 break;
1727
1728 case 0xf0: //CAY impl
1729 Registers[REGISTER_Y] = Registers[REGISTER_A];
1730 set_flag_n((BYTE)temp_word);
1731 break;
1732
1733 case 0xf1: //MYA impl
1734 Registers[REGISTER_A] = Registers[REGISTER_Y];
1735 break;
1736
1737
1738
1739
1740
1741 case 0x93: // SBIA
1742 data = fetch();
1743 temp_word = (WORD)data - (WORD)Registers[REGISTER_A];
1744 if ((Flags & FLAG_C) != 0) {
1745 temp_word--;
1746 }
1747 set_flag_n(Registers[REGISTER_B]);
1748 set_flag_z(Registers[REGISTER_B]);
1749 Registers[REGISTER_A] = (BYTE)temp_word;
1750
1751 break;
1752
1753 case 0x95: // CPIA
1754 data = fetch();
1755 temp_word = (WORD)data - (WORD)Registers[REGISTER_A];
1756 set_flag_n(Registers[REGISTER_B]);
1757 set_flag_z(Registers[REGISTER_B]);
1758 break;
1759
1760 case 0x96: // CPIB
1761 data = fetch();
1762 temp_word = (WORD)data - (WORD)Registers[REGISTER_B];
1763 set_flag_n(Registers[REGISTER_B]);
1764 set_flag_z(Registers[REGISTER_B]);
1765 break;
1766
1767
1768 case 0x94: // SBIB
1769 data = fetch();
1770 temp_word = (WORD)data - (WORD)Registers[REGISTER_B];
1771 if ((Flags & FLAG_C) != 0) {
1772 temp_word--;
1773 }
1774 set_flag_n(Registers[REGISTER_B]);
1775 set_flag_z(Registers[REGISTER_B]);
1776 Registers[REGISTER_B] = (BYTE)temp_word;
1777
1778 break;
1779
1780 case 0xBE:// push
1781 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1782 Memory[StackPointer] = Registers[REGISTER_A];
1783 StackPointer--;
1784 }
1785
1786 break;
1787
1788 case 0xCE: //PUSH B
1789 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1790 Memory[StackPointer] = Registers[REGISTER_B];
1791 StackPointer--;
1792 }
1793 break;
1794
1795 case 0xDE: //PUSH FL
1796 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1797 Memory[StackPointer] = Flags;
1798 StackPointer--;
1799 }
1800 break;
1801
1802 case 0xEE: //PUSH L
1803 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1804 Memory[StackPointer] = Registers[REGISTER_L];
1805 StackPointer--;
1806 }
1807 break;
1808
1809 case 0xFE: //PUSH H
1810 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1811 Memory[StackPointer] = Registers[REGISTER_H];
1812 StackPointer--;
1813 }
1814 break;
1815
1816 case 0x10:// jmp
1817 HB = fetch();
1818 LB = fetch();
1819 address = ((WORD)HB << 8) + (WORD)LB;
1820 ProgramCounter = address;
1821 break;
1822
1823
1824 case 0x21:// JSR
1825 HB = fetch();
1826 LB = fetch();
1827 address = ((WORD)HB << 8) + (WORD)LB;
1828 if ((StackPointer >= 2) && (StackPointer < MEMORY_SIZE))
1829 Memory[StackPointer] = (BYTE)(ProgramCounter & 0xFF);
1830 StackPointer--;
1831 Memory[StackPointer] = (BYTE)((ProgramCounter >> 8) & 0xFF);
1832 StackPointer--;
1833 {
1834 ProgramCounter = address;
1835
1836 }
1837 break;
1838
1839 case 0x4C:// RET
1840 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 2))
1841 StackPointer++;
1842 HB = Memory[StackPointer];
1843 StackPointer++;
1844 LB = Memory[StackPointer];
1845 ProgramCounter = ((WORD)HB << 8) + (WORD)LB;
1846 break;
1847
1848 case 0xd0:// INCA
1849 ++Registers[REGISTER_A];
1850 set_flag_n(Registers[REGISTER_A]);
1851 set_flag_z(Registers[REGISTER_A]);
1852 break;
1853
1854 case 0xe0:// INCB
1855 ++Registers[REGISTER_B];
1856 set_flag_n(Registers[REGISTER_B]);
1857 set_flag_z(Registers[REGISTER_B]);
1858 break;
1859
1860 case 0x02:// INCX
1861 ++Index_Registers[REGISTER_X];
1862 set_flag_z(Registers[REGISTER_X]);
1863 break;
1864
1865 case 0x04:// INCY
1866 ++Index_Registers[REGISTER_Y];
1867 set_flag_z(Registers[REGISTER_Y]);
1868 break;
1869
1870
1871 case 0x39:// BIT
1872 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_L];
1873 set_flag_n((BYTE)temp_word);
1874 set_flag_z((BYTE)temp_word);
1875 break;
1876
1877 case 0x49:// BIT
1878 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_H];
1879 set_flag_n((BYTE)temp_word);
1880 set_flag_z((BYTE)temp_word);
1881 break;
1882
1883 case 0x59:// BIT
1884 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_M];
1885 set_flag_n((BYTE)temp_word);
1886 set_flag_z((BYTE)temp_word);
1887 break;
1888
1889 case 0x69:// BIT
1890 temp_word = (WORD)Registers[REGISTER_B] & (WORD)Registers[REGISTER_L];
1891 set_flag_n((BYTE)temp_word);
1892 set_flag_z((BYTE)temp_word);
1893 break;
1894
1895 case 0x79:// BIT
1896 temp_word = (WORD)Registers[REGISTER_B] & (WORD)Registers[REGISTER_H];
1897 set_flag_n((BYTE)temp_word);
1898 set_flag_z((BYTE)temp_word);
1899 break;
1900
1901 case 0x89:// BIT
1902 temp_word = (WORD)Registers[REGISTER_B] & (WORD)Registers[REGISTER_M];
1903 set_flag_n((BYTE)temp_word);
1904 set_flag_z((BYTE)temp_word);
1905 break;
1906
1907 case 0xBF: // POP A
1908 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1909 StackPointer++;
1910 Registers[REGISTER_A] = Memory[StackPointer];
1911 }
1912 break;
1913 case 0xCF: // POP B
1914 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1915 StackPointer++;
1916 Registers[REGISTER_B] = Memory[StackPointer];
1917 }
1918 break;
1919 case 0xDF: // POP FL
1920 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1921 StackPointer++;
1922 Flags = Memory[StackPointer];
1923 }
1924 break;
1925 case 0xEF: // POP L
1926 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1927 StackPointer++;
1928 Registers[REGISTER_L] = Memory[StackPointer];
1929 }
1930 break;
1931 case 0xFF: // POP H
1932 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1933 StackPointer++;
1934 Registers[REGISTER_H] = Memory[StackPointer];
1935 }
1936
1937 case 0xf3: // ABA
1938 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_B];
1939 set_flag_n((BYTE)temp_word);
1940 set_flag_z((BYTE)temp_word);
1941 Registers[REGISTER_A] = (BYTE)temp_word;
1942 break;
1943
1944 case 0xf5: // AAB
1945 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_B];
1946 set_flag_n((BYTE)temp_word);
1947 set_flag_z((BYTE)temp_word);
1948 Registers[REGISTER_B] = (BYTE)temp_word;
1949 break;
1950
1951 case 0xf4: // SBA
1952 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_B];
1953 set_flag_n((BYTE)temp_word);
1954 set_flag_z((BYTE)temp_word);
1955 Registers[REGISTER_A] = (BYTE)temp_word;
1956 break;
1957
1958 case 0xf6: // SAB
1959 temp_word = (WORD)Registers[REGISTER_B] - (WORD)Registers[REGISTER_A];
1960 set_flag_n((BYTE)temp_word);
1961 set_flag_z((BYTE)temp_word);
1962 Registers[REGISTER_B] = (BYTE)temp_word;
1963 break;
1964
1965 case 0xf7: // ADCP
1966 temp_word = (WORD)Registers[REGISTER_L] + (WORD)Registers[REGISTER_A];
1967 set_flag_n((BYTE)temp_word);
1968 set_flag_z((BYTE)temp_word);
1969 Registers[REGISTER_A] = (BYTE)temp_word;
1970 break;
1971
1972 case 0xf8: // SBCP
1973 temp_word = (WORD)Registers[REGISTER_L] - (WORD)Registers[REGISTER_A];
1974 set_flag_n((BYTE)temp_word);
1975 set_flag_z((BYTE)temp_word);
1976 Registers[REGISTER_A] = (BYTE)temp_word;
1977 break;
1978
1979 case 0x11: // JCC
1980 HB = fetch();
1981 LB = fetch();
1982 address = (WORD)((WORD)HB << 8) + LB;
1983 if ((Flags & FLAG_C) == 0) {
1984 ProgramCounter = address;
1985 }
1986 break;
1987 case 0x12: // JCS
1988 HB = fetch();
1989 LB = fetch();
1990 address = (WORD)((WORD)HB << 8) + LB;
1991 if ((Flags & FLAG_C) != 0) {
1992 ProgramCounter = address;
1993 }
1994 break;
1995 case 0x13: // JNE
1996 HB = fetch();
1997 LB = fetch();
1998 address = (WORD)((WORD)HB << 8) + LB;
1999 if ((Flags & FLAG_Z) == 0) {
2000 ProgramCounter = address;
2001 }
2002 break;
2003
2004 case 0x14: //JEQ
2005 HB = fetch();
2006 LB = fetch();
2007 address = ((WORD)HB << 8) + (WORD)LB;
2008 if ((Flags & FLAG_Z) == 1)
2009 {
2010 ProgramCounter = address;
2011 }
2012 break;
2013
2014 case 0x15: // JMI
2015 HB = fetch();
2016 LB = fetch();
2017 address = ((WORD)HB << 8) + (WORD)LB;
2018 if ((Flags & FLAG_N) == 1)
2019 {
2020 ProgramCounter = address;
2021 }
2022 break;
2023
2024
2025 case 0x16: // JPL
2026 HB = fetch();
2027 LB = fetch();
2028 address = ((WORD)HB << 8) + (WORD)LB;
2029 if ((Flags & FLAG_N) == 0)
2030 {
2031 ProgramCounter = address;
2032 }
2033 break;
2034
2035 case 0x17: // JHI
2036 HB = fetch();
2037 LB = fetch();
2038 address = ((WORD)HB << 8) + (WORD)LB;
2039 if (((Flags & FLAG_C) == 1) || (Flags & FLAG_Z) == 1)
2040 {
2041 ProgramCounter = address;
2042 }
2043 break;
2044
2045 case 0x18: // JLE
2046 HB = fetch();
2047 LB = fetch();
2048 address = ((WORD)HB << 8) + (WORD)LB;
2049 if (((Flags & FLAG_C) == 0) || (Flags & FLAG_Z) == 0)
2050 {
2051 ProgramCounter = address;
2052 }
2053 break;
2054
2055 case 0x22: //CCC
2056 HB = fetch();
2057 LB = fetch();
2058 address = ((WORD)HB << 8) + (WORD)LB;
2059 if ((Flags & FLAG_C) == 0)
2060 {
2061 if ((StackPointer >= -2) && (StackPointer < MEMORY_SIZE)) {
2062 Memory[StackPointer] = (BYTE)((ProgramCounter & 0xFF));
2063 StackPointer--;
2064 Memory[StackPointer] = (BYTE)((ProgramCounter >> 8) & 0xFF);
2065 StackPointer--;
2066 }
2067 ProgramCounter = address;
2068 }
2069 break;
2070
2071 case 0x23: //CCS
2072 HB = fetch();
2073 LB = fetch();
2074 address = ((WORD)HB << 8) + (WORD)LB;
2075 if ((Flags & FLAG_C) != 0)
2076 {
2077 if ((StackPointer >= -2) && (StackPointer < MEMORY_SIZE)) {
2078 Memory[StackPointer] = (BYTE)((ProgramCounter & 0xFF));
2079 StackPointer--;
2080 Memory[StackPointer] = (BYTE)((ProgramCounter >> 8) & 0xFF);
2081 StackPointer--;
2082 }
2083 ProgramCounter = address;
2084 }
2085 break;
2086
2087 case 0x24: //CNE
2088 HB = fetch();
2089 LB = fetch();
2090 address = ((WORD)HB << 8) + (WORD)LB;
2091 if ((Flags & FLAG_Z) == 0)
2092 {
2093 if ((StackPointer >= -2) && (StackPointer < MEMORY_SIZE)) {
2094 Memory[StackPointer] = (BYTE)((ProgramCounter & 0xFF));
2095 StackPointer--;
2096 Memory[StackPointer] = (BYTE)((ProgramCounter >> 8) & 0xFF);
2097 StackPointer--;
2098 }
2099 ProgramCounter = address;
2100 }
2101 break;
2102
2103 case 0x05: //CLC
2104 Flags = Flags & (0xff - FLAG_C);
2105 break;
2106 case 0x06: //STC
2107 Flags = Flags | FLAG_C;
2108 break;
2109 case 0x07: //CLI
2110 Flags = Flags & (0xff - FLAG_I);
2111 break;
2112 case 0x08: //STI
2113 Flags = Flags | FLAG_I;
2114 break;
2115
2116 ///////////////////////// additions 21 nov 16 ////////
2117 /*
2118 case 0xD7: //COMB
2119 temp_word = ~(Registers[REGISTER_A]);
2120 set_flag_z((BYTE)temp_word);
2121 set_flag_n((BYTE)temp_word);
2122 Registers[REGISTER_A] = temp_word;
2123 break;
2124
2125 case 0xE7: //COMB
2126 temp_word = ~(Registers[REGISTER_B]);
2127 set_flag_z((BYTE)temp_word);
2128 set_flag_n((BYTE)temp_word);
2129 Registers[REGISTER_B] = temp_word;
2130 break;
2131
2132
2133
2134 case 0xA1: //DEC abs
2135 --Registers[REGISTER_X];
2136 set_flag_n(Registers[REGISTER_X]);
2137 set_flag_z(Registers[REGISTER_X]);
2138 break;
2139
2140 case 0xB1: //DEC abs,X
2141 --Index_Registers[REGISTER_X];
2142 set_flag_n(Index_Registers[REGISTER_X]);
2143 set_flag_z(Index_Registers[REGISTER_X]);
2144 break;
2145
2146 case 0xC1: //DEC abs,Y
2147 --Index_Registers[REGISTER_Y];
2148 set_flag_n(Index_Registers[REGISTER_Y]);
2149 set_flag_z(Index_Registers[REGISTER_Y]);
2150 break;
2151
2152 case 0xD1: //DECA
2153 --Registers[REGISTER_A];
2154 set_flag_n(Registers[REGISTER_A]);
2155 set_flag_z(Registers[REGISTER_A]);
2156 break;
2157
2158 case 0xE1: //DECB
2159 --Registers[REGISTER_B];
2160 set_flag_n(Registers[REGISTER_B]);
2161 set_flag_z(Registers[REGISTER_B]);
2162 break;
2163
2164
2165 case 0x98: //ORIA (#)
2166 data = fetch();
2167 param1 = Registers[REGISTER_A];
2168 temp_word = (WORD)data | (WORD)param1;
2169 set_flag_z((WORD)temp_word);
2170 set_flag_n((WORD)temp_word);
2171 Registers[REGISTER_A] = temp_word;
2172 break;
2173
2174 case 0x97: //ORIB (#)
2175 data = fetch();
2176 param1 = Registers[REGISTER_B];
2177 temp_word = (WORD)data | (WORD)param1;
2178 set_flag_z((WORD)temp_word);
2179 set_flag_n((WORD)temp_word);
2180 Registers[REGISTER_B] = temp_word;
2181 break;
2182 */
2183
2184
2185
2186 default: // unimplemented instruction
2187 opcode = opcode;
2188 halt = true;
2189 break;
2190
2191
2192
2193 }
2194}
2195
2196void Group_2_Move(BYTE opcode)
2197{
2198 /*
2199 MOVE is like a grid/block
2200 We can untilise this to make our lives simpler
2201 */
2202
2203 //store low nibble and high nibble
2204 //low nibble = source = original location to swap
2205 //high nibble = dest = new location of where swapped
2206 BYTE dest = opcode & 0x0F; //get the last 4 bits --> xxxxyyyy becomes 0000yyyy
2207 BYTE source = opcode & 0xF0; //get the front 4 bits ---> xxxxyyyy becomes 0000xxxx
2208
2209 //temp vars for registers
2210 int destReg = 0, sourceReg = 0;
2211
2212 //address for memory
2213 WORD address;
2214
2215 switch (dest) {
2216 case 0x0B:
2217 destReg = REGISTER_A;
2218 break;
2219 case 0x0C:
2220 destReg = REGISTER_B;
2221 break;
2222 case 0x0D:
2223 destReg = REGISTER_L;
2224 break;
2225 case 0x0E:
2226 destReg = REGISTER_H;
2227 break;
2228 case 0x0F:
2229 destReg = REGISTER_M;
2230 break;
2231 default:
2232 break;
2233 }
2234
2235 switch (source)
2236 {
2237 case 0x60:
2238 sourceReg = REGISTER_A;
2239 break;
2240 case 0x70:
2241 sourceReg = REGISTER_B;
2242 break;
2243 case 0x80:
2244 sourceReg = REGISTER_L;
2245 break;
2246 case 0x90:
2247 sourceReg = REGISTER_H;
2248 break;
2249 case 0xA0:
2250 sourceReg = REGISTER_M;
2251 break;
2252 default:
2253 break;
2254 }
2255
2256
2257 if (destReg == REGISTER_M) {
2258 address = Registers[REGISTER_L];
2259 address += (WORD)Registers[REGISTER_H] << 4;
2260 if (address >= 0 && address <= MEMORY_SIZE) {
2261 Memory[address] = Registers[sourceReg];
2262 }
2263 }
2264 else {
2265 //do the swap
2266 Registers[destReg] = Registers[sourceReg];
2267 }
2268
2269 if (sourceReg == REGISTER_M) {
2270 address = Registers[REGISTER_L];
2271 address += (WORD)Registers[REGISTER_H] << 4;
2272 if (address >= 0 && address <= MEMORY_SIZE) {
2273 Memory[address] = Registers[sourceReg];
2274 }
2275 }
2276 else {
2277 //do the swap
2278 Registers[destReg] = Registers[sourceReg];
2279 }
2280
2281
2282}
2283
2284
2285void execute(BYTE opcode)
2286{
2287
2288 if (((opcode >= 0x6B) && (opcode <= 0x6F))
2289 || ((opcode >= 0x7B) && (opcode <= 0x7F))
2290 || ((opcode >= 0x8B) && (opcode <= 0x8F))
2291 || ((opcode >= 0x9B) && (opcode <= 0x9F))
2292 || ((opcode >= 0xAB) && (opcode <= 0xAF)))
2293 {
2294 Group_2_Move(opcode);
2295 }
2296 else
2297 {
2298 Group_1(opcode);
2299 }
2300}
2301
2302void emulate()
2303{
2304 BYTE opcode;
2305 int sanity;
2306
2307 ProgramCounter = 0;
2308 halt = false;
2309 memory_in_range = true;
2310 sanity = 0;
2311
2312 printf(" A B L H X Y SP\n");
2313
2314 while ((!halt) && (memory_in_range) && (sanity < 200))
2315 {
2316 printf("%04X ", ProgramCounter); // Print current address
2317 opcode = fetch();
2318 execute(opcode);
2319
2320 printf("%s ", opcode_mneumonics[opcode]); // Print current opcode
2321
2322 printf("%02X ", Registers[REGISTER_A]);
2323 printf("%02X ", Registers[REGISTER_B]);
2324 printf("%02X ", Registers[REGISTER_L]);
2325 printf("%02X ", Registers[REGISTER_H]);
2326 printf("%02X ", Index_Registers[REGISTER_X]);
2327 printf("%02X ", Index_Registers[REGISTER_Y]);
2328 printf("%04X ", StackPointer); // Print Stack Pointer
2329
2330 if ((Flags & FLAG_I) == FLAG_I)
2331 {
2332 printf("I=1 ");
2333 }
2334 else
2335 {
2336 printf("I=0 ");
2337 }
2338 if ((Flags & FLAG_Z) == FLAG_Z)
2339 {
2340 printf("Z=1 ");
2341 }
2342 else
2343 {
2344 printf("Z=0 ");
2345 }
2346 if ((Flags & FLAG_N) == FLAG_N)
2347 {
2348 printf("N=1 ");
2349 }
2350 else
2351 {
2352 printf("N=0 ");
2353 }
2354 if ((Flags & FLAG_C) == FLAG_C)
2355 {
2356 printf("C=1 ");
2357 }
2358 else
2359 {
2360 printf("C=0 ");
2361 }
2362
2363 printf("\n"); // New line
2364 sanity++;
2365 }
2366
2367 printf("\n"); // New line
2368}
2369
2370
2371////////////////////////////////////////////////////////////////////////////////
2372// Simulator/Emulator (End) //
2373////////////////////////////////////////////////////////////////////////////////
2374
2375
2376void initialise_filenames() {
2377 int i;
2378
2379 for (i = 0; i<MAX_FILENAME_SIZE; i++) {
2380 hex_file[i] = '\0';
2381 trc_file[i] = '\0';
2382 }
2383}
2384
2385
2386
2387
2388int find_dot_position(char *filename) {
2389 int dot_position;
2390 int i;
2391 char chr;
2392
2393 dot_position = 0;
2394 i = 0;
2395 chr = filename[i];
2396
2397 while (chr != '\0') {
2398 if (chr == '.') {
2399 dot_position = i;
2400 }
2401 i++;
2402 chr = filename[i];
2403 }
2404
2405 return (dot_position);
2406}
2407
2408
2409int find_end_position(char *filename) {
2410 int end_position;
2411 int i;
2412 char chr;
2413
2414 end_position = 0;
2415 i = 0;
2416 chr = filename[i];
2417
2418 while (chr != '\0') {
2419 end_position = i;
2420 i++;
2421 chr = filename[i];
2422 }
2423
2424 return (end_position);
2425}
2426
2427
2428bool file_exists(char *filename) {
2429 bool exists;
2430 FILE *ifp;
2431
2432 exists = false;
2433
2434 if ((ifp = fopen(filename, "r")) != NULL)
2435 {
2436 exists = true;
2437
2438 fclose(ifp);
2439 }
2440
2441 return (exists);
2442}
2443
2444
2445
2446void create_file(char *filename) {
2447 FILE *ofp;
2448
2449 if ((ofp = fopen(filename, "w")) != NULL) {
2450 fclose(ofp);
2451 }
2452}
2453
2454
2455
2456bool getline(FILE *fp, char *buffer) {
2457 bool rc;
2458 bool collect;
2459 char c;
2460 int i;
2461
2462 rc = false;
2463 collect = true;
2464
2465 i = 0;
2466 while (collect) {
2467 c = getc(fp);
2468
2469 switch (c) {
2470 case EOF:
2471 if (i > 0) {
2472 rc = true;
2473 }
2474 collect = false;
2475 break;
2476
2477 case '\n':
2478 if (i > 0) {
2479 rc = true;
2480 collect = false;
2481 buffer[i] = '\0';
2482 }
2483 break;
2484
2485 default:
2486 buffer[i] = c;
2487 i++;
2488 break;
2489 }
2490 }
2491
2492 return (rc);
2493}
2494
2495
2496
2497
2498
2499
2500void load_and_run(int args, _TCHAR** argv) {
2501 char chr;
2502 int ln;
2503 int dot_position;
2504 int end_position;
2505 long i;
2506 FILE *ifp;
2507 long address;
2508 long load_at;
2509 int code;
2510
2511 // Prompt for the .hex file
2512
2513 printf("\n");
2514 printf("Enter the hex filename (.hex): ");
2515
2516 if (args == 2) {
2517 ln = 0;
2518 chr = argv[1][ln];
2519 while (chr != '\0')
2520 {
2521 if (ln < MAX_FILENAME_SIZE)
2522 {
2523 hex_file[ln] = chr;
2524 trc_file[ln] = chr;
2525 ln++;
2526 }
2527 chr = argv[1][ln];
2528 }
2529 }
2530 else {
2531 ln = 0;
2532 chr = '\0';
2533 while (chr != '\n') {
2534 chr = getchar();
2535
2536 switch (chr) {
2537 case '\n':
2538 break;
2539 default:
2540 if (ln < MAX_FILENAME_SIZE) {
2541 hex_file[ln] = chr;
2542 trc_file[ln] = chr;
2543 ln++;
2544 }
2545 break;
2546 }
2547 }
2548
2549 }
2550 // Tidy up the file names
2551
2552 dot_position = find_dot_position(hex_file);
2553 if (dot_position == 0) {
2554 end_position = find_end_position(hex_file);
2555
2556 hex_file[end_position + 1] = '.';
2557 hex_file[end_position + 2] = 'h';
2558 hex_file[end_position + 3] = 'e';
2559 hex_file[end_position + 4] = 'x';
2560 hex_file[end_position + 5] = '\0';
2561 }
2562 else {
2563 hex_file[dot_position + 0] = '.';
2564 hex_file[dot_position + 1] = 'h';
2565 hex_file[dot_position + 2] = 'e';
2566 hex_file[dot_position + 3] = 'x';
2567 hex_file[dot_position + 4] = '\0';
2568 }
2569
2570 dot_position = find_dot_position(trc_file);
2571 if (dot_position == 0) {
2572 end_position = find_end_position(trc_file);
2573
2574 trc_file[end_position + 1] = '.';
2575 trc_file[end_position + 2] = 't';
2576 trc_file[end_position + 3] = 'r';
2577 trc_file[end_position + 4] = 'c';
2578 trc_file[end_position + 5] = '\0';
2579 }
2580 else {
2581 trc_file[dot_position + 0] = '.';
2582 trc_file[dot_position + 1] = 't';
2583 trc_file[dot_position + 2] = 'r';
2584 trc_file[dot_position + 3] = 'c';
2585 trc_file[dot_position + 4] = '\0';
2586 }
2587
2588 if (file_exists(hex_file)) {
2589 // Clear Registers and Memory
2590
2591 Registers[REGISTER_A] = 0;
2592 Registers[REGISTER_B] = 0;
2593 Registers[REGISTER_L] = 0;
2594 Registers[REGISTER_H] = 0;
2595 Index_Registers[REGISTER_X] = 0;
2596 Index_Registers[REGISTER_Y] = 0;
2597 Flags = 0;
2598 ProgramCounter = 0;
2599 StackPointer = 0;
2600
2601 for (i = 0; i<MEMORY_SIZE; i++) {
2602 Memory[i] = 0x00;
2603 }
2604
2605 // Load hex file
2606
2607 if ((ifp = fopen(hex_file, "r")) != NULL) {
2608 printf("Loading file...\n\n");
2609
2610 load_at = 0;
2611
2612 while (getline(ifp, InputBuffer)) {
2613 if (sscanf(InputBuffer, "L=%x", &address) == 1) {
2614 load_at = address;
2615 }
2616 else if (sscanf(InputBuffer, "%x", &code) == 1) {
2617 if ((load_at >= 0) && (load_at <= MEMORY_SIZE)) {
2618 Memory[load_at] = (BYTE)code;
2619 }
2620 load_at++;
2621 }
2622 else {
2623 printf("ERROR> Failed to load instruction: %s \n", InputBuffer);
2624 }
2625 }
2626
2627 fclose(ifp);
2628 }
2629
2630 // Emulate
2631
2632 emulate();
2633 }
2634 else {
2635 printf("\n");
2636 printf("ERROR> Input file %s does not exist!\n", hex_file);
2637 printf("\n");
2638 }
2639}
2640
2641void building(int args, _TCHAR** argv)
2642{
2643 char buffer[1024];
2644 load_and_run(args, argv);
2645 sprintf(buffer, "0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X",
2646 Memory[TEST_ADDRESS_1],
2647 Memory[TEST_ADDRESS_2],
2648 Memory[TEST_ADDRESS_3],
2649 Memory[TEST_ADDRESS_4],
2650 Memory[TEST_ADDRESS_5],
2651 Memory[TEST_ADDRESS_6],
2652 Memory[TEST_ADDRESS_7],
2653 Memory[TEST_ADDRESS_8],
2654 Memory[TEST_ADDRESS_9],
2655 Memory[TEST_ADDRESS_10],
2656 Memory[TEST_ADDRESS_11],
2657 Memory[TEST_ADDRESS_12]
2658 );
2659 sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
2660}
2661
2662
2663
2664void test_and_mark() {
2665 char buffer[1024];
2666 bool testing_complete;
2667 int len = sizeof(SOCKADDR);
2668 char chr;
2669 int i;
2670 int j;
2671 bool end_of_program;
2672 long address;
2673 long load_at;
2674 int code;
2675 int mark;
2676 int passed;
2677
2678 printf("\n");
2679 printf("Automatic Testing and Marking\n");
2680 printf("\n");
2681
2682 testing_complete = false;
2683
2684 sprintf(buffer, "Test Student %s", STUDENT_NUMBER);
2685 sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
2686
2687 while (!testing_complete) {
2688 memset(buffer, '\0', sizeof(buffer));
2689
2690 if (recvfrom(sock, buffer, sizeof(buffer) - 1, 0, (SOCKADDR *)&client_addr, &len) != SOCKET_ERROR) {
2691 printf("Incoming Data: %s \n", buffer);
2692
2693 //if (strcmp(buffer, "Testing complete") == 1)
2694 if (sscanf(buffer, "Testing complete %d", &mark) == 1) {
2695 testing_complete = true;
2696 printf("Current mark = %d\n", mark);
2697
2698 }
2699 else if (sscanf(buffer, "Tests passed %d", &passed) == 1) {
2700 //testing_complete = true;
2701 printf("Passed = %d\n", passed);
2702
2703 }
2704 else if (strcmp(buffer, "Error") == 0) {
2705 printf("ERROR> Testing abnormally terminated\n");
2706 testing_complete = true;
2707 }
2708 else {
2709 // Clear Registers and Memory
2710
2711 Registers[REGISTER_A] = 0;
2712 Registers[REGISTER_B] = 0;
2713 Registers[REGISTER_L] = 0;
2714 Registers[REGISTER_H] = 0;
2715 Index_Registers[REGISTER_X] = 0;
2716 Index_Registers[REGISTER_Y] = 0;
2717 Flags = 0;
2718 ProgramCounter = 0;
2719 StackPointer = 0;
2720 for (i = 0; i<MEMORY_SIZE; i++) {
2721 Memory[i] = 0;
2722 }
2723
2724 // Load hex file
2725
2726 i = 0;
2727 j = 0;
2728 load_at = 0;
2729 end_of_program = false;
2730 FILE *ofp;
2731 fopen_s(&ofp, "branch.txt", "a");
2732
2733 while (!end_of_program) {
2734 chr = buffer[i];
2735 switch (chr) {
2736 case '\0':
2737 end_of_program = true;
2738
2739 case ',':
2740 if (sscanf(InputBuffer, "L=%x", &address) == 1) {
2741 load_at = address;
2742 }
2743 else if (sscanf(InputBuffer, "%x", &code) == 1) {
2744 if ((load_at >= 0) && (load_at <= MEMORY_SIZE)) {
2745 Memory[load_at] = (BYTE)code;
2746 fprintf(ofp, "%02X\n", (BYTE)code);
2747 }
2748 load_at++;
2749 }
2750 else {
2751 printf("ERROR> Failed to load instruction: %s \n", InputBuffer);
2752 }
2753 j = 0;
2754 break;
2755
2756 default:
2757 InputBuffer[j] = chr;
2758 j++;
2759 break;
2760 }
2761 i++;
2762 }
2763 fclose(ofp);
2764 // Emulate
2765
2766 if (load_at > 1) {
2767 emulate();
2768 // Send and store results
2769 sprintf(buffer, "%02X%02X %02X%02X %02X%02X %02X%02X %02X%02X %02X%02X",
2770 Memory[TEST_ADDRESS_1],
2771 Memory[TEST_ADDRESS_2],
2772 Memory[TEST_ADDRESS_3],
2773 Memory[TEST_ADDRESS_4],
2774 Memory[TEST_ADDRESS_5],
2775 Memory[TEST_ADDRESS_6],
2776 Memory[TEST_ADDRESS_7],
2777 Memory[TEST_ADDRESS_8],
2778 Memory[TEST_ADDRESS_9],
2779 Memory[TEST_ADDRESS_10],
2780 Memory[TEST_ADDRESS_11],
2781 Memory[TEST_ADDRESS_12]
2782 );
2783 sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
2784 }
2785 }
2786 }
2787 }
2788}
2789
2790
2791
2792int _tmain(int argc, _TCHAR* argv[])
2793{
2794 char chr;
2795 char dummy;
2796
2797 printf("\n");
2798 printf("Microprocessor Emulator\n");
2799 printf("UWE Computer and Network Systems Assignment 1\n");
2800 printf("\n");
2801
2802 initialise_filenames();
2803
2804 if (WSAStartup(MAKEWORD(2, 2), &data) != 0) return(0);
2805
2806 sock = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); // Here we create our socket, which will be a UDP socket (SOCK_DGRAM).
2807 if (!sock) {
2808 // Creation failed!
2809 }
2810
2811 memset(&server_addr, 0, sizeof(SOCKADDR_IN));
2812 server_addr.sin_family = AF_INET;
2813 server_addr.sin_addr.s_addr = inet_addr(IP_ADDRESS_SERVER);
2814 server_addr.sin_port = htons(PORT_SERVER);
2815
2816 memset(&client_addr, 0, sizeof(SOCKADDR_IN));
2817 client_addr.sin_family = AF_INET;
2818 client_addr.sin_addr.s_addr = inet_addr("127.0.0.1");
2819 client_addr.sin_port = htons(PORT_CLIENT);
2820
2821 chr = '\0';
2822 while ((chr != 'e') && (chr != 'E'))
2823 {
2824 printf("\n");
2825 printf("Please select option\n");
2826 printf("L - Load and run a hex file\n");
2827 printf("T - Have the server test and mark your emulator\n");
2828 printf("E - Exit\n");
2829 if (argc == 2) { building(argc, argv); exit(0); }
2830 printf("Enter option: ");
2831 chr = getchar();
2832 if (chr != 0x0A)
2833 {
2834 dummy = getchar(); // read in the <CR>
2835 }
2836 printf("\n");
2837
2838 switch (chr)
2839 {
2840 case 'L':
2841 case 'l':
2842 load_and_run(argc, argv);
2843 break;
2844
2845 case 'T':
2846 case 't':
2847 test_and_mark();
2848 break;
2849
2850 default:
2851 break;
2852 }
2853 }
2854
2855 closesocket(sock);
2856 WSACleanup();
2857
2858
2859 return 0;
2860}