mmVfXQ1j

1[0000.250] [L4T TegraBoot] (version 00.00.2018.01-l4t-39a9dc3d)
2[0000.256] Processing in cold boot mode Bootloader 2
3[0000.261] A02 Bootrom Patch rev = 1023
4[0000.264] Power-up reason: pmc por
5[0000.267] No Battery Present
6[0000.270] pmic max77620 reset reason
7[0000.273] pmic max77620 NVERC : 0x47
8[0000.277] RamCode = 0
9[0000.279] Platform has DDR4 type RAM
10[0000.282] max77620 disabling SD1 Remote Sense
11[0000.287] Setting DDR voltage to 1125mv
12[0000.290] Serial Number of Pmic Max77663: 0xe24f1
13[0000.298] Entering ramdump check
14[0000.301] Get RamDumpCarveOut = 0x0
15[0000.304] RamDumpCarveOut=0x0,  RamDumperFlag=0xe59ff3f8
16[0000.309] Last reboot was clean, booting normally!
17[0000.314] Sdram initialization is successful
18[0000.318] SecureOs Carveout Base=0x00000000ff800000 Size=0x00800000
19[0000.324] Lp0 Carveout Base=0x00000000ff780000 Size=0x00001000
20[0000.330] BpmpFw Carveout Base=0x00000000ff700000 Size=0x00080000
21[0000.336] GSC1 Carveout Base=0x00000000ff600000 Size=0x00100000
22[0000.342] GSC2 Carveout Base=0x00000000ff500000 Size=0x00100000
23[0000.348] GSC4 Carveout Base=0x00000000ff400000 Size=0x00100000
24[0000.353] GSC5 Carveout Base=0x00000000ff300000 Size=0x00100000
25[0000.359] GSC3 Carveout Base=0x000000017f300000 Size=0x00d00000
26[0000.375] RamDump Carveout Base=0x00000000ff280000 Size=0x00080000
27[0000.382] Platform-DebugCarveout: 0
28[0000.385] Nck Carveout Base=0x00000000ff080000 Size=0x00200000
29[0000.391] Non secure mode, and RB not enabled.
30[0000.407] Csd NumOfBlocks=0
31[0000.599] *** Booting BFS1.
32[0000.605] Using BFS PT to query partitions
33[0001.191] *** Booting KFS1.
34[0001.195] Using GPT Primary to query partitions
35[0001.200] Loading Tboot-CPU binary
36[0001.207] Verifying TBC in OdmNonSecureSBK mode
37[0001.217] Bootloader load address is 0xa0000000, entry address is 0xa0000258
38[0001.224] Bootloader downloaded successfully.
39[0001.228] Downloaded Tboot-CPU binary to 0xa0000258
40[0001.233] MAX77620_GPIO5 configured
41[0001.237] CPU power rail is up
42[0001.239] CPU clock enabled
43[0001.243] Performing RAM repair
44[0001.246] Updating A64 Warmreset Address to 0xa00002e9
45[0001.252] Loading NvTbootBootloaderDTB
46[0001.269] Verifying NvTbootBootloaderDTB in OdmNonSecureSBK mode
47[0001.334] Bootloader DTB Load Address: 0x83000000
48[0001.339] Loading NvTbootKernelDTB
49[0001.355] Verifying NvTbootKernelDTB in OdmNonSecureSBK mode
50[0001.420] Kernel DTB Load Address: 0x83100000
51[0001.426] Loading cboot binary
52[0001.437] Verifying EBT in OdmNonSecureSBK mode
53[0001.479] Bootloader load address is 0x92c00000, entry address is 0x92c00258
54[0001.486] Bootloader downloaded successfully.
55[0001.490] Next binary entry address: 0x92c00258
56[0001.495] BoardId: 3448
57[0001.499] Overriding pmu board id with proc board id
58[0001.504] Display board id is not available
59[0001.516] Verifying SC7EntryFw in OdmNonSecureSBK mode
60[0001.568] /bpmp deleted
61[0001.570] SC7EntryFw header found loaded at 0xff700000
62[0001.759] OVR2 PMIC
63[0001.761] Bpmp FW successfully loaded
64[0001.766] WB0 init successfully at 0xff780000
65[0001.770] Set NvDecSticky Bits
66[0001.774] GSC2 address ff53fffc value c0edbbcc
67[0001.780] GSC MC Settings done
68[0001.783] TOS Image length 53680
69[0001.786]  Monitor size 53680
70[0001.789]  OS size 0
71[0001.794] Secure Os AES-CMAC Verification Success!
72[0001.799] TOS image cipher info: plaintext
73[0001.803] Loading and Validation of Secure OS Successful
74[0001.819] SC7 Entry Firmware - 0xff700000, 0x4000
75[0001.823] NvTbootPackSdramParams: start.
76[0001.828] NvTbootPackSdramParams: done.
77[0001.832] Tegraboot started after 180686 us
78[0001.836] Basic modules init took 1364797 us
79[0001.840] Sec Bootdevice Read Time = 545 ms, Read Size = 14457 KB
80[0001.846] Sec Bootdevice Write Time = 0 ms, Write Size = 0 KB
81[0001.852] Next stage binary read took 7384 us
82[0001.856] Carveout took -19405 us
83[0001.859] CPU initialization took 343015 us
84[0001.863] Total time taken by TegraBoot 1695791 us
85
86[0001.868] Starting CPU & Halting co-processor
87
8864NOTICE:  BL31: v1.3(release):23b153a63
89NOTICE:  BL31: Built : 22:39:57, Dec  9 2019
90ERROR:   Error initializing runtime service trusty_fast
91[0001.990] RamCode = 0
92[0001.995] LPDDR4 Training: Read DT: Number of tables = 2
93[0002.000] EMC Training (SRC-freq: 204000; DST-freq: 1600000)
94[0002.012] EMC Training Successful
95[0002.015] 408000 not found in DVFS table
96[0002.022] RamCode = 0
97[0002.025] DT Write: emc-table@204000 succeeded
98[0002.031] DT Write: emc-table@1600000 succeeded
99[0002.035] LPDDR4 Training: Write DT: Number of tables = 2
100[0002.093]
101[0002.094] Debug Init done
102[0002.097] Marked DTB cacheable
103[0002.100] Bootloader DTB loaded at 0x83000000
104[0002.104] Marked DTB cacheable
105[0002.107] Kernel DTB loaded at 0x83100000
106[0002.111] DeviceTree Init done
107[0002.127] Pinmux applied successfully
108[0002.131] gicd_base: 0x50041000
109[0002.135] gicc_base: 0x50042000
110[0002.138] Interrupts Init done
111[0002.142] Using base:0x60005090 & irq:208 for tick-timer
112[0002.147] Using base:0x60005098 for delay-timer
113[0002.152] platform_init_timer: DONE
114[0002.155] Timer(tick) Init done
115[0002.159] osc freq = 38400 khz
116[0002.163]
117[0002.164] Welcome to L4T Cboot
118[0002.167]
119[0002.168] Cboot Version: 00.00.2018.01-t210-40c3ff9c
120[0002.173] calling constructors
121[0002.176] initializing heap
122[0002.179] initializing threads
123[0002.182] initializing timers
124[0002.185] creating bootstrap completion thread
125[0002.189] top of bootstrap2()
126[0002.192] CPU: ARM Cortex A57
127[0002.195] CPU: MIDR: 0x411FD071, MPIDR: 0x80000000
128[0002.199] initializing platform
129[0002.253] Config for emmc ddr50 mode completed
130[0002.258] sdmmc bdev is already initialized
131[0002.262] Enable APE clock
132[0002.264] Un-powergate APE partition
133[0002.268] of_register: registering tegra_udc to of_hal
134[0002.273] of_register: registering inv20628-driver to of_hal
135[0002.279] of_register: registering ads1015-driver to of_hal
136[0002.284] of_register: registering lp8557-bl-driver to of_hal
137[0002.290] of_register: registering bq2419x_charger to of_hal
138[0002.296] of_register: registering bq27441_fuel_gauge to of_hal
139[0002.307] gpio framework initialized
140[0002.310] of_register: registering tca9539_gpio to of_hal
141[0002.316] of_register: registering tca9539_gpio to of_hal
142[0002.321] of_register: registering i2c_bus_driver to of_hal
143[0002.327] of_register: registering i2c_bus_driver to of_hal
144[0002.332] of_register: registering i2c_bus_driver to of_hal
145[0002.338] pmic framework initialized
146[0002.341] of_register: registering max77620_pmic to of_hal
147[0002.347] regulator framework initialized
148[0002.351] of_register: registering tps65132_bl_driver to of_hal
149[0002.357] initializing target
150[0002.363] gpio_driver_register: register 'tegra_gpio_driver' driver
151[0002.373] fixed regulator driver initialized
152[0002.391] initializing OF layer
153[0002.394] NCK carveout not present
154[0002.397] Skipping dts_overrides
155[0002.401] of_children_init: Ops found for compatible string nvidia,tegra210-i2c
156[0002.418] I2C Bus Init done
157[0002.420] of_children_init: Ops found for compatible string nvidia,tegra210-i2c
158[0002.431] I2C Bus Init done
159[0002.433] of_children_init: Ops found for compatible string nvidia,tegra210-i2c
160[0002.444] I2C Bus Init done
161[0002.446] of_children_init: Ops found for compatible string nvidia,tegra210-i2c
162[0002.457] I2C Bus Init done
163[0002.459] of_children_init: Ops found for compatible string nvidia,tegra210-i2c
164[0002.470] I2C Bus Init done
165[0002.472] of_children_init: Ops found for compatible string maxim,max77620
166[0002.483] max77620_init using irq 118
167[0002.488] register 'maxim,max77620' pmic
168[0002.492] gpio_driver_register: register 'max77620-gpio' driver
169[0002.498] of_children_init: Ops found for compatible string nvidia,tegra210-i2c
170[0002.509] I2C Bus Init done
171[0002.512] NCK carveout not present
172[0002.522] Find /i2c@7000c000's alias i2c0
173[0002.526] get eeprom at 1-a0, size 256, type 0
174[0002.535] Find /i2c@7000c500's alias i2c2
175[0002.539] get eeprom at 3-a0, size 256, type 0
176[0002.543] get eeprom at 3-ae, size 256, type 0
177[0002.548] pm_ids_update: Updating 1,a0, size 256, type 0
178[0002.553] I2C slave not started
179[0002.556] I2C write failed
180[0002.558] Writing offset failed
181[0002.561] eeprom_init: EEPROM read failed
182[0002.565] pm_ids_update: eeprom init failed
183[0002.570] pm_ids_update: Updating 3,a0, size 256, type 0
184[0002.600] pm_ids_update: The pm board id is 3448-0002-400
185[0002.606] Adding plugin-manager/ids/3448-0002-400=/i2c@7000c500:module@0x50
186[0002.614] pm_ids_update: pm id update successful
187[0002.619] pm_ids_update: Updating 3,ae, size 256, type 0
188[0002.624] I2C slave not started
189[0002.627] I2C write failed
190[0002.630] Writing offset failed
191[0002.633] eeprom_init: EEPROM read failed
192[0002.637] pm_ids_update: eeprom init failed
193[0002.667] eeprom_get_mac: EEPROM invalid MAC address (all 0xff)
194[0002.673] shim_eeprom_update_mac:267: Failed to update 0 MAC address in DTB
195[0002.681] eeprom_get_mac: EEPROM invalid MAC address (all 0xff)
196[0002.687] shim_eeprom_update_mac:267: Failed to update 1 MAC address in DTB
197[0002.695] updating /chosen/nvidia,ethernet-mac node 00:04:4b:e5:dd:c6
198[0002.702] Plugin Manager: Parse ODM data 0x00094000
199[0002.712] shim_cmdline_install: /chosen/bootargs: root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 console=ttyS0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 sdhci_tegra.en_boot_part_access=1
200[0002.736] Find /i2c@7000c000's alias i2c0
201[0002.740] get eeprom at 1-a0, size 256, type 0
202[0002.749] Find /i2c@7000c500's alias i2c2
203[0002.753] get eeprom at 3-a0, size 256, type 0
204[0002.757] get eeprom at 3-ae, size 256, type 0
205[0002.762] pm_ids_update: Updating 1,a0, size 256, type 0
206[0002.767] I2C slave not started
207[0002.770] I2C write failed
208[0002.773] Writing offset failed
209[0002.776] eeprom_init: EEPROM read failed
210[0002.780] pm_ids_update: eeprom init failed
211[0002.784] pm_ids_update: Updating 3,a0, size 256, type 0
212[0002.814] pm_ids_update: The pm board id is 3448-0002-400
213[0002.820] Adding plugin-manager/ids/3448-0002-400=/i2c@7000c500:module@0x50
214[0002.827] pm_ids_update: pm id update successful
215[0002.832] pm_ids_update: Updating 3,ae, size 256, type 0
216[0002.837] I2C slave not started
217[0002.840] I2C write failed
218[0002.843] Writing offset failed
219[0002.846] eeprom_init: EEPROM read failed
220[0002.850] pm_ids_update: eeprom init failed
221[0002.880] Add serial number:1422819018334 as DT property
222[0002.888] Applying platform configs
223[0002.894] platform-init is not present. Skipping
224[0002.899] calling apps_init()
225[0002.915] Found 17 GPT partitions in "sdmmc3_user"
226[0002.920] Proceeding to Cold Boot
227[0002.923] starting app android_boot_app
228[0002.927] Device state: unlocked
229[0002.930] display console init
230[0002.938] could not find regulator
231[0002.962] hdmi cable not connected
232[0002.965] is_hdmi_needed: HDMI not connected, returning false
233[0002.971] hdmi is not connected
234[0002.974][0002.978] DT entry for leds-pwm not found
235 sor0 is not supported
236[0002.984] display_console_init: no valid display out_type
237[0002.992] subnode volume_up is not found !
238[0002.996] subnode back is not found !
239[0002.999] subnode volume_down is not found !
240[0003.004] subnode menu is not found !
241[0003.007] Gpio keyboard init success
242[0003.070] found decompressor handler: lz4-legacy
243[0003.085] decompressing blob (type 1)...
244[0003.118] display_resolution: No display init
245[0003.122] Failed to retrieve display resolution
246[0003.127] Could not load/initialize BMP blob...ignoring
247[0003.193] decompressor handler not found
248[0003.197] load_firmware_blob: Firmware blob loaded, entries=2
249[0003.202] -------> se_aes_verify_sbk_clear: 747
250[0003.207] se_aes_verify_sbk_clear: Error
251[0003.211] bl_battery_charging: connected to external power supply
252[0003.218] xusb is supported
253[0003.224] error while finding nvidia,portmap
254[0003.728] xusb blob version 0 size 124416
255[0003.732] firmware size 124416
256[0003.737] Firmware timestamp: 0x5da88fc3, Version: 50.25 release
257[0003.745] xhci0: 64 bytes context size, 32-bit DMA
258[0003.785] usbus0: 5.0Gbps Super Speed USB v3.0
259[0003.805] uhub0: <Nvidia XHCI root HUB, class 9/0, rev 3.00/1.00, addr 1> on usbus0
260[0004.455] uhub0: 9 ports with 9 removable, self powered
261[0005.455] failed to get HID devices
262[0005.458] failed to init xhci or no usb device attached
263[0005.465] display_console_ioctl: No display init
264[0005.470] switch_backlight failed
265[0005.483] device_query_partition_size: failed to open partition sdmmc3_user:MSC !
266[0005.491] MSC Partition not found
267[0005.505] device_query_partition_size: failed to open partition sdmmc3_user:USP !
268[0005.512] USP partition read failed!
269[0005.515] blob_init: blob-partition USP header read failed
270[0005.521] android_boot Unable to update recovery partition
271[0005.526] kfs_getpartname: name = LNX-1
272[0005.530] Loading kernel from LNX-1
273[0005.598] load kernel from storage
274[0005.607] decompressor handler not found
275[0005.627] Successfully loaded kernel and ramdisk images
276[0005.634] display_resolution: No display init
277[0005.638] Failed to retrieve display resolution
278[0005.642] bmp blob is not loaded and initialized
279[0005.647] Failed to display boot-logo
280[0005.650] NCK carveout not present
281[0005.654] Skipping dts_overrides
282[0005.657] NCK carveout not present
283[0005.667] Find /i2c@7000c000's alias i2c0
284[0005.671] get eeprom at 1-a0, size 256, type 0
285[0005.680] Find /i2c@7000c500's alias i2c2
286[0005.683] get eeprom at 3-a0, size 256, type 0
287[0005.688] get eeprom at 3-ae, size 256, type 0
288[0005.692] pm_ids_update: Updating 1,a0, size 256, type 0
289[0005.698] I2C slave not started
290[0005.701] I2C write failed
291[0005.703] Writing offset failed
292[0005.706] eeprom_init: EEPROM read failed
293[0005.710] pm_ids_update: eeprom init failed
294[0005.714] pm_ids_update: Updating 3,a0, size 256, type 0
295[0005.744] pm_ids_update: The pm board id is 3448-0002-400
296[0005.751] Adding plugin-manager/ids/3448-0002-400=/i2c@7000c500:module@0x50
297[0005.759] pm_ids_update: pm id update successful
298[0005.763] pm_ids_update: Updating 3,ae, size 256, type 0
299[0005.769] I2C slave not started
300[0005.772] I2C write failed
301[0005.774] Writing offset failed
302[0005.777] eeprom_init: EEPROM read failed
303[0005.781] pm_ids_update: eeprom init failed
304[0005.812] eeprom_get_mac: EEPROM invalid MAC address (all 0xff)
305[0005.817] shim_eeprom_update_mac:267: Failed to update 0 MAC address in DTB
306[0005.826] eeprom_get_mac: EEPROM invalid MAC address (all 0xff)
307[0005.832] shim_eeprom_update_mac:267: Failed to update 1 MAC address in DTB
308[0005.840] updating /chosen/nvidia,ethernet-mac node 00:04:4b:e5:dd:c6
309[0005.847] Plugin Manager: Parse ODM data 0x00094000
310[0005.857] shim_cmdline_install: /chosen/bootargs: root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 console=ttyS0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 sdhci_tegra.en_boot_part_access=1
311[0005.874] Add serial number:1422819018334 as DT property
312[0005.883] "bpmp" doesn't exist, creating
313[0005.889] Updated bpmp info to DTB
314[0005.894] Updated initrd info to DTB
315[0005.897] "proc-board" doesn't exist, creating
316[0005.903] Updated board info to DTB
317[0005.906] "pmu-board" doesn't exist, creating
318[0005.912] Updated board info to DTB
319[0005.915] "display-board" doesn't exist, creating
320[0005.921] Updated board info to DTB
321[0005.924] "reset" doesn't exist, creating
322[0005.929] Updated reset info to DTB
323[0005.932] display_console_ioctl: No display init
324[0005.937] display_console_ioctl: No display init
325[0005.941] display_console_ioctl: No display init
326[0005.946] Cmdline: tegraid=21.1.2.0.0 ddr_die=4096M@2048M section=512M memtype=0 vpr_resize usb_port_owner_info=0 lane_owner_info=0 emc_max_dvfs=0 touch_id=0@63 video=tegrafb no_console_suspend=1 console=ttyS0,115200n8 debug_uartport=lsport,2 earlyprintk=uart8250-32bit,0x70006000 maxcpus=4 usbcore.old_scheme_first=1 lp0_vec=0x1000@0xff780000 core_edp_mv=1075 core_edp_ma=4000
327[0005.980] DTB cmdline: root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 console=ttyS0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 sdhci_tegra.en_boot_part_access=1
328[0005.995] boot image cmdline: root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 console=ttyS0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 sdhci_tegra.en_boot_part_access=1
329[0006.011] Updated bootarg info to DTB
330[0006.015] Adding uuid 00000001644495871c0000000afc8380 to DT
331[0006.021] Adding eks info 0 to DT
332[0006.026] WARNING: Failed to pass NS DRAM ranges to TOS, err: -7
333[0006.032] Updated memory info to DTB
334[0006.041] set vdd_core voltage to 1075 mv
335[0006.045] setting 'vdd-core' regulator to 1075000 micro volts
336[0006.065] Found secure-pmc; disable BPMP
337
338
339U-Boot 2016.07-g0536cf2a27 (Dec 09 2019 - 22:40:32 -0800)
340
341TEGRA210
342Model: NVIDIA P3450-Porg
343Board: NVIDIA P3450-PORG
344DRAM:  4 GiB
345MMC:   Tegra SD/MMC: 0, Tegra SD/MMC: 1
346SF: Failed to get idcodes
347*** Warning - spi_flash_probe() failed, using default environment
348
349In:    serial
350Out:   serial
351Err:   serial
352Net:   No ethernet found.
353Card did not respond to voltage select!
354** Bad device mmc 1 **
355Hit any key to stop autoboot:  0
356Card did not respond to voltage select!
357switch to partitions #0, OK
358mmc0(part 0) is current device
359Scanning mmc 0:1...
360Found /boot/extlinux/extlinux.conf
361Retrieving file: /boot/extlinux/extlinux.conf
362727 bytes read in 141 ms (4.9 KiB/s)
3631:      primary kernel
364Retrieving file: /boot/initrd
3655487751 bytes read in 174 ms (30.1 MiB/s)
366Retrieving file: /boot/Image
36734191368 bytes read in 807 ms (40.4 MiB/s)
368append: tegraid=21.1.2.0.0 ddr_die=4096M@2048M section=512M memtype=0 vpr_resize usb_port_owner_info=0 lane_owner_info=0 emc_max_dvfs=0 touch_id=0@63 video=tegrafb no_console_suspend=1 console=ttyS0,115200n8 debug_uartport=lsport,2 earlyprintk=uart8250-32bit,0x70006000 maxcpus=4 usbcore.old_scheme_first=1 lp0_vec=0x1000@0xff780000 core_edp_mv=1075 core_edp_ma=4000  root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 console=ttyS0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 sdhci_tegra.en_boot_part_access=1    root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 console=ttyS0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 sdhci_tegra.en_boot_part_access=1
369## Flattened Device Tree blob at 83100000
370   Booting using the fdt blob at 0x83100000
371   reserving fdt memory region: addr=80000000 size=20000
372   Using Device Tree in place at 0000000083100000, end 00000000831776fe
373
374Starting kernel ...
375
376<hit enter to activate fiq debugger>
377[    0.000000] Booting Linux on physical CPU 0x0
378[    0.000000] Linux version 4.9.140-tegra (buildbrain@mobile-u64-2713) (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05) ) #1 SMP PREEMPT Mon Dec 9 22:47:42 PST 2019
379[    0.000000] Boot CPU: AArch64 Processor [411fd071]
380[    0.000000] OF: fdt:memory scan node memory@80000000, reg size 48,
381[    0.000000] OF: fdt: - 80000000 ,  7ee00000
382[    0.000000] OF: fdt: - 100000000 ,  7f200000
383[    0.000000] OF: fdt:Reserved memory: failed to reserve memory for node 'fb0_carveout': base 0x0000000000000000, size 0 MiB
384[    0.000000] OF: fdt:Reserved memory: failed to reserve memory for node 'fb0_carveout': base 0x0000000000000000, size 0 MiB
385[    0.000000] OF: fdt:Reserved memory: failed to reserve memory for node 'fb1_carveout': base 0x0000000000000000, size 0 MiB
386[    0.000000] OF: fdt:Reserved memory: failed to reserve memory for node 'fb1_carveout': base 0x0000000000000000, size 0 MiB
387[    0.000000] OF: reserved mem: initialized node vpr-carveout, compatible id nvidia,vpr-carveout
388[    0.000000] OF: reserved mem: initialized node iram-carveout, compatible id nvidia,iram-carveout
389[    0.000000] OF: reserved mem: initialized node ramoops_carveout, compatible id nvidia,ramoops
390[    0.000000] cma: Reserved 64 MiB at 0x00000000fac00000
391[    0.000000] psci: probing for conduit method from DT.
392[    0.000000] psci: PSCIv1.0 detected in firmware.
393[    0.000000] psci: Using standard PSCI v0.2 function IDs
394[    0.000000] psci: MIGRATE_INFO_TYPE not supported.
395[    0.000000] psci: SMC Calling Convention v1.1
396[    0.000000] percpu: Embedded 25 pages/cpu @ffffffc0fefb2000 s61592 r8192 d32616 u102400
397[    0.000000] CPU features: enabling workaround for ARM erratum 832075
398[    0.000000] Speculative Store Bypass Disable mitigation not required
399[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 1023544
400[    0.000000] Kernel command line: tegraid=21.1.2.0.0 ddr_die=4096M@2048M section=512M memtype=0 vpr_resize usb_port_owner_info=0 lane_owner_info=0 emc_max_dvfs=0 touch_id=0@63 video=tegrafb no_console_suspend=1 console=ttyS0,115200n8 debug_uartport=lsport,2 earlyprintk=uart8250-32bit,0x70006000 maxcpus=4 usbcore.old_scheme_first=1 lp0_vec=0x1000@0xff780000 core_edp_mv=1075 core_edp_ma=4000  root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 console=ttyS0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 sdhci_tegra.en_boot_part_access=1    root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 console=ttyS0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0 sdhci_tegra.en_boot_part_access=1
401[    0.000000] log_buf_len individual max cpu contribution: 32768 bytes
402[    0.000000] log_buf_len total cpu_extra contributions: 98304 bytes
403[    0.000000] log_buf_len min size: 32768 bytes
404[    0.000000] log_buf_len: 131072 bytes
405[    0.000000] early log buf free: 29436(89%)
406[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
407[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
408[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
409[    0.000000] Memory: 3570416K/4159488K available (15230K kernel code, 2926K rwdata, 6620K rodata, 8576K init, 609K bss, 113936K reserved, 475136K cma-reserved)
410[    0.000000] Virtual kernel memory layout:
411[    0.000000]     modules : 0xffffff8000000000 - 0xffffff8008000000   (   128 MB)
412[    0.000000]     vmalloc : 0xffffff8008000000 - 0xffffffbebfff0000   (   250 GB)
413[    0.000000]       .text : 0xffffff8008080000 - 0xffffff8008f60000   ( 15232 KB)
414[    0.000000]     .rodata : 0xffffff8008f60000 - 0xffffff80095e0000   (  6656 KB)
415[    0.000000]       .init : 0xffffff80095e0000 - 0xffffff8009e40000   (  8576 KB)
416[    0.000000]       .data : 0xffffff8009e40000 - 0xffffff800a11b808   (  2927 KB)
417[    0.000000]        .bss : 0xffffff800a11b808 - 0xffffff800a1b3dbc   (   610 KB)
418[    0.000000]     fixed   : 0xffffffbefe7fd000 - 0xffffffbefec00000   (  4108 KB)
419[    0.000000]     PCI I/O : 0xffffffbefee00000 - 0xffffffbeffe00000   (    16 MB)
420[    0.000000]     vmemmap : 0xffffffbf00000000 - 0xffffffc000000000   (     4 GB maximum)
421[    0.000000]               0xffffffbf00000000 - 0xffffffbf03fc8000   (    63 MB actual)
422[    0.000000]     memory  : 0xffffffc000000000 - 0xffffffc0ff200000   (  4082 MB)
423[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
424[    0.000000] Preemptible hierarchical RCU implementation.
425[    0.000000]  Build-time adjustment of leaf fanout to 64.
426[    0.000000]  RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=4.
427[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=4
428[    0.000000] NR_IRQS:64 nr_irqs:64 0
429[    0.000000] /interrupt-controller@60004000: 192 interrupts forwarded to /interrupt-controller
430[    0.000000] t210 clock and reset probe
431[    0.000000] tegra-pmc: get_secure_pmc_setting: done secure_pmc=1
432[    0.000000] clk_cbus_recalc_rate: no gbus parent
433[    0.000000] clk_cbus_recalc_rate: no gbus parent
434[    0.000000] clk_cbus_recalc_rate: no gbus parent
435[    0.000000] clk_cbus_recalc_rate: no gbus parent
436[    0.000000] clk_cbus_recalc_rate: no gbus parent
437[    0.000000] arm_arch_timer: Architected cp15 timer(s) running at 19.20MHz (phys).
438[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x46d987e47, max_idle_ns: 440795202767 ns
439[    0.000006] sched_clock: 56 bits at 19MHz, resolution 52ns, wraps every 4398046511078ns
440[    0.001722] Console: colour dummy device 80x25
441[    0.002570] console [tty0] enabled
442[    0.002595] kmemleak: Kernel memory leak detector disabled
443[    0.002627] Calibrating delay loop (skipped), value calculated using timer frequency.. 38.40 BogoMIPS (lpj=76800)
444[    0.002658] pid_max: default: 32768 minimum: 301
445[    0.003114] Security Framework initialized
446[    0.003349] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes)
447[    0.003368] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes)
448[    0.004554] ftrace: allocating 47001 entries in 184 pages
449[    0.176081] ASID allocator initialised with 65536 entries
450[    0.215974] tegra-id: chipid=22117.
451[    0.216020] tegra-id: opt_subrevision=0.
452[    0.216050] Tegra Speedo/IDDQ fuse revision 4
453[    0.216065] Tegra: CPU Speedo ID 9, SoC Speedo ID 0, GPU Speedo ID 2
454[    0.216080] Tegra: CPU Process ID 0, SoC Process ID 1, GPU Process ID 0
455[    0.216096] Tegra: CPU Speedo Value 2112, SoC Speedo Value 2025, GPU Speedo Value 2133
456[    0.216117] Tegra: CPU IDDQ Value 2424, SoC IDDQ Value 2772, GPU IDDQ Value 3435
457[    0.216153] Tegra Revision: A02 SKU: 0x8f CPU Process: 0 SoC Process: 1
458[    0.216179] DTS File Name: /dvs/git/dirty/git-master_linux/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t210/porg/kernel-dts/tegra210-p3448-0002-p3449-0000-b00.dts
459[    0.216254] DTB Build time: Dec  9 2019 22:51:55
460[    0.265032] CPU1: Booted secondary processor [411fd071]
461[    0.296976] CPU2: Booted secondary processor [411fd071]
462[    0.328939] CPU3: Booted secondary processor [411fd071]
463[    0.329025] Brought up 4 CPUs
464[    0.329092] SMP: Total of 4 processors activated.
465[    0.329110] CPU features: detected feature: 32-bit EL0 Support
466[    0.329385] CPU: All CPU(s) started at EL2
467[    0.329416] alternatives: patching kernel code
468[    0.337479] devtmpfs: initialized
469[    0.374636] Initilizing CustomIPI irq domain
470[    0.375061] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
471[    0.375107] futex hash table entries: 1024 (order: 4, 65536 bytes)
472[    0.385593] pinctrl core: initialized pinctrl subsystem
473[    0.386264] OS set in device tree is not L4T.
474[    0.386668] regulator-dummy: no parameters
475[    0.386979] Initializing plugin-manager
476[    0.387099] Plugin module not found
477[    0.387334] node /plugin-manager/fragement@0 match with board >=3448-0002-100
478[    0.387902] node /plugin-manager/fragment@1 match with board >=3448-0002-101
479[    0.388416] node /plugin-manager/fragment@3 match with board >=3448-0002-100
480[    0.389154] node /plugin-manager/fragement@6 match with odm-data enable-tegra-wdt
481[    0.389610] node /plugin-manager/fragement@8 match with odm-data enable-tegra-wdt
482[    0.390251] node /plugin-manager/fragement@10 match with board >=3448-0002-300
483[    0.392367] node /plugin-manager/fragement@11 match with board >=3448-0002-300
484[    0.395827] NET: Registered protocol family 16
485[    0.397196] pstore: using zlib compression
486[    0.397863] console [pstore-1] enabled
487[    0.397881] pstore: Registered ramoops as persistent store backend
488[    0.397899] ramoops: attached 0x200000@0xb0000000, ecc: 0/0
489[    0.413053] cpuidle: using governor menu
490[    0.417304] tegra_smmu 70019000.iommu: Loaded Tegra IOMMU driver
491[    0.418971] vdso: 2 pages (1 code @ ffffff8008f67000, 1 data @ ffffff8009e44000)
492[    0.419017] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
493[    0.421511] atomic_pool_init():622: DMA: preallocated 1024 KiB pool for atomic allocations
494[    0.424154] tegra_powergate_init: DONE
495[    0.424195] DTS File Name: /dvs/git/dirty/git-master_linux/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t210/porg/kernel-dts/tegra210-p3448-0002-p3449-0000-b00.dts
496[    0.424232] DTB Build time: Dec  9 2019 22:51:55
497[    0.426086] Tegra reboot handler registered.
498[    0.430609] iommu: Adding device tegra-carveouts to group 0
499[    0.430769] platform tegra-carveouts: domain=ffffffc0f9434318 allocates as[0]=ffffffc0f94080a8
500[    0.431157] iommu: Adding device smmu_test to group 1
501[    0.431221] platform smmu_test: domain=ffffffc0f9434558 allocates as[0]=ffffffc0f9408110
502[    0.432045] mc: mapped MMIO address: 0xffffff800802e000 -> 0x70019000
503[    0.432127] mc: mapped MMIO address: 0xffffff8008065000 -> 0x7001c000
504[    0.432196] mc: mapped MMIO address: 0xffffff8008079000 -> 0x7001d000
505[    0.432219] nv-tegra-mc 70019000.mc: No mssnvlink node
506[    0.432255] mc-err: mcerr ops are set to t21x
507[    0.441986] iommu: Adding device 70090000.xusb to group 2
508[    0.442318] iommu: Adding device 70006000.serial to group 3
509[    0.442417] platform 70006000.serial: domain=ffffffc0f94ac618 allocates as[0]=ffffffc0f9408178
510[    0.442878] iommu: Adding device 70006040.serial to group 4
511[    0.443172] iommu: Adding device 70006200.serial to group 5
512[    0.443414] iommu: Adding device sound to group 6
513[    0.443475] platform sound: domain=ffffffc0f94acb58 allocates as[0]=ffffffc0f94081e0
514[    0.444043] iommu: Adding device 7000d400.spi to group 7
515[    0.444325] iommu: Adding device 7000d600.spi to group 8
516[    0.444677] iommu: Adding device 50000000.host1x to group 9
517[    0.444966] iommu: Adding device 54080000.vi to group 10
518[    0.445414] iommu: Adding device 54600000.isp to group 11
519[    0.445693] iommu: Adding device 54680000.isp to group 12
520[    0.445980] iommu: Adding device tegradc.0 to group 13
521[    0.446076] platform tegradc.0: domain=ffffffc0f94b9918 allocates as[0]=ffffffc0f9408248
522[    0.446613] platform tegradc.0: IOVA linear map 0x00000000d7000000(19000000)
523[    0.446958] iommu: Adding device tegradc.1 to group 14
524[    0.447021] platform tegradc.1: domain=ffffffc0f94b9b58 allocates as[0]=ffffffc0f94082b0
525[    0.447541] platform tegradc.1: IOVA linear map 0x00000000d7000000(19000000)
526[    0.447798] iommu: Adding device 54340000.vic to group 15
527[    0.448021] iommu: Adding device 544c0000.nvenc to group 16
528[    0.448228] iommu: Adding device 54500000.tsec to group 17
529[    0.448453] iommu: Adding device 54100000.tsecb to group 18
530[    0.448671] iommu: Adding device 54480000.nvdec to group 19
531[    0.448872] iommu: Adding device 54380000.nvjpg to group 20
532[    0.450054] iommu: Adding device 546c0000.i2c to group 21
533[    0.450416] iommu: Adding device 57000000.gpu to group 22
534[    0.450483] platform 57000000.gpu: domain=ffffffc0f94c4b58 allocates as[0]=ffffffc0f9408318
535[    0.450542] platform 57000000.gpu: domain=ffffffc0f94c4b58 allocates as[1]=ffffffc0f9408380
536[    0.450602] platform 57000000.gpu: domain=ffffffc0f94c4b58 allocates as[2]=ffffffc0f94083e8
537[    0.450661] platform 57000000.gpu: domain=ffffffc0f94c4b58 allocates as[3]=ffffffc0f9408450
538[    0.451547] tegra-pmc 7000e400.pmc: i2c-thermtrip node not found, emergency thermal reset disabled.
539[    0.451585] tegra-pmc 7000e400.pmc: scratch reg offset dts data not present
540[    0.451611] tegra-pmc: ### PMC reset source: TEGRA_POWER_ON_RESET
541[    0.451631] tegra-pmc: ### PMC reset level: TEGRA_RESET_LEVEL_WARM
542[    0.451649] tegra-pmc: ### PMC reset status reg: 0x0
543[    0.501139] padctrl padctrl.0: Pad control driver tegra-pmc-padctrl registered
544[    0.501176] tegra-pmc: Clear bootloader IO dpd settings
545[    0.501211] tegra-pmc 7000e400.pmc: IO padctrl driver initialized
546[    0.501287] tegra-pmc 7000e400.pmc: PMC: Successfully configure bootrom reset commands
547[    0.501594] iommu: Adding device 70012000.se to group 23
548[    0.502469] iommu: Adding device 7000c000.i2c to group 24
549[    0.502786] iommu: Adding device 7000c400.i2c to group 25
550[    0.503115] iommu: Adding device 7000c500.i2c to group 26
551[    0.503449] iommu: Adding device 7000c700.i2c to group 27
552[    0.503771] iommu: Adding device 7000d000.i2c to group 28
553[    0.504123] iommu: Adding device 7000d100.i2c to group 29
554[    0.504473] iommu: Adding device sdhci-tegra.3 to group 30
555[    0.504545] platform sdhci-tegra.3: domain=ffffffc0f9554cd8 allocates as[0]=ffffffc0f94084b8
556[    0.505546] iommu: Adding device 700d0000.xudc to group 31
557[    0.509657] vdd-ac-bat: 5000 mV
558[    0.510092] vdd-5v0-sys: 5000 mV
559[    0.511196] vdd-5v0-hdmi: supplied by vdd-5v0-sys
560[    0.511284] vdd-5v0-hdmi: 5000 mV
561[    0.511755] vdd-1v8-sys: 1800 mV
562[    0.512209] vdd-fan: supplied by vdd-5v0-sys
563[    0.512261] vdd-fan: 5000 mV
564[    0.512721] vdd-usb-vbus: supplied by vdd-5v0-sys
565[    0.512796] vdd-usb-vbus: 5000 mV
566[    0.513427] vdd-usb-vbus2: 5000 mV
567[    0.541973] HugeTLB registered 2 MB page size, pre-allocated 0 pages
568[    0.544336] gpio gpiochip0: gpio-line-names specifies 240 line names but there are 256 lines on the chip
569[    0.546018] GPIO line 151 (camera-control-output-low) hogged as output/low
570[    0.546059] GPIO line 152 (camera-control-output-low) hogged as output/low
571[    0.546115] GPIO line 6 (system-suspend-gpio) hogged as output/high
572[    0.546504] gpiochip_setup_dev: registered GPIOs 0 to 255 on device: gpiochip0 (tegra-gpio)
573[    0.554933] eventlib_kernel: keventlib is initialized, test id: 0
574[    0.555313] SCSI subsystem initialized
575[    0.555848] usbcore: registered new interface driver usbfs
576[    0.555928] usbcore: registered new interface driver hub
577[    0.556023] usbcore: registered new device driver usb
578[    0.559981] max77620 4-003c: PMIC Version OTP:0x35 and ES:0x8
579[    0.565199] vdd-core: 600 <--> 1162 mV at 1075 mV
580[    0.565867] random: fast init done
581[    0.566210] vdd-ddr-1v1: Bringing 1125000uV into 1150000-1150000uV
582[    0.569052] vdd-ddr-1v1: 1150 mV
583[    0.573082] vdd-pre-reg-1v35: 1350 mV
584[    0.577048] vdd-1v8: 1800 mV
585[    0.581047] avdd-sys-1v2: 1200 mV
586[    0.585046] vdd-pex-1v0: 1050 mV
587[    0.585718] vddio-sdmmc-ap: 1800 <--> 3300 mV at 3300 mV
588[    0.586273] max77620-ldo3: at 3100 mV
589[    0.589049] vdd-rtc: 850 <--> 1100 mV at 1000 mV
590[    0.589599] max77620-ldo5: at 3100 mV
591[    0.593048] vddio-sdmmc3-ap: 1800 <--> 3300 mV at 2800 mV
592[    0.597045] avdd-1v05-pll: 1050 mV
593[    0.601046] avdd-io-hdmi-dp: 1050 mV
594[    0.603632] GPIO line 505 (spmic-default-output-high) hogged as output/high
595[    0.603916] gpiochip_setup_dev: registered GPIOs 504 to 511 on device: gpiochip1 (max77620-gpio)
596[    0.604216] max77620 4-003c: max77620 probe successful
597[    0.606831] media: Linux media interface: v0.10
598[    0.606912] Linux video capture interface: v2.00
599[    0.607821] pps_core: LinuxPPS API ver. 1 registered
600[    0.607847] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
601[    0.607891] PTP clock support registered
602[    0.611705] tegra_fiq_debugger_init: found FIQ source (IRQ 97)
603[    0.618077] tegra210-emc 7001b000.external-memory-controller: validated EMC DFS table
604[    0.618887] Advanced Linux Sound Architecture Driver Initialized.
605[    0.619529] Bluetooth: Core ver 2.22
606[    0.619601] NET: Registered protocol family 31
607[    0.619620] Bluetooth: HCI device and connection manager initialized
608[    0.619648] Bluetooth: HCI socket layer initialized
609[    0.619670] Bluetooth: L2CAP socket layer initialized
610[    0.619709] Bluetooth: SCO socket layer initialized
611[    0.621534] tegra210_dvfs: no clock found for sdmmc2_ddr
612[    0.621574] tegra210_dvfs: no clock found for sdmmc4_ddr
613[    0.621638] tegra210_dvfs: no clock found for sdmmc1_ddr
614[    0.621667] tegra210_dvfs: no clock found for sdmmc3_ddr
615[    0.624793] tegra_dvfs: Unable to get vdd-cpu rail for step info, defering probe
616[    0.625995] vdd-3v3-sys: supplied by vdd-5v0-sys
617[    0.626108] vdd-3v3-sys: 3300 mV
618[    0.626382] vdd-1v8-sys: supplied by vdd-3v3-sys
619[    0.629111] vdd-usb-vbus2: supplied by vdd-3v3-sys
620[    0.629576] vdd-3v3-sd: supplied by vdd-3v3-sys
621[    0.629628] vdd-3v3-sd: 3300 mV
622[    0.630729] avdd-io-edp-1v05: supplied by avdd-1v05-pll
623[    0.630785] avdd-io-edp-1v05: 1050 mV
624[    0.631223] vdd-usb-hub-en: supplied by vdd-1v8-sys
625[    0.631275] vdd-usb-hub-en: 5000 mV
626[    0.632555] camchar: rtcpu character device driver loaded
627[    0.633292] extcon-gpio-states extcon:extcon@1: Cable state:0, cable id:0
628[    0.634626] clocksource: Switched to clocksource arch_sys_counter
629[    0.673985] VFS: Disk quotas dquot_6.6.0
630[    0.674151] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
631[    0.674692] nvmap_heap_init: nvmap_heap_init: created heap block cache
632[    0.675130] dma_declare_coherent_resizable_cma_memory:324: resizable heap=vpr, base=0x00000000d7000000, size=0x19000000
633[    0.675179]  dma-vpr: heap size is not multiple of cma_chunk_size heap_info->num_chunks (13) rem_chunk_size(0x1000000)
634[    0.675402] cma: enabled page replacement for spfn=d7000, epfn=f0000
635[    0.675425] dma_declare_coherent_resizable_cma_memory:373: resizable cma heap=vpr create successful
636[    0.675454] tegra-carveouts tegra-carveouts: assigned reserved memory node vpr-carveout
637[    0.675501] tegra-carveouts tegra-carveouts: iram :dma coherent mem declare 0x0000000040001000,258048
638[    0.675528] tegra-carveouts tegra-carveouts: assigned reserved memory node iram-carveout
639[    0.675559] nvmap: nvmap_select_cache_ops() nvmap cache ops set to set/ways
640[    0.675581] nvmap_page_pool_init: Total RAM pages: 1011388
641[    0.675599] nvmap_page_pool_init: nvmap page pool size: 126423 pages (493 MB)
642[    0.675805] nvmap_background_zero_thread: PP zeroing thread starting.
643[    0.676214] misc nvmap: created heap iram base 0x0000000040001000 size (252KiB)
644[    0.677152] misc nvmap: created heap vpr base 0x00000000d7000000 size (409600KiB)
645[    0.685340] thermal thermal_zone0: Registering thermal zone thermal_zone0 for type AO-therm
646[    0.685778] thermal thermal_zone1: Registering thermal zone thermal_zone1 for type CPU-therm
647[    0.686055] thermal thermal_zone2: Registering thermal zone thermal_zone2 for type GPU-therm
648[    0.686286] thermal thermal_zone3: Registering thermal zone thermal_zone3 for type PLL-therm
649[    0.686480] thermal thermal_zone4: Registering thermal zone thermal_zone4 for type PMIC-Die
650[    0.686799] pre_t19x_iso_plat_init(): iso emc max clk=1600000KHz
651[    0.686821] pre_t19x_iso_plat_init(): max_iso_bw=11520000KB
652[    0.687267] NET: Registered protocol family 2
653[    0.688264] TCP established hash table entries: 32768 (order: 6, 262144 bytes)
654[    0.688503] TCP bind hash table entries: 32768 (order: 7, 524288 bytes)
655[    0.689010] TCP: Hash tables configured (established 32768 bind 32768)
656[    0.689174] UDP hash table entries: 2048 (order: 4, 65536 bytes)
657[    0.689271] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes)
658[    0.689689] NET: Registered protocol family 1
659[    0.690489] RPC: Registered named UNIX socket transport module.
660[    0.690519] RPC: Registered udp transport module.
661[    0.690537] RPC: Registered tcp transport module.
662[    0.690555] RPC: Registered tcp NFSv4.1 backchannel transport module.
663[    0.691070] Trying to unpack rootfs image as initramfs...
664[    0.922596] Freeing initrd memory: 5356K
665[    0.932663] host1x 50000000.host1x: initialized
666[    0.934504] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
667[    0.937771] audit: initializing netlink subsys (disabled)
668[    0.937886] audit: type=2000 audit(0.787:1): initialized
669[    0.938655] workingset: timestamp_bits=46 max_order=20 bucket_order=0
670[    0.948571] squashfs: version 4.0 (2009/01/31) Phillip Lougher
671[    0.950106] ntfs: driver 2.1.32 [Flags: R/W].
672[    0.950958] 9p: Installing v9fs 9p2000 file system support
673[    0.954217] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 240)
674[    0.954370] io scheduler noop registered
675[    0.954716] io scheduler cfq registered (default)
676[    0.957399] gic 702f9000.agic: GIC IRQ controller registered
677[    0.960425] iommu: Adding device 702ef000.adsp to group 32
678[    0.969840] iommu: Adding device aconnect@702c0000:adsp_audio to group 33
679[    0.970018] tegra-aconnect aconnect@702c0000: Tegra ACONNECT bus registered
680[    0.970675] tegra-xusb-padctl 7009f000.xusb_padctl: TEGRA_FUSE_SKU_CALIB_0 = 0x9a09411
681[    0.970707] tegra-xusb-padctl 7009f000.xusb_padctl: TEGRA_FUSE_USB_CALIB_EXT_0 = 0x4
682[    0.972314] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-usb2.0, lane = usb2-0, function = xusb
683[    0.972452] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-usb2.1, lane = usb2-1, function = xusb
684[    0.972563] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-usb2.2, lane = usb2-2, function = xusb
685[    0.972771] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-pcie.3, lane = pcie-0, function = pcie-x1
686[    0.972885] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-pcie.4, lane = pcie-1, function = pcie-x4
687[    0.972999] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-pcie.5, lane = pcie-2, function = pcie-x4
688[    0.973109] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-pcie.6, lane = pcie-3, function = pcie-x4
689[    0.973217] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-pcie.7, lane = pcie-4, function = pcie-x4
690[    0.973331] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-pcie.8, lane = pcie-5, function = xusb
691[    0.973438] tegra-xusb-padctl 7009f000.xusb_padctl: dev = phy-pcie.9, lane = pcie-6, function = xusb
692[    0.979498] tegra-pwm 7000a000.pwm: PWM clk cannot sleep in ops
693[    0.981233] tegra-dfll-pwm 70110000.pwm: DFLL pwm-rate: 12800000
694[    0.983206] tegra-pcie 1003000.pcie: 4x1, 1x1 configuration
695[    0.984504] tegra-pcie 1003000.pcie: PCIE: Enable power rails
696[    0.984869] tegra-pcie 1003000.pcie: probing port 0, using 4 lanes
697[    0.986064] tegra_camera_platform tegra-camera-platform: tegra_camera_probe:camera_platform_driver probe
698[    0.986308] misc tegra_camera_ctrl: tegra_camera_isomgr_register isp_iso_bw=1500000, vi_iso_bw=1500000, max_bw=1500000
699[    0.986589] Adding domain tsec-pd to PM domain host1x-pd
700[    0.986768] tegra-pcie 1003000.pcie: probing port 1, using 1 lanes
701[    0.990134] tsec 54500000.tsec: initialized
702[    0.991565] tsec 54100000.tsecb: initialized
703[    0.992295] Adding domain nvdec-pd to PM domain host1x-pd
704[    0.995654] nvdec 54480000.nvdec: initialized
705[    0.996697] Adding domain vic03-pd to PM domain host1x-pd
706[    0.996893] Adding domain msenc-pd to PM domain host1x-pd
707[    0.997067] Adding domain nvjpg-pd to PM domain host1x-pd
708[    1.001181] falcon 54340000.vic: initialized
709[    1.002410] falcon 544c0000.nvenc: initialized
710[    1.003773] falcon 54380000.nvjpg: initialized
711[    1.008285] tegra_cec 70015000.tegra_cec: dt=1 start=0x70015000 end=0x70015FFF irq=96
712[    1.008368] tegra_cec 70015000.tegra_cec: Enable clock result: 0.
713[    1.008413] tegradc tegradc.0: disp0 connected to head0->/host1x/sor1
714[    1.008416] tegra_cec 70015000.tegra_cec: tegra_cec_init started
715[    1.008569] display board info: id 0x0, fab 0x0
716[    1.008649] generic_infoframe_type: 0x87
717[    1.008706] tegra_cec 70015000.tegra_cec: cec_add_sysfs ret=0
718[    1.008728] tegra_cec 70015000.tegra_cec: probed
719[    1.008821] tegradc tegradc.0: DT parsed successfully
720[    1.008894] tegradc tegradc.0: Display dc.ffffff800ab40000 registered with id=0
721[    1.016535] tegra-apbdma 60020000.dma: Tegra20 APB DMA driver register 32 channels
722[    1.016876] tegradc tegradc.0: probed
723[    1.017672] Console: switching to colour frame buffer device 80x30
724[    1.017731] tegradc tegradc.0: fb registered
725[    1.019188] tegradc tegradc.1: disp1 connected to head1->/host1x/sor
726[    1.019306] tegradc tegradc.1: No lt-data, using default setting
727[    1.019357] tegradc tegradc.1: No hpd-gpio in DT
728[    1.019396] tegradc tegradc.1: DT parsed successfully
729[    1.019462] tegradc tegradc.1: Display dc.ffffff800acc0000 registered with id=1
730[    1.020948] tegradc tegradc.1: dpd enable lookup fail:-19
731[    1.022847] tegra-adma 702e2000.adma: Tegra210 ADMA driver registered 22 channels
732[    1.023678] tegra-fuse-burn 7000f800.efuse:efuse-burn: Fuse burn driver initialized
733[    1.024022] kfuse 7000fc00.kfuse: initialized
734[    1.527249] Host read timeout at address 545c00c4
735[    1.527373] tegra-pmc-iopower pmc-iopower: Regulator supply iopower-dbg-supply not available
736[    1.528304] tegra-pmc-iopower pmc-iopower: NO_IOPOWER setting 0x0
737[    1.528563] tegradc tegradc.1: probed
738[    1.528949] tegradc tegradc.1: fb registered
739[    1.529574] tegra-dfll-pwm 70110000.pwm: DFLL_PWM regulator is available now
740[    1.529604] vdd-cpu: 708 <--> 1322 mV at 708 mV
741[    1.529987] pwm-regulator pwm_regulators:pwm-regulator@0: PWM regulator registration passed
742[    1.531277] vdd-gpu: applied init 1000000uV constraint
743[    1.531301] vdd-gpu: 708 <--> 1323 mV at 997 mV
744[    1.531685] pwm-regulator pwm_regulators:pwm-regulator@1: PWM regulator registration passed
745[    1.535712] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
746[    1.535842] No Device Node present for smmu client: serial8250 !!
747[    1.535866] platform serial8250: No iommus property found in DT node, got swgids from fixup(101004000)
748[    1.535920] iommu: Adding device serial8250 to group 34
749[    1.538444] console [ttyS0] disabled
750[    1.538578] 70006000.serial: ttyS0 at MMIO 0x70006000 (irq = 63, base_baud = 25500000) is a Tegra
751[    1.544324] tegradc tegradc.1: nominal-pclk:138500000 parent:138498632 div:1.0 pclk:138498632 137115000~150965000
752[    1.546449] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10200000 did not specify bpp
753[    1.550035] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
754[    1.554764] dp lt: state 0 (Reset), pending_lt_evt 1
755[    1.554768] dp lt: switching from state 0 (Reset) to state 0 (Reset)
756[    1.554772] dp lt: state 0 (Reset), pending_lt_evt 0
757[    1.555985] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
758[    1.556134] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
759[    1.556138] dp lt: state 2 (clock recovery), pending_lt_evt 0
760[    1.556380] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
761[    1.556391] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
762[    1.556400] dp lt: tx_pu: 0x20
763[    1.557086] dp lt: CR not done
764[    1.557315] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
765[    1.557318] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
766[    1.557320] dp lt: CR retry
767[    1.557324] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
768[    1.557328] dp lt: state 2 (clock recovery), pending_lt_evt 0
769[    1.557341] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
770[    1.557351] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
771[    1.557358] dp lt: tx_pu: 0x30
772[    1.558041] dp lt: CR not done
773[    1.558268] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
774[    1.558270] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
775[    1.558272] dp lt: CR retry
776[    1.558275] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
777[    1.558279] dp lt: state 2 (clock recovery), pending_lt_evt 0
778[    1.558292] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
779[    1.558302] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
780[    1.558307] dp lt: tx_pu: 0x30
781[    1.558992] dp lt: CR done
782[    1.558995] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
783[    1.559000] dp lt: state 3 (channel equalization), pending_lt_evt 0
784[    1.560977] dp lt: CE done
785[    1.560981] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
786[    1.561473] hpd: state 7 (Takeover from bootloader), hpd 1, pending_hpd_evt 1
787[    1.561478] hpd: switching from state 7 (Takeover from bootloader) to state 1 (Check Plug)
788[    1.666138] hpd: state 1 (Check Plug), hpd 1, pending_hpd_evt 0
789[    1.666144] hpd: switching from state 1 (Check Plug) to state 2 (Check EDID)
790[    1.671210] hpd: state 2 (Check EDID), hpd 1, pending_hpd_evt 0
791[    1.681293] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10200000 did not specify bpp
792[    1.704848] tegradc tegradc.1: nominal-pclk:138504000 parent:138498632 div:1.0 pclk:138498632 137118960~150969360
793[    2.037144] tegra_cec 70015000.tegra_cec: Can't find physical addresse.
794[    2.037151] tegra_cec 70015000.tegra_cec: tegra_cec_init Done.
795[    2.238602] tegra-pcie 1003000.pcie: link 0 down, retrying
796[    2.642900] tegra-pcie 1003000.pcie: link 0 down, retrying
797[    3.047197] tegra-pcie 1003000.pcie: link 0 down, retrying
798[    3.049213] tegra-pcie 1003000.pcie: link 0 down, ignoring
799[    3.155260] tegra-pcie 1003000.pcie: PCI host bridge to bus 0000:00
800[    3.155272] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
801[    3.155278] pci_bus 0000:00: root bus resource [mem 0x13000000-0x1fffffff]
802[    3.155284] pci_bus 0000:00: root bus resource [mem 0x20000000-0x3fffffff pref]
803[    3.155291] pci_bus 0000:00: root bus resource [bus 00-ff]
804[    3.155710] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
805[    3.166741] pci 0000:00:02.0: BAR 15: assigned [mem 0x20000000-0x200fffff 64bit pref]
806[    3.166746] pci 0000:00:02.0: BAR 13: assigned [io  0x1000-0x1fff]
807[    3.166756] pci 0000:01:00.0: BAR 4: assigned [mem 0x20000000-0x20003fff 64bit pref]
808[    3.166776] pci 0000:01:00.0: BAR 2: assigned [mem 0x20004000-0x20004fff 64bit pref]
809[    3.166794] pci 0000:01:00.0: BAR 0: assigned [io  0x1000-0x10ff]
810[    3.166805] pci 0000:00:02.0: PCI bridge to [bus 01]
811[    3.166810] pci 0000:00:02.0:   bridge window [io  0x1000-0x1fff]
812[    3.166818] pci 0000:00:02.0:   bridge window [mem 0x20000000-0x200fffff 64bit pref]
813[    3.167210] pcieport 0000:00:02.0: Signaling PME through PCIe PME interrupt
814[    3.167215] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt
815[    4.293339] console [ttyS0] enabled
816[    4.293586] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10200000 did not specify bpp
817[    4.293826] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10200000 did not specify bpp
818[    4.293834] tegradc tegradc.1: blank - powerdown
819[    4.294926] 70006040.serial: ttyTHS1 at MMIO 0x70006040 (irq = 64, base_baud = 0) is a TEGRA_UART
820[    4.295263] serial-tegra 70006200.serial: RX in PIO mode
821[    4.295358] 70006200.serial: ttyTHS2 at MMIO 0x70006200 (irq = 65, base_baud = 0) is a TEGRA_UART
822[    4.296466] [drm] Initialized
823[    4.315287] brd: module loaded
824[    4.320781] loop: module loaded
825[    4.320887] tegra_profiler: version: 1.139, samples/io: 47/27
826[    4.321006] tegra_profiler: auth: init
827[    4.322439] THERMAL EST: found 2 subdevs
828[    4.322447] THERMAL EST num_resources: 0
829[    4.322453] [THERMAL EST subdev 0]
830[    4.322460] [THERMAL EST subdev 1]
831[    4.323004] thermal thermal_zone5: Registering thermal zone thermal_zone5 for type thermal-fan-est
832[    4.323006] THERMAL EST: thz register success.
833[    4.323184] THERMAL EST: end of probe, return err: 0
834[    4.324480] hisi_sas: driver version v1.6
835[    4.330732] libphy: Fixed MDIO Bus: probed
836[    4.330927] dp lt: state 5 (link training pass), pending_lt_evt 1
837[    4.330932] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
838[    4.330937] dp lt: state 0 (Reset), pending_lt_evt 0
839[    4.330949] dp lt: link training force disable
840[    4.330952] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
841[    4.331362] tun: Universal TUN/TAP device driver, 1.6
842[    4.331364] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
843[    4.332446] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
844[    4.332451] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
845[    4.332510] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.4.0-k
846[    4.332513] igb: Copyright (c) 2007-2014 Intel Corporation.
847[    4.332563] igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.4.0-k
848[    4.332566] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
849[    4.332614] Intel(R) 10GbE PCI Express Linux Network Driver - version 4.6.4
850[    4.332617] Copyright(c) 1999 - 2017 Intel Corporation.
851[    4.333555] r8168 0000:01:00.0: enabling device (0000 -> 0003)
852[    4.333593] r8168 Gigabit Ethernet driver 8.045.08-NAPI loaded
853[    4.348553] tegradc tegradc.1: dp: irq event received, ignoring
854[    4.351916] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10200000 did not specify bpp
855[    4.351943] tegradc tegradc.1: unblank
856[    4.355172] r8168 0000:01:00.0 (unnamed net_device) (uninitialized): Invalid ethernet address 00:00:00:00:00:00, trying device tree node
857[    4.355365] r8168 0000:01:00.0 (unnamed net_device) (uninitialized): Found valid ethernet address 00:04:4b:e5:dd:c6 from device tree
858[    4.355984] r8168: This product is covered by one or more of the following patents: US6,570,884, US6,115,776, and US6,327,625.
859[    4.356049] r8168  Copyright (C) 2017  Realtek NIC software team <nicfae@realtek.com>
860[    4.356049]  This program comes with ABSOLUTELY NO WARRANTY; for details, please see <http://www.gnu.org/licenses/>.
861[    4.356049]  This is free software, and you are welcome to redistribute it under certain conditions; see <http://www.gnu.org/licenses/>.
862[    4.356737] PPP generic driver version 2.4.2
863[    4.356959] PPP BSD Compression module registered
864[    4.356963] PPP Deflate Compression module registered
865[    4.357002] PPP MPPE Compression module registered
866[    4.357008] NET: Registered protocol family 24
867[    4.357083] usbcore: registered new interface driver r8152
868[    4.357128] usbcore: registered new interface driver asix
869[    4.357198] usbcore: registered new interface driver ax88179_178a
870[    4.357236] usbcore: registered new interface driver cdc_ether
871[    4.357274] usbcore: registered new interface driver net1080
872[    4.357324] usbcore: registered new interface driver cdc_subset
873[    4.357360] usbcore: registered new interface driver zaurus
874[    4.357413] usbcore: registered new interface driver cdc_ncm
875[    4.357588] VFIO - User Level meta-driver version: 0.3
876[    4.358950] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
877[    4.358976] ehci-pci: EHCI PCI platform driver
878[    4.359020] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
879[    4.359030] ohci-pci: OHCI PCI platform driver
880[    4.359072] ohci-platform: OHCI generic platform driver
881[    4.361714] tegra-xusb 70090000.xusb: USB2 port 0 has OTG_CAP
882[    4.362320] tegra-xusb-padctl 7009f000.xusb_padctl: enabled OTG on UTMI pad 0
883[    4.363473] tegra-xusb 70090000.xusb: extcon 0: ffffffc0f90a7400 id
884[    4.365654] usbcore: registered new interface driver uas
885[    4.365711] usbcore: registered new interface driver usb-storage
886[    4.365836] usbcore: registered new interface driver usbserial
887[    4.366333] tegra-xusb 70090000.xusb: Firmware timestamp: 2019-10-17 15:58:59 UTC, Version: 50.25 release
888[    4.366384] tegra-xusb 70090000.xusb: xHCI Host Controller
889[    4.366409] tegra-xusb 70090000.xusb: new USB bus registered, assigned bus number 1
890[    4.367186] tegra-xusb 70090000.xusb: hcc params 0x0184f525 hci version 0x100 quirks 0x00050010
891[    4.367246] tegra-xusb 70090000.xusb: irq 61, io mem 0x70090000
892[    4.367444] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
893[    4.367450] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
894[    4.367454] usb usb1: Product: xHCI Host Controller
895[    4.367457] usb usb1: Manufacturer: Linux 4.9.140-tegra xhci-hcd
896[    4.367461] usb usb1: SerialNumber: 70090000.xusb
897[    4.368082] hub 1-0:1.0: USB hub found
898[    4.368123] hub 1-0:1.0: 5 ports detected
899[    4.368688] tegra-xusb 70090000.xusb: xHCI Host Controller
900[    4.368698] tegra-xusb 70090000.xusb: new USB bus registered, assigned bus number 2
901[    4.368773] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
902[    4.368871] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
903[    4.368876] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
904[    4.368879] usb usb2: Product: xHCI Host Controller
905[    4.368882] usb usb2: Manufacturer: Linux 4.9.140-tegra xhci-hcd
906[    4.368885] usb usb2: SerialNumber: 70090000.xusb
907[    4.369301] hub 2-0:1.0: USB hub found
908[    4.369328] hub 2-0:1.0: 4 ports detected
909[    4.372533] tegra-xudc-new 700d0000.xudc: device count: 1
910[    4.373792] tegra-xudc-new 700d0000.xudc: USB charger detection disabled
911[    4.373804] tegra-xudc-new 700d0000.xudc: vbus state: 0
912[    4.373836] tegra-xudc-new 700d0000.xudc: entering ELPG
913[    4.374075] tegra-xudc-new 700d0000.xudc: entering ELPG done
914[    4.374789] mousedev: PS/2 mouse device common for all mice
915[    4.374892] usbcore: registered new interface driver xpad
916[    4.385684] tegradc tegradc.1: nominal-pclk:138500000 parent:138498632 div:1.0 pclk:138498632 137115000~150965000
917[    4.387118] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10200000 did not specify bpp
918[    4.390758] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
919[    4.395438] dp lt: state 4 (link training fail/disable), pending_lt_evt 1
920[    4.395442] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
921[    4.395446] dp lt: state 0 (Reset), pending_lt_evt 0
922[    4.396653] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
923[    4.396799] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
924[    4.396804] dp lt: state 2 (clock recovery), pending_lt_evt 0
925[    4.397044] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
926[    4.397053] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
927[    4.397062] dp lt: tx_pu: 0x20
928[    4.397748] dp lt: CR not done
929[    4.397977] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
930[    4.397980] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
931[    4.397982] dp lt: CR retry
932[    4.397986] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
933[    4.397990] dp lt: state 2 (clock recovery), pending_lt_evt 0
934[    4.398003] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
935[    4.398012] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
936[    4.398018] dp lt: tx_pu: 0x30
937[    4.398703] dp lt: CR not done
938[    4.398930] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
939[    4.398932] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
940[    4.398933] dp lt: CR retry
941[    4.398936] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
942[    4.398940] dp lt: state 2 (clock recovery), pending_lt_evt 0
943[    4.398952] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
944[    4.398961] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
945[    4.398967] dp lt: tx_pu: 0x30
946[    4.399651] dp lt: CR done
947[    4.399654] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
948[    4.399658] dp lt: state 3 (channel equalization), pending_lt_evt 0
949[    4.401614] dp lt: CE done
950[    4.401619] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
951[    4.401975] tegradc tegradc.1: sync windows ret = 250
952[    4.470841] usb usb1: usb_suspend_both: status 0
953[    4.503522] max77686-rtc max77620-rtc: rtc core: registered max77620-rtc as rtc0
954[    4.506003] rtc rtc1: alarm rtc device
955[    4.506021] tegra_rtc 7000e000.rtc: rtc core: registered 7000e000.rtc as rtc1
956[    4.506071] tegra_rtc 7000e000.rtc: Tegra internal Real Time Clock
957[    4.506763] i2c /dev entries driver
958[    4.508766] i2c i2c-6: Added multiplexed i2c bus 7
959[    4.509170] i2c i2c-6: Added multiplexed i2c bus 8
960[    4.509176] i2c-mux-gpio cam_i2cmux: 2 port mux on Tegra I2C adapter adapter
961[    4.509947] imx219 7-0010: tegracam sensor driver:imx219_v2.0.6
962[    4.533283] tegra-vii2c 546c0000.i2c: no acknowledge from address 0x10
963[    4.533360] imx219 7-0010: imx219_board_setup: error during i2c read probe (-121)
964[    4.533399] imx219 7-0010: board setup failed
965[    4.533503] imx219: probe of 7-0010 failed with error -121
966[    4.534034] imx219 8-0010: tegracam sensor driver:imx219_v2.0.6
967[    4.557301] tegra-vii2c 546c0000.i2c: no acknowledge from address 0x10
968[    4.557371] imx219 8-0010: imx219_board_setup: error during i2c read probe (-121)
969[    4.557402] imx219 8-0010: board setup failed
970[    4.557465] imx219: probe of 8-0010 failed with error -121
971[    4.558471] max77620-power max77620-power: Event recorder REG_NVERC : 0x0
972[    4.561342] tegra_soctherm 700e2000.soctherm: pllx_offset tz:0 max:14, min:2
973[    4.561347] tegra_soctherm 700e2000.soctherm: pllx_offset tz:2 max:8, min:4
974[    4.561807] tegra_soctherm 700e2000.soctherm: soctherm: trip temperature -2147483647 forced to -127000
975[    4.561823] tegra_soctherm 700e2000.soctherm: thermtrip: will shut down when cpu reaches 102500 mC
976[    4.561833] tegra_soctherm 700e2000.soctherm: throttrip: will throttle when cpu reaches 100500 mC
977[    4.562000] tegra_soctherm 700e2000.soctherm: soctherm: trip temperature -2147483647 forced to -127000
978[    4.562011] tegra_soctherm 700e2000.soctherm: thermtrip: will shut down when gpu reaches 103000 mC
979[    4.562018] tegra_soctherm 700e2000.soctherm: throttrip: will throttle when gpu reaches 101000 mC
980[    4.562164] tegra_soctherm 700e2000.soctherm: soctherm: trip temperature -2147483647 forced to -127000
981[    4.562174] tegra_soctherm 700e2000.soctherm: thermtrip: will shut down when pll reaches 127000 mC
982[    4.562178] tegra_soctherm 700e2000.soctherm: throttrip: pll: missing hot temperature
983[    4.562350] tegra_soctherm 700e2000.soctherm: failed to register sensor: -19
984[    4.563246] tegra_aotag tegra-aotag: Registering sensor 0
985[    4.563300] tegra_aotag tegra-aotag: Invalid temp readout
986[    4.563328] tegra_aotag tegra-aotag: Invalid temp readout
987[    4.563344] tegra_aotag tegra-aotag: Bound to TZ : ID 0
988[    4.563353] tegra_aotag tegra-aotag: Probe done [SUCCESS]:0
989[    4.564414] tegra_soctherm 700e2000.soctherm: soctherm: trip temperature -2147483647 forced to -127000
990[    4.564434] tegra_dfll_action dfll-cdev-cap: Tegra DFLL 'cap cooling device' registered
991[    4.564672] tegra_aotag tegra-aotag: Invalid temp readout
992[    4.564703] tegra_dfll_action dfll-cdev-floor: Tegra DFLL 'floor cooling device' registered
993[    4.565224] parse_throttle_dt_data: Num cap clks = 6
994[    4.565229] parse_throttle_dt_data: clk=cclk_g type=2
995[    4.565244] parse_throttle_dt_data: clk=gpu type=4
996[    4.565266] parse_throttle_dt_data: clk=cap.throttle.c2bus type=0
997[    4.565285] parse_throttle_dt_data: clk=cap.throttle.c3bus type=0
998[    4.565306] parse_throttle_dt_data: clk=cap.throttle.sclk type=0
999[    4.565309] parse_throttle_dt_data: clk=emc type=3
1000[    4.565794] tegra_soctherm 700e2000.soctherm: soctherm: trip temperature -2147483647 forced to -127000
1001[    4.565945] tegra_soctherm 700e2000.soctherm: soctherm: trip temperature -2147483647 forced to -127000
1002[    4.566121] tegra_throttle_probe: probe successful. #cdevs=4
1003[    4.567023] FAN dev name: pwm-fan
1004[    4.567113] FAN:gpio request success.
1005[    4.567184] pwm_fan_driver pwm-fan: cap state:7, cap pwm:255
1006[    4.567497] pwm_fan_driver pwm-fan: got pwm for fan. polarity is normal
1007[    4.567676] pwm_fan_driver pwm-fan: fan tach request irq success
1008[    4.567686] pwm_fan_driver pwm-fan: tach period: 1000
1009[    4.567796] pwm_fan_driver pwm-fan: index 0: pwm=0, rpm=0, rru=40, rrd=40, state:2
1010[    4.567800] pwm_fan_driver pwm-fan: index 1: pwm=80, rpm=1000, rru=2, rrd=2, state:2
1011[    4.567805] pwm_fan_driver pwm-fan: index 2: pwm=120, rpm=2000, rru=1, rrd=1, state:2
1012[    4.567808] pwm_fan_driver pwm-fan: index 3: pwm=160, rpm=3000, rru=1, rrd=1, state:2
1013[    4.567813] pwm_fan_driver pwm-fan: index 4: pwm=255, rpm=4000, rru=1, rrd=1, state:3
1014[    4.567817] pwm_fan_driver pwm-fan: index 5: pwm=255, rpm=5000, rru=1, rrd=1, state:3
1015[    4.567821] pwm_fan_driver pwm-fan: index 6: pwm=255, rpm=6000, rru=1, rrd=1, state:3
1016[    4.567824] pwm_fan_driver pwm-fan: index 7: pwm=255, rpm=7000, rru=1, rrd=1, state:4
1017[    4.567829] pwm_fan_driver pwm-fan: index 8: pwm=255, rpm=10000, rru=1, rrd=1, state:4
1018[    4.567833] pwm_fan_driver pwm-fan: index 9: pwm=255, rpm=11000, rru=1, rrd=1, state:4
1019[    4.568592] tegra-wdt 60005100.watchdog: Tegra WDT enabled on probe. Timeout = 120 seconds.
1020[    4.568940] tegra-wdt 60005100.watchdog: initialized (timeout = 120 sec, nowayout = 1)
1021[    4.570013] device-mapper: uevent: version 1.0.3
1022[    4.570493] device-mapper: ioctl: 4.35.0-ioctl (2016-06-23) initialised: dm-devel@redhat.com
1023[    4.576071] tegra210-cpufreq cpufreq: probe()...completed
1024[    4.576810] sdhci: Secure Digital Host Controller Interface driver
1025[    4.576811] sdhci: Copyright(c) Pierre Ossman
1026[    4.576813] sdhci-pltfm: SDHCI platform and OF driver helper
1027[    4.577172] sdhci-tegra sdhci-tegra.3: Client registration for eMC Successful
1028[    4.584192] tegra-se 70012000.se: tegra_se_probe: complete
1029[    4.584741] hidraw: raw HID events driver (C) Jiri Kosina
1030[    4.586008] usbcore: registered new interface driver usbhid
1031[    4.586009] usbhid: USB HID core driver
1032[    4.588146] tegra21x_actmon 6000c800.actmon: in actmon_register()...
1033[    4.588312] tegra21x_actmon 6000c800.actmon: initialization Completed for the device mc_all
1034[    4.590114] nvpmodel: initialized successfully
1035[    4.591177] usbcore: registered new interface driver snd-usb-audio
1036[    4.591231] No Device Node present for smmu client: snd-soc-dummy !!
1037[    4.591235] platform snd-soc-dummy: No iommus property found in DT node, got swgids from fixup(101004000)
1038[    4.591252] iommu: Adding device snd-soc-dummy to group 35
1039[    4.608150] input: tegra-hda HDMI/DP,pcm=3 as /devices/70030000.hda/sound/card0/input0
1040[    4.609709] OPE platform probe
1041[    4.609794] OPE platform probe successful
1042[    4.610118] OPE platform probe
1043[    4.610200] OPE platform probe successful
1044[    4.622755] mmc0: SDHCI controller on sdhci-tegra.3 [sdhci-tegra.3] using ADMA 64-bit with 64 bit addr
1045[    4.640986] tegra-asoc: sound: ADMAIF1 <-> ADMAIF1 mapping ok
1046[    4.641112] tegra-asoc: sound: ADMAIF2 <-> ADMAIF2 mapping ok
1047[    4.641235] tegra-asoc: sound: ADMAIF3 <-> ADMAIF3 mapping ok
1048[    4.641361] tegra-asoc: sound: ADMAIF4 <-> ADMAIF4 mapping ok
1049[    4.641479] tegra-asoc: sound: ADMAIF5 <-> ADMAIF5 mapping ok
1050[    4.641599] tegra-asoc: sound: ADMAIF6 <-> ADMAIF6 mapping ok
1051[    4.641717] tegra-asoc: sound: ADMAIF7 <-> ADMAIF7 mapping ok
1052[    4.641839] tegra-asoc: sound: ADMAIF8 <-> ADMAIF8 mapping ok
1053[    4.641956] tegra-asoc: sound: ADMAIF9 <-> ADMAIF9 mapping ok
1054[    4.642089] tegra-asoc: sound: ADMAIF10 <-> ADMAIF10 mapping ok
1055[    4.653782] u32 classifier
1056[    4.653783]     Actions configured
1057[    4.653852] Initializing XFRM netlink socket
1058[    4.654574] NET: Registered protocol family 10
1059[    4.655301] NET: Registered protocol family 17
1060[    4.655311] NET: Registered protocol family 15
1061[    4.655382] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
1062[    4.655427] Bluetooth: RFCOMM socket layer initialized
1063[    4.655436] Bluetooth: RFCOMM ver 1.11
1064[    4.655440] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
1065[    4.655444] Bluetooth: HIDP socket layer initialized
1066[    4.655461] 9pnet: Installing 9P2000 support
1067[    4.655494] Key type dns_resolver registered
1068[    4.666313] Registered cp15_barrier emulation handler
1069[    4.666372] Registered setend emulation handler
1070[    4.667634] registered taskstats version 1
1071[    4.668235] Adding domain ve2-pd to PM domain host1x-pd
1072[    4.668472] Adding domain ve-pd to PM domain host1x-pd
1073[    4.670689] isp 54600000.isp: initialized
1074[    4.671614] isp 54680000.isp: initialized
1075[    4.681925] last reset is due to pmic watchdog timeout
1076[    4.681927] KERNEL: PMC reset status reg: 0x5
1077[    4.682003] BL: PMC reset status reg: 0x0
1078[    4.682004] BL: PMIC poweroff Event Recorder: 0x47
1079[    4.683540] clk_cbus_recalc_rate: no gbus parent
1080[    4.683543] clk_cbus_round_rate: no gbus parent
1081[    4.683545] clk_cbus_round_rate: no gbus parent
1082[    4.683552] clk_cbus_recalc_rate: no gbus parent
1083[    4.683678] clk_cbus_recalc_rate: no gbus parent
1084[    4.683680] clk_cbus_round_rate: no gbus parent
1085[    4.683682] clk_cbus_round_rate: no gbus parent
1086[    4.683685] clk_cbus_recalc_rate: no gbus parent
1087[    4.684372] tegra_dvfs: GPU-cap: registered
1088[    4.684425] tegra dvfs: vdd-cpu: nominal 1168mV, offset 708000uV, step 19200uV, scaling enabled
1089[    4.684427] tegra dvfs: vdd-core: nominal 1075mV, offset 600000uV, step 12500uV, scaling enabled
1090[    4.684429] tegra dvfs: vdd-gpu: nominal 1038mV, offset 708000uV, step 10000uV, scaling enabled
1091[    4.685845] tegra_dvfs: vdd-gpu-vts: registered
1092[    4.686513] tegra_core_action core_dvfs_cdev_floor: Tegra CORE DVFS 'floor cooling device' registered
1093[    4.687121] tegra_core_action core_dvfs_cdev_cap: Tegra CORE DVFS 'cap cooling device' registered
1094[    4.687707] input: gpio-keys as /devices/gpio-keys/input/input1
1095[    4.687743] mmc0: new HS400 Enhanced strobe MMC card at address 0001
1096[    4.692203] mmcblk0: mmc0:0001 DG4016 14.7 GiB
1097[    4.696338] mmcblk0boot0: mmc0:0001 DG4016 partition 1 4.00 MiB
1098[    4.700524] mmcblk0boot1: mmc0:0001 DG4016 partition 2 4.00 MiB
1099[    4.704711] mmcblk0rpmb: mmc0:0001 DG4016 partition 3 4.00 MiB
1100[    4.705749]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17
1101[    4.720402] tegra_rtc 7000e000.rtc: setting system clock to 2000-01-01 01:00:15 UTC (946688415)
1102[    4.721409] vi 54080000.vi: vi_probe: ++
1103[    4.724282] vi 54080000.vi: initialized
1104[    4.726306] vi 54080000.vi: subdev nvcsi--2 bound
1105[    4.726405] vi 54080000.vi: subdev nvcsi--1 bound
1106[    4.726650] mmcblk mmc0:0001: Card claimed for testing.
1107[    4.728011] Disable partitions left on by BL
1108[    4.728013]   disb
1109[    4.728061] bwmgr: missing cdev-type property
1110[    4.728155] tegra_soctherm 700e2000.soctherm: soctherm: trip temperature -2147483647 forced to -127000
1111[    4.728161] DRAM derating cdev registered.
1112[    4.729177] vdd-fan: disabling
1113[    4.729179] vdd-usb-vbus: disabling
1114[    4.729181] vdd-usb-vbus2: disabling
1115[    4.729189] vddio-sdmmc-ap: disabling
1116[    4.729270] vddio-sdmmc3-ap: disabling
1117[    4.729334] vdd-3v3-sd: disabling
1118[    4.729338] vdd-usb-hub-en: disabling
1119[    4.729415] ALSA device list:
1120[    4.729417]   #0: tegra-hda at 0x70038000 irq 82
1121[    4.729419]   #1: tegra-snd-t210ref-mobile-rt565x
1122[    6.220563] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10200000 did not specify bpp
1123[    6.220791] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10200000 did not specify bpp
1124[    6.220795] tegradc tegradc.1: blank - powerdown
1125[    6.270462] dp lt: state 5 (link training pass), pending_lt_evt 1
1126[    6.270465] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
1127[    6.270467] dp lt: state 0 (Reset), pending_lt_evt 0
1128[    6.270470] dp lt: link training force disable
1129[    6.270472] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
1130[    6.288116] tegradc tegradc.1: dp: irq event received, ignoring
1131[    6.291553] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10200000 did not specify bpp
1132[    6.291563] tegradc tegradc.1: unblank
1133[    6.322378] tegradc tegradc.1: nominal-pclk:138500000 parent:138498632 div:1.0 pclk:138498632 137115000~150965000
1134[    6.323749] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10200000 did not specify bpp
1135[    6.327436] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1136[    6.332056] dp lt: state 4 (link training fail/disable), pending_lt_evt 1
1137[    6.332058] dp lt: switching from state 4 (link training fail/disable) to state 1 (fast link training)
1138[    6.332060] dp lt: state 1 (fast link training), pending_lt_evt 0
1139[    6.332069] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1140[    6.332076] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1141[    6.332080] dp lt: tx_pu: 0x30
1142[    6.335741] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1143[    6.335767] dp lt: fast link training fail
1144[    6.335770] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1145[    6.335774] dp lt: state 0 (Reset), pending_lt_evt 0
1146[    6.336961] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1147[    6.337103] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1148[    6.337106] dp lt: state 2 (clock recovery), pending_lt_evt 0
1149[    6.337339] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1150[    6.337347] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1151[    6.337353] dp lt: tx_pu: 0x20
1152[    6.337936] tegradc tegradc.1: dp: irq event received
1153[    6.338245] dp lt: CR not done
1154[    6.338470] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1155[    6.338472] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1156[    6.338474] dp lt: CR retry
1157[    6.338476] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1158[    6.338479] dp lt: state 2 (clock recovery), pending_lt_evt 0
1159[    6.338490] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1160[    6.338498] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1161[    6.338502] dp lt: tx_pu: 0x30
1162[    6.339182] dp lt: CR not done
1163[    6.339408] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1164[    6.339410] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1165[    6.339412] dp lt: CR retry
1166[    6.339414] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1167[    6.339418] dp lt: state 2 (clock recovery), pending_lt_evt 0
1168[    6.339429] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1169[    6.339437] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1170[    6.339442] dp lt: tx_pu: 0x30
1171[    6.340122] dp lt: CR done
1172[    6.340125] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1173[    6.340128] dp lt: state 3 (channel equalization), pending_lt_evt 0
1174[    6.342050] dp lt: CE done
1175[    6.342052] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1176[    6.342281] tegradc tegradc.1: sync windows ret = 250
1177[    6.676300] dp lt: state 5 (link training pass), pending_lt_evt 1
1178[    6.676302] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1179[    6.676305] dp lt: state 1 (fast link training), pending_lt_evt 0
1180[    6.697161] extcon-disp-state extcon:disp-state: cable 44 state 1
1181[    6.700226] Freeing unused kernel memory: 8576K
1182[    6.709300] Extcon DP: HPD enabled
1183[    6.709320] hpd: Display connected, hpd_switch 1
1184[    6.709322] hpd: switching from state 2 (Check EDID) to state 4 (Enabled)
1185[    6.725910] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1186[    6.732720] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1187[    6.739523] dp lt: tx_pu: 0x30
1188[    6.742670] Root device found: mmcblk0p1
1189[    6.743799] tegradc tegradc.1: dp: irq event received
1190[    6.746265] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1191[    6.746289] dp lt: fast link training fail
1192[    6.746291] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1193[    6.746297] dp lt: state 0 (Reset), pending_lt_evt 0
1194[    6.747492] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1195[    6.747629] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1196[    6.747632] dp lt: state 2 (clock recovery), pending_lt_evt 0
1197[    6.747863] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1198[    6.747871] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1199[    6.747875] dp lt: tx_pu: 0x20
1200[    6.748462] tegradc tegradc.1: dp: irq event received
1201[    6.748761] dp lt: CR not done
1202[    6.748984] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1203[    6.748986] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1204[    6.748987] dp lt: CR retry
1205[    6.748989] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1206[    6.748992] dp lt: state 2 (clock recovery), pending_lt_evt 0
1207[    6.749001] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1208[    6.749009] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1209[    6.749013] dp lt: tx_pu: 0x30
1210[    6.749688] dp lt: CR not done
1211[    6.749911] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1212[    6.749912] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1213[    6.749913] dp lt: CR retry
1214[    6.749915] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1215[    6.749918] dp lt: state 2 (clock recovery), pending_lt_evt 0
1216[    6.749927] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1217[    6.749935] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1218[    6.749939] dp lt: tx_pu: 0x30
1219[    6.750617] dp lt: CR done
1220[    6.750619] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1221[    6.750622] dp lt: state 3 (channel equalization), pending_lt_evt 0
1222[    6.752542] dp lt: CE done
1223[    6.752545] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1224[    6.826679] dp lt: state 5 (link training pass), pending_lt_evt 1
1225[    6.826681] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1226[    6.826683] dp lt: state 1 (fast link training), pending_lt_evt 0
1227[    6.869435] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1228[    6.869443] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1229[    6.869448] dp lt: tx_pu: 0x30
1230[    6.870651] tegradc tegradc.1: dp: irq event received
1231[    6.873114] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1232[    6.873137] dp lt: fast link training fail
1233[    6.873139] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1234[    6.873142] dp lt: state 0 (Reset), pending_lt_evt 0
1235[    6.874326] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1236[    6.874462] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1237[    6.874465] dp lt: state 2 (clock recovery), pending_lt_evt 0
1238[    6.874697] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1239[    6.874705] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1240[    6.874709] dp lt: tx_pu: 0x20
1241[    6.875292] tegradc tegradc.1: dp: irq event received
1242[    6.875594] dp lt: CR not done
1243[    6.875817] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1244[    6.875818] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1245[    6.875819] dp lt: CR retry
1246[    6.875821] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1247[    6.875824] dp lt: state 2 (clock recovery), pending_lt_evt 0
1248[    6.875834] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1249[    6.875841] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1250[    6.875845] dp lt: tx_pu: 0x30
1251[    6.876520] dp lt: CR not done
1252[    6.876743] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1253[    6.876744] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1254[    6.876745] dp lt: CR retry
1255[    6.876747] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1256[    6.876750] dp lt: state 2 (clock recovery), pending_lt_evt 0
1257[    6.876760] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1258[    6.876767] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1259[    6.876771] dp lt: tx_pu: 0x30
1260[    6.877447] dp lt: CR done
1261[    6.877449] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1262[    6.877451] dp lt: state 3 (channel equalization), pending_lt_evt 0
1263[    6.879367] dp lt: CE done
1264[    6.879370] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1265[    6.950631] dp lt: state 5 (link training pass), pending_lt_evt 1
1266[    6.950632] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1267[    6.950635] dp lt: state 1 (fast link training), pending_lt_evt 0
1268[    6.996263] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1269[    6.996271] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1270[    6.996276] dp lt: tx_pu: 0x30
1271[    6.997476] tegradc tegradc.1: dp: irq event received
1272[    6.999940] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1273[    6.999962] dp lt: fast link training fail
1274[    6.999964] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1275[    6.999967] dp lt: state 0 (Reset), pending_lt_evt 0
1276[    7.001150] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1277[    7.001287] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1278[    7.001290] dp lt: state 2 (clock recovery), pending_lt_evt 0
1279[    7.001521] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1280[    7.001528] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1281[    7.001532] dp lt: tx_pu: 0x20
1282[    7.002118] tegradc tegradc.1: dp: irq event received
1283[    7.002417] dp lt: CR not done
1284[    7.002642] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1285[    7.002643] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1286[    7.002644] dp lt: CR retry
1287[    7.002646] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1288[    7.002649] dp lt: state 2 (clock recovery), pending_lt_evt 0
1289[    7.002660] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1290[    7.002668] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1291[    7.002672] dp lt: tx_pu: 0x30
1292[    7.003349] dp lt: CR not done
1293[    7.003571] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1294[    7.003573] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1295[    7.003573] dp lt: CR retry
1296[    7.003575] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1297[    7.003578] dp lt: state 2 (clock recovery), pending_lt_evt 0
1298[    7.003587] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1299[    7.003594] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1300[    7.003598] dp lt: tx_pu: 0x30
1301[    7.004273] dp lt: CR done
1302[    7.004275] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1303[    7.004278] dp lt: state 3 (channel equalization), pending_lt_evt 0
1304[    7.006193] dp lt: CE done
1305[    7.006196] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1306[    7.074628] dp lt: state 5 (link training pass), pending_lt_evt 1
1307[    7.074630] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1308[    7.074633] dp lt: state 1 (fast link training), pending_lt_evt 0
1309[    7.123082] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1310[    7.123090] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1311[    7.123095] dp lt: tx_pu: 0x30
1312[    7.124293] tegradc tegradc.1: dp: irq event received
1313[    7.126752] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1314[    7.126775] dp lt: fast link training fail
1315[    7.126777] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1316[    7.126780] dp lt: state 0 (Reset), pending_lt_evt 0
1317[    7.127964] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1318[    7.128100] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1319[    7.128103] dp lt: state 2 (clock recovery), pending_lt_evt 0
1320[    7.128333] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1321[    7.128340] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1322[    7.128344] dp lt: tx_pu: 0x20
1323[    7.128931] tegradc tegradc.1: dp: irq event received
1324[    7.129230] dp lt: CR not done
1325[    7.129452] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1326[    7.129454] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1327[    7.129455] dp lt: CR retry
1328[    7.129457] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1329[    7.129459] dp lt: state 2 (clock recovery), pending_lt_evt 0
1330[    7.129469] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1331[    7.129476] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1332[    7.129480] dp lt: tx_pu: 0x30
1333[    7.130156] dp lt: CR not done
1334[    7.130378] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1335[    7.130380] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1336[    7.130381] dp lt: CR retry
1337[    7.130383] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1338[    7.130385] dp lt: state 2 (clock recovery), pending_lt_evt 0
1339[    7.130395] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1340[    7.130402] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1341[    7.130406] dp lt: tx_pu: 0x30
1342[    7.131084] dp lt: CR done
1343[    7.131086] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1344[    7.131089] dp lt: state 3 (channel equalization), pending_lt_evt 0
1345[    7.133003] dp lt: CE done
1346[    7.133006] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1347[    7.202630] dp lt: state 5 (link training pass), pending_lt_evt 1
1348[    7.202632] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1349[    7.202634] dp lt: state 1 (fast link training), pending_lt_evt 0
1350[    7.249893] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1351[    7.249901] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1352[    7.249906] dp lt: tx_pu: 0x30
1353[    7.251105] tegradc tegradc.1: dp: irq event received
1354[    7.253567] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1355[    7.253590] dp lt: fast link training fail
1356[    7.253592] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1357[    7.253595] dp lt: state 0 (Reset), pending_lt_evt 0
1358[    7.254781] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1359[    7.254918] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1360[    7.254920] dp lt: state 2 (clock recovery), pending_lt_evt 0
1361[    7.255151] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1362[    7.255158] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1363[    7.255162] dp lt: tx_pu: 0x20
1364[    7.255747] tegradc tegradc.1: dp: irq event received
1365[    7.256046] dp lt: CR not done
1366[    7.256269] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1367[    7.256271] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1368[    7.256272] dp lt: CR retry
1369[    7.256273] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1370[    7.256276] dp lt: state 2 (clock recovery), pending_lt_evt 0
1371[    7.256286] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1372[    7.256293] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1373[    7.256297] dp lt: tx_pu: 0x30
1374[    7.256973] dp lt: CR not done
1375[    7.257196] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1376[    7.257197] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1377[    7.257198] dp lt: CR retry
1378[    7.257200] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1379[    7.257202] dp lt: state 2 (clock recovery), pending_lt_evt 0
1380[    7.257212] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1381[    7.257219] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1382[    7.257223] dp lt: tx_pu: 0x30
1383[    7.257899] dp lt: CR done
1384[    7.257901] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1385[    7.257903] dp lt: state 3 (channel equalization), pending_lt_evt 0
1386[    7.259820] dp lt: CE done
1387[    7.259822] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1388[    7.330626] dp lt: state 5 (link training pass), pending_lt_evt 1
1389[    7.330628] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1390[    7.330630] dp lt: state 1 (fast link training), pending_lt_evt 0
1391[    7.376708] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1392[    7.376716] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1393[    7.376720] dp lt: tx_pu: 0x30
1394[    7.377920] tegradc tegradc.1: dp: irq event received
1395[    7.380382] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1396[    7.380404] dp lt: fast link training fail
1397[    7.380406] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1398[    7.380409] dp lt: state 0 (Reset), pending_lt_evt 0
1399[    7.381594] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1400[    7.381731] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1401[    7.381733] dp lt: state 2 (clock recovery), pending_lt_evt 0
1402[    7.381964] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1403[    7.381971] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1404[    7.381975] dp lt: tx_pu: 0x20
1405[    7.382559] tegradc tegradc.1: dp: irq event received
1406[    7.382861] dp lt: CR not done
1407[    7.383084] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1408[    7.383086] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1409[    7.383087] dp lt: CR retry
1410[    7.383089] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1411[    7.383091] dp lt: state 2 (clock recovery), pending_lt_evt 0
1412[    7.383101] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1413[    7.383108] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1414[    7.383112] dp lt: tx_pu: 0x30
1415[    7.383787] dp lt: CR not done
1416[    7.384010] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1417[    7.384011] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1418[    7.384012] dp lt: CR retry
1419[    7.384014] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1420[    7.384017] dp lt: state 2 (clock recovery), pending_lt_evt 0
1421[    7.384026] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1422[    7.384034] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1423[    7.384038] dp lt: tx_pu: 0x30
1424[    7.384713] dp lt: CR done
1425[    7.384715] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1426[    7.384717] dp lt: state 3 (channel equalization), pending_lt_evt 0
1427[    7.386643] dp lt: CE done
1428[    7.386646] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1429[    7.454629] dp lt: state 5 (link training pass), pending_lt_evt 1
1430[    7.454631] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1431[    7.454634] dp lt: state 1 (fast link training), pending_lt_evt 0
1432[    7.498705] random: crng init done
1433[    7.503513] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1434[    7.503521] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1435[    7.503526] dp lt: tx_pu: 0x30
1436[    7.504727] tegradc tegradc.1: dp: irq event received
1437[    7.507188] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1438[    7.507211] dp lt: fast link training fail
1439[    7.507213] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1440[    7.507216] dp lt: state 0 (Reset), pending_lt_evt 0
1441[    7.508401] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1442[    7.508538] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1443[    7.508541] dp lt: state 2 (clock recovery), pending_lt_evt 0
1444[    7.508771] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1445[    7.508778] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1446[    7.508782] dp lt: tx_pu: 0x20
1447[    7.509367] tegradc tegradc.1: dp: irq event received
1448[    7.509667] dp lt: CR not done
1449[    7.509889] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1450[    7.509891] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1451[    7.509892] dp lt: CR retry
1452[    7.509894] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1453[    7.509896] dp lt: state 2 (clock recovery), pending_lt_evt 0
1454[    7.509906] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1455[    7.509913] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1456[    7.509917] dp lt: tx_pu: 0x30
1457[    7.510592] dp lt: CR not done
1458[    7.510817] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1459[    7.510819] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1460[    7.510820] dp lt: CR retry
1461[    7.510821] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1462[    7.510824] dp lt: state 2 (clock recovery), pending_lt_evt 0
1463[    7.510834] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1464[    7.510841] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1465[    7.510845] dp lt: tx_pu: 0x30
1466[    7.511521] dp lt: CR done
1467[    7.511523] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1468[    7.511525] dp lt: state 3 (channel equalization), pending_lt_evt 0
1469[    7.513438] dp lt: CE done
1470[    7.513440] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1471[    7.582628] dp lt: state 5 (link training pass), pending_lt_evt 1
1472[    7.582630] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1473[    7.582632] dp lt: state 1 (fast link training), pending_lt_evt 0
1474[    7.630320] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1475[    7.630329] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1476[    7.630334] dp lt: tx_pu: 0x30
1477[    7.631535] tegradc tegradc.1: dp: irq event received
1478[    7.633995] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1479[    7.634017] dp lt: fast link training fail
1480[    7.634019] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1481[    7.634022] dp lt: state 0 (Reset), pending_lt_evt 0
1482[    7.635207] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1483[    7.635344] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1484[    7.635347] dp lt: state 2 (clock recovery), pending_lt_evt 0
1485[    7.635578] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1486[    7.635586] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1487[    7.635590] dp lt: tx_pu: 0x20
1488[    7.636174] tegradc tegradc.1: dp: irq event received
1489[    7.636474] dp lt: CR not done
1490[    7.636697] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1491[    7.636699] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1492[    7.636700] dp lt: CR retry
1493[    7.636702] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1494[    7.636704] dp lt: state 2 (clock recovery), pending_lt_evt 0
1495[    7.636714] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1496[    7.636722] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1497[    7.636726] dp lt: tx_pu: 0x30
1498[    7.637401] dp lt: CR not done
1499[    7.637623] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1500[    7.637625] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1501[    7.637626] dp lt: CR retry
1502[    7.637628] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1503[    7.637630] dp lt: state 2 (clock recovery), pending_lt_evt 0
1504[    7.637640] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1505[    7.637647] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1506[    7.637651] dp lt: tx_pu: 0x30
1507[    7.638326] dp lt: CR done
1508[    7.638328] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1509[    7.638330] dp lt: state 3 (channel equalization), pending_lt_evt 0
1510[    7.640247] dp lt: CE done
1511[    7.640249] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1512[    7.710631] dp lt: state 5 (link training pass), pending_lt_evt 1
1513[    7.710633] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1514[    7.710635] dp lt: state 1 (fast link training), pending_lt_evt 0
1515[    7.757130] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1516[    7.757137] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1517[    7.757142] dp lt: tx_pu: 0x30
1518[    7.758386] tegradc tegradc.1: dp: irq event received
1519[    7.760795] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1520[    7.760817] dp lt: fast link training fail
1521[    7.760819] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1522[    7.760822] dp lt: state 0 (Reset), pending_lt_evt 0
1523[    7.762006] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1524[    7.762142] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1525[    7.762145] dp lt: state 2 (clock recovery), pending_lt_evt 0
1526[    7.762375] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1527[    7.762382] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1528[    7.762386] dp lt: tx_pu: 0x20
1529[    7.762973] tegradc tegradc.1: dp: irq event received
1530[    7.763272] dp lt: CR not done
1531[    7.763495] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1532[    7.763497] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1533[    7.763498] dp lt: CR retry
1534[    7.763499] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1535[    7.763502] dp lt: state 2 (clock recovery), pending_lt_evt 0
1536[    7.763512] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1537[    7.763520] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1538[    7.763524] dp lt: tx_pu: 0x30
1539[    7.764199] dp lt: CR not done
1540[    7.764422] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1541[    7.764424] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1542[    7.764425] dp lt: CR retry
1543[    7.764427] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1544[    7.764429] dp lt: state 2 (clock recovery), pending_lt_evt 0
1545[    7.764439] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1546[    7.764446] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1547[    7.764450] dp lt: tx_pu: 0x30
1548[    7.765125] dp lt: CR done
1549[    7.765127] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1550[    7.765129] dp lt: state 3 (channel equalization), pending_lt_evt 0
1551[    7.767045] dp lt: CE done
1552[    7.767047] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1553[    7.838630] dp lt: state 5 (link training pass), pending_lt_evt 1
1554[    7.838632] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1555[    7.838634] dp lt: state 1 (fast link training), pending_lt_evt 0
1556[    7.883936] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1557[    7.883944] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1558[    7.883948] dp lt: tx_pu: 0x30
1559[    7.885191] tegradc tegradc.1: dp: irq event received
1560[    7.887601] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1561[    7.887623] dp lt: fast link training fail
1562[    7.887625] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1563[    7.887628] dp lt: state 0 (Reset), pending_lt_evt 0
1564[    7.888812] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1565[    7.888949] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1566[    7.888952] dp lt: state 2 (clock recovery), pending_lt_evt 0
1567[    7.889183] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1568[    7.889190] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1569[    7.889195] dp lt: tx_pu: 0x20
1570[    7.889779] tegradc tegradc.1: dp: irq event received
1571[    7.890078] dp lt: CR not done
1572[    7.890302] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1573[    7.890303] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1574[    7.890304] dp lt: CR retry
1575[    7.890306] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1576[    7.890309] dp lt: state 2 (clock recovery), pending_lt_evt 0
1577[    7.890319] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1578[    7.890326] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1579[    7.890332] dp lt: tx_pu: 0x30
1580[    7.891010] dp lt: CR not done
1581[    7.891233] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1582[    7.891235] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1583[    7.891236] dp lt: CR retry
1584[    7.891238] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1585[    7.891240] dp lt: state 2 (clock recovery), pending_lt_evt 0
1586[    7.891250] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1587[    7.891258] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1588[    7.891262] dp lt: tx_pu: 0x30
1589[    7.891937] dp lt: CR done
1590[    7.891939] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1591[    7.891942] dp lt: state 3 (channel equalization), pending_lt_evt 0
1592[    7.893855] dp lt: CE done
1593[    7.893857] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1594[    7.962634] dp lt: state 5 (link training pass), pending_lt_evt 1
1595[    7.962636] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1596[    7.962638] dp lt: state 1 (fast link training), pending_lt_evt 0
1597[    8.010747] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1598[    8.010754] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1599[    8.010760] dp lt: tx_pu: 0x30
1600[    8.011958] tegradc tegradc.1: dp: irq event received
1601[    8.014419] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1602[    8.014441] dp lt: fast link training fail
1603[    8.014443] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1604[    8.014446] dp lt: state 0 (Reset), pending_lt_evt 0
1605[    8.015632] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1606[    8.015769] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1607[    8.015771] dp lt: state 2 (clock recovery), pending_lt_evt 0
1608[    8.016002] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1609[    8.016009] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1610[    8.016013] dp lt: tx_pu: 0x20
1611[    8.016597] tegradc tegradc.1: dp: irq event received
1612[    8.016898] dp lt: CR not done
1613[    8.017121] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1614[    8.017122] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1615[    8.017123] dp lt: CR retry
1616[    8.017125] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1617[    8.017128] dp lt: state 2 (clock recovery), pending_lt_evt 0
1618[    8.017137] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1619[    8.017145] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1620[    8.017149] dp lt: tx_pu: 0x30
1621[    8.017824] dp lt: CR not done
1622[    8.018046] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1623[    8.018048] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1624[    8.018049] dp lt: CR retry
1625[    8.018050] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1626[    8.018053] dp lt: state 2 (clock recovery), pending_lt_evt 0
1627[    8.018063] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1628[    8.018070] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1629[    8.018074] dp lt: tx_pu: 0x30
1630[    8.018751] dp lt: CR done
1631[    8.018753] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1632[    8.018756] dp lt: state 3 (channel equalization), pending_lt_evt 0
1633[    8.020669] dp lt: CE done
1634[    8.020672] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1635[    8.090630] dp lt: state 5 (link training pass), pending_lt_evt 1
1636[    8.090632] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1637[    8.090634] dp lt: state 1 (fast link training), pending_lt_evt 0
1638[    8.137552] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1639[    8.137560] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1640[    8.137565] dp lt: tx_pu: 0x30
1641[    8.138765] tegradc tegradc.1: dp: irq event received
1642[    8.141228] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1643[    8.141250] dp lt: fast link training fail
1644[    8.141252] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1645[    8.141255] dp lt: state 0 (Reset), pending_lt_evt 0
1646[    8.142440] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1647[    8.142577] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1648[    8.142580] dp lt: state 2 (clock recovery), pending_lt_evt 0
1649[    8.142813] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1650[    8.142820] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1651[    8.142825] dp lt: tx_pu: 0x20
1652[    8.143409] tegradc tegradc.1: dp: irq event received
1653[    8.143710] dp lt: CR not done
1654[    8.143933] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1655[    8.143935] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1656[    8.143935] dp lt: CR retry
1657[    8.143937] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1658[    8.143940] dp lt: state 2 (clock recovery), pending_lt_evt 0
1659[    8.143950] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1660[    8.143957] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1661[    8.143961] dp lt: tx_pu: 0x30
1662[    8.144636] dp lt: CR not done
1663[    8.144859] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1664[    8.144861] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1665[    8.144862] dp lt: CR retry
1666[    8.144863] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1667[    8.144866] dp lt: state 2 (clock recovery), pending_lt_evt 0
1668[    8.144876] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1669[    8.144883] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1670[    8.144887] dp lt: tx_pu: 0x30
1671[    8.145562] dp lt: CR done
1672[    8.145564] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1673[    8.145566] dp lt: state 3 (channel equalization), pending_lt_evt 0
1674[    8.147482] dp lt: CE done
1675[    8.147485] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1676[    8.218631] dp lt: state 5 (link training pass), pending_lt_evt 1
1677[    8.218632] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1678[    8.218635] dp lt: state 1 (fast link training), pending_lt_evt 0
1679[    8.264376] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1680[    8.264384] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1681[    8.264389] dp lt: tx_pu: 0x30
1682[    8.265588] tegradc tegradc.1: dp: irq event received
1683[    8.268047] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1684[    8.268069] dp lt: fast link training fail
1685[    8.268071] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1686[    8.268074] dp lt: state 0 (Reset), pending_lt_evt 0
1687[    8.269257] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1688[    8.269393] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1689[    8.269396] dp lt: state 2 (clock recovery), pending_lt_evt 0
1690[    8.269625] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1691[    8.269632] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1692[    8.269636] dp lt: tx_pu: 0x20
1693[    8.270226] tegradc tegradc.1: dp: irq event received
1694[    8.270518] dp lt: CR not done
1695[    8.270743] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1696[    8.270745] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1697[    8.270746] dp lt: CR retry
1698[    8.270747] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1699[    8.270750] dp lt: state 2 (clock recovery), pending_lt_evt 0
1700[    8.270760] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1701[    8.270767] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1702[    8.270771] dp lt: tx_pu: 0x30
1703[    8.271444] dp lt: CR not done
1704[    8.271666] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1705[    8.271668] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1706[    8.271669] dp lt: CR retry
1707[    8.271671] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1708[    8.271673] dp lt: state 2 (clock recovery), pending_lt_evt 0
1709[    8.271683] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1710[    8.271691] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1711[    8.271695] dp lt: tx_pu: 0x30
1712[    8.272368] dp lt: CR done
1713[    8.272370] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1714[    8.272372] dp lt: state 3 (channel equalization), pending_lt_evt 0
1715[    8.274282] dp lt: CE done
1716[    8.274284] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1717[    8.342628] dp lt: state 5 (link training pass), pending_lt_evt 1
1718[    8.342629] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1719[    8.342632] dp lt: state 1 (fast link training), pending_lt_evt 0
1720[    8.391176] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1721[    8.391184] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1722[    8.391188] dp lt: tx_pu: 0x30
1723[    8.392385] tegradc tegradc.1: dp: irq event received
1724[    8.394846] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1725[    8.394868] dp lt: fast link training fail
1726[    8.394869] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1727[    8.394872] dp lt: state 0 (Reset), pending_lt_evt 0
1728[    8.396057] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1729[    8.396193] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1730[    8.396196] dp lt: state 2 (clock recovery), pending_lt_evt 0
1731[    8.396427] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1732[    8.396434] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1733[    8.396438] dp lt: tx_pu: 0x20
1734[    8.397023] tegradc tegradc.1: dp: irq event received
1735[    8.397322] dp lt: CR not done
1736[    8.397545] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1737[    8.397546] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1738[    8.397547] dp lt: CR retry
1739[    8.397549] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1740[    8.397552] dp lt: state 2 (clock recovery), pending_lt_evt 0
1741[    8.397561] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1742[    8.397569] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1743[    8.397573] dp lt: tx_pu: 0x30
1744[    8.398247] dp lt: CR not done
1745[    8.398470] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1746[    8.398471] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1747[    8.398472] dp lt: CR retry
1748[    8.398474] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1749[    8.398476] dp lt: state 2 (clock recovery), pending_lt_evt 0
1750[    8.398486] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1751[    8.398493] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1752[    8.398497] dp lt: tx_pu: 0x30
1753[    8.399174] dp lt: CR done
1754[    8.399176] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1755[    8.399179] dp lt: state 3 (channel equalization), pending_lt_evt 0
1756[    8.401091] dp lt: CE done
1757[    8.401094] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1758[    8.470631] dp lt: state 5 (link training pass), pending_lt_evt 1
1759[    8.470633] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1760[    8.470635] dp lt: state 1 (fast link training), pending_lt_evt 0
1761[    8.517985] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1762[    8.517993] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1763[    8.517997] dp lt: tx_pu: 0x30
1764[    8.519198] tegradc tegradc.1: dp: irq event received
1765[    8.521659] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1766[    8.521681] dp lt: fast link training fail
1767[    8.521683] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1768[    8.521686] dp lt: state 0 (Reset), pending_lt_evt 0
1769[    8.522872] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1770[    8.523008] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1771[    8.523011] dp lt: state 2 (clock recovery), pending_lt_evt 0
1772[    8.523241] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1773[    8.523248] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1774[    8.523252] dp lt: tx_pu: 0x20
1775[    8.523840] tegradc tegradc.1: dp: irq event received
1776[    8.524137] dp lt: CR not done
1777[    8.524360] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1778[    8.524361] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1779[    8.524362] dp lt: CR retry
1780[    8.524364] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1781[    8.524367] dp lt: state 2 (clock recovery), pending_lt_evt 0
1782[    8.524377] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1783[    8.524384] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1784[    8.524388] dp lt: tx_pu: 0x30
1785[    8.525064] dp lt: CR not done
1786[    8.525287] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1787[    8.525288] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1788[    8.525289] dp lt: CR retry
1789[    8.525291] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1790[    8.525293] dp lt: state 2 (clock recovery), pending_lt_evt 0
1791[    8.525303] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1792[    8.525311] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1793[    8.525315] dp lt: tx_pu: 0x30
1794[    8.525990] dp lt: CR done
1795[    8.525992] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1796[    8.525995] dp lt: state 3 (channel equalization), pending_lt_evt 0
1797[    8.527910] dp lt: CE done
1798[    8.527913] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1799[    8.542581] tegra-xusb 70090000.xusb: Upgrade port 0 to USB3.0
1800[    8.542585] tegra-xusb 70090000.xusb: Upgrade port 1 to USB3.0
1801[    8.601137] dp lt: state 5 (link training pass), pending_lt_evt 1
1802[    8.601140] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1803[    8.601142] dp lt: state 1 (fast link training), pending_lt_evt 0
1804[    8.635270] usb usb2: usb_suspend_both: status 0
1805[    8.644800] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1806[    8.644808] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1807[    8.644813] dp lt: tx_pu: 0x30
1808[    8.646013] tegradc tegradc.1: dp: irq event received
1809[    8.648480] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1810[    8.648503] dp lt: fast link training fail
1811[    8.648505] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1812[    8.648509] dp lt: state 0 (Reset), pending_lt_evt 0
1813[    8.649693] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1814[    8.649829] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1815[    8.649832] dp lt: state 2 (clock recovery), pending_lt_evt 0
1816[    8.650062] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1817[    8.650069] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1818[    8.650074] dp lt: tx_pu: 0x20
1819[    8.650663] tegradc tegradc.1: dp: irq event received
1820[    8.650958] dp lt: CR not done
1821[    8.651181] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1822[    8.651182] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1823[    8.651183] dp lt: CR retry
1824[    8.651185] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1825[    8.651188] dp lt: state 2 (clock recovery), pending_lt_evt 0
1826[    8.651197] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1827[    8.651205] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1828[    8.651209] dp lt: tx_pu: 0x30
1829[    8.651885] dp lt: CR not done
1830[    8.652107] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1831[    8.652109] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1832[    8.652110] dp lt: CR retry
1833[    8.652112] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1834[    8.652114] dp lt: state 2 (clock recovery), pending_lt_evt 0
1835[    8.652124] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1836[    8.652131] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1837[    8.652135] dp lt: tx_pu: 0x30
1838[    8.652811] dp lt: CR done
1839[    8.652813] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1840[    8.652816] dp lt: state 3 (channel equalization), pending_lt_evt 0
1841[    8.654731] dp lt: CE done
1842[    8.654734] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1843[    8.726630] dp lt: state 5 (link training pass), pending_lt_evt 1
1844[    8.726632] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1845[    8.726634] dp lt: state 1 (fast link training), pending_lt_evt 0
1846[    8.771621] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1847[    8.771629] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1848[    8.771634] dp lt: tx_pu: 0x30
1849[    8.772834] tegradc tegradc.1: dp: irq event received
1850[    8.775297] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1851[    8.775319] dp lt: fast link training fail
1852[    8.775321] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1853[    8.775324] dp lt: state 0 (Reset), pending_lt_evt 0
1854[    8.776510] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1855[    8.776649] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1856[    8.776652] dp lt: state 2 (clock recovery), pending_lt_evt 0
1857[    8.776882] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1858[    8.776889] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1859[    8.776893] dp lt: tx_pu: 0x20
1860[    8.777481] tegradc tegradc.1: dp: irq event received
1861[    8.777776] dp lt: CR not done
1862[    8.777999] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1863[    8.778000] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1864[    8.778002] dp lt: CR retry
1865[    8.778003] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1866[    8.778006] dp lt: state 2 (clock recovery), pending_lt_evt 0
1867[    8.778016] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1868[    8.778023] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1869[    8.778027] dp lt: tx_pu: 0x30
1870[    8.778705] dp lt: CR not done
1871[    8.778928] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1872[    8.778929] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1873[    8.778930] dp lt: CR retry
1874[    8.778932] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1875[    8.778934] dp lt: state 2 (clock recovery), pending_lt_evt 0
1876[    8.778944] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1877[    8.778951] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1878[    8.778955] dp lt: tx_pu: 0x30
1879[    8.779630] dp lt: CR done
1880[    8.779632] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1881[    8.779635] dp lt: state 3 (channel equalization), pending_lt_evt 0
1882[    8.781550] dp lt: CE done
1883[    8.781552] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1884[    8.850631] dp lt: state 5 (link training pass), pending_lt_evt 1
1885[    8.850633] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1886[    8.850635] dp lt: state 1 (fast link training), pending_lt_evt 0
1887[    8.898443] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1888[    8.898451] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1889[    8.898456] dp lt: tx_pu: 0x30
1890[    8.899656] tegradc tegradc.1: dp: irq event received
1891[    8.902117] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1892[    8.902140] dp lt: fast link training fail
1893[    8.902142] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1894[    8.902145] dp lt: state 0 (Reset), pending_lt_evt 0
1895[    8.903332] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1896[    8.903468] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1897[    8.903471] dp lt: state 2 (clock recovery), pending_lt_evt 0
1898[    8.903701] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1899[    8.903709] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1900[    8.903713] dp lt: tx_pu: 0x20
1901[    8.904296] tegradc tegradc.1: dp: irq event received
1902[    8.904597] dp lt: CR not done
1903[    8.904819] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1904[    8.904821] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1905[    8.904822] dp lt: CR retry
1906[    8.904824] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1907[    8.904826] dp lt: state 2 (clock recovery), pending_lt_evt 0
1908[    8.904836] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1909[    8.904843] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1910[    8.904847] dp lt: tx_pu: 0x30
1911[    8.905521] dp lt: CR not done
1912[    8.905744] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1913[    8.905746] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1914[    8.905747] dp lt: CR retry
1915[    8.905749] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1916[    8.905751] dp lt: state 2 (clock recovery), pending_lt_evt 0
1917[    8.905761] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1918[    8.905768] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1919[    8.905772] dp lt: tx_pu: 0x30
1920[    8.906447] dp lt: CR done
1921[    8.906449] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1922[    8.906452] dp lt: state 3 (channel equalization), pending_lt_evt 0
1923[    8.908369] dp lt: CE done
1924[    8.908371] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1925[    8.978631] dp lt: state 5 (link training pass), pending_lt_evt 1
1926[    8.978633] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1927[    8.978635] dp lt: state 1 (fast link training), pending_lt_evt 0
1928[    9.025255] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1929[    9.025263] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1930[    9.025268] dp lt: tx_pu: 0x30
1931[    9.026466] tegradc tegradc.1: dp: irq event received
1932[    9.028927] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1933[    9.028950] dp lt: fast link training fail
1934[    9.028952] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1935[    9.028955] dp lt: state 0 (Reset), pending_lt_evt 0
1936[    9.030138] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1937[    9.030275] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1938[    9.030277] dp lt: state 2 (clock recovery), pending_lt_evt 0
1939[    9.030509] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1940[    9.030516] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1941[    9.030520] dp lt: tx_pu: 0x20
1942[    9.031105] tegradc tegradc.1: dp: irq event received
1943[    9.031406] dp lt: CR not done
1944[    9.031628] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1945[    9.031630] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1946[    9.031631] dp lt: CR retry
1947[    9.031633] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1948[    9.031636] dp lt: state 2 (clock recovery), pending_lt_evt 0
1949[    9.031646] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1950[    9.031653] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1951[    9.031657] dp lt: tx_pu: 0x30
1952[    9.032333] dp lt: CR not done
1953[    9.032555] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1954[    9.032557] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1955[    9.032558] dp lt: CR retry
1956[    9.032560] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1957[    9.032562] dp lt: state 2 (clock recovery), pending_lt_evt 0
1958[    9.032572] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1959[    9.032580] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1960[    9.032584] dp lt: tx_pu: 0x30
1961[    9.033259] dp lt: CR done
1962[    9.033261] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
1963[    9.033264] dp lt: state 3 (channel equalization), pending_lt_evt 0
1964[    9.035181] dp lt: CE done
1965[    9.035184] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
1966[    9.106631] dp lt: state 5 (link training pass), pending_lt_evt 1
1967[    9.106632] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
1968[    9.106635] dp lt: state 1 (fast link training), pending_lt_evt 0
1969[    9.152075] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1970[    9.152083] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1971[    9.152087] dp lt: tx_pu: 0x30
1972[    9.153285] tegradc tegradc.1: dp: irq event received
1973[    9.155750] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1974[    9.155773] dp lt: fast link training fail
1975[    9.155775] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
1976[    9.155778] dp lt: state 0 (Reset), pending_lt_evt 0
1977[    9.156962] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
1978[    9.157099] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
1979[    9.157102] dp lt: state 2 (clock recovery), pending_lt_evt 0
1980[    9.157332] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
1981[    9.157339] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
1982[    9.157343] dp lt: tx_pu: 0x20
1983[    9.157932] tegradc tegradc.1: dp: irq event received
1984[    9.158228] dp lt: CR not done
1985[    9.158451] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1986[    9.158452] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1987[    9.158453] dp lt: CR retry
1988[    9.158455] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1989[    9.158458] dp lt: state 2 (clock recovery), pending_lt_evt 0
1990[    9.158467] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1991[    9.158475] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1992[    9.158479] dp lt: tx_pu: 0x30
1993[    9.159157] dp lt: CR not done
1994[    9.159379] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
1995[    9.159381] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
1996[    9.159382] dp lt: CR retry
1997[    9.159383] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
1998[    9.159386] dp lt: state 2 (clock recovery), pending_lt_evt 0
1999[    9.159396] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
2000[    9.159403] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
2001[    9.159407] dp lt: tx_pu: 0x30
2002[    9.160082] dp lt: CR done
2003[    9.160084] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
2004[    9.160086] dp lt: state 3 (channel equalization), pending_lt_evt 0
2005[    9.162000] dp lt: CE done
2006[    9.162003] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
2007[    9.230631] dp lt: state 5 (link training pass), pending_lt_evt 1
2008[    9.230632] dp lt: switching from state 5 (link training pass) to state 1 (fast link training)
2009[    9.230635] dp lt: state 1 (fast link training), pending_lt_evt 0
2010[    9.278886] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
2011[    9.278894] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
2012[    9.278899] dp lt: tx_pu: 0x30
2013[    9.280097] tegradc tegradc.1: dp: irq event received
2014[    9.282558] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
2015[    9.282580] dp lt: fast link training fail
2016[    9.282582] dp lt: switching from state 1 (fast link training) to state 0 (Reset)
2017[    9.282586] dp lt: state 0 (Reset), pending_lt_evt 0
2018[    9.283769] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
2019[    9.283907] dp lt: switching from state 0 (Reset) to state 2