· 8 years ago · Feb 27, 2018, 12:38 PM
1#include "stdafx.h"
2#include <winsock2.h>
3
4#pragma comment(lib, "wsock32.lib")
5#pragma warning(disable:4996)
6
7#define STUDENT_NUMBER "17008770"
8
9#define IP_ADDRESS_SERVER "127.0.0.1"
10
11#define PORT_SERVER 0x1984 // We define a port that we are going to use.
12#define PORT_CLIENT 0x1985 // We define a port that we are going to use.
13
14#define WORD unsigned short
15#define DWORD unsigned long
16#define BYTE unsigned char
17
18#define MAX_FILENAME_SIZE 500
19#define MAX_BUFFER_SIZE 500
20
21SOCKADDR_IN server_addr;
22SOCKADDR_IN client_addr;
23
24SOCKET sock; // This is our socket, it is the handle to the IO address to read/write packets
25
26WSADATA data;
27
28char InputBuffer[MAX_BUFFER_SIZE];
29
30char hex_file[MAX_BUFFER_SIZE];
31char trc_file[MAX_BUFFER_SIZE];
32
33//////////////////////////
34// Registers //
35//////////////////////////
36
37#define FLAG_I 0x10
38#define FLAG_V 0x08
39#define FLAG_N 0x04
40#define FLAG_Z 0x02
41#define FLAG_C 0x01
42#define REGISTER_A 5
43#define REGISTER_F 4
44#define REGISTER_E 3
45#define REGISTER_D 2
46#define REGISTER_C 1
47#define REGISTER_B 0
48#define REGISTER_X 0
49#define REGISTER_Y 1
50BYTE Index_Registers[2];
51
52BYTE Registers[6];
53BYTE Flags;
54WORD ProgramCounter;
55WORD StackPointer;
56
57
58////////////
59// Memory //
60////////////
61
62#define MEMORY_SIZE 65536
63
64BYTE Memory[MEMORY_SIZE];
65
66#define TEST_ADDRESS_1 0x01FA
67#define TEST_ADDRESS_2 0x01FB
68#define TEST_ADDRESS_3 0x01FC
69#define TEST_ADDRESS_4 0x01FD
70#define TEST_ADDRESS_5 0x01FE
71#define TEST_ADDRESS_6 0x01FF
72#define TEST_ADDRESS_7 0x0200
73#define TEST_ADDRESS_8 0x0201
74#define TEST_ADDRESS_9 0x0202
75#define TEST_ADDRESS_10 0x0203
76#define TEST_ADDRESS_11 0x0204
77#define TEST_ADDRESS_12 0x0205
78
79
80///////////////////////
81// Control variables //
82///////////////////////
83
84bool memory_in_range = true;
85bool halt = false;
86
87
88///////////////////////
89// Disassembly table //
90///////////////////////
91
92char opcode_mneumonics[][14] =
93{
94 "ILLEGAL ",
95 "ILLEGAL ",
96 "STX abs ",
97 "ILLEGAL ",
98 "ILLEGAL ",
99 "ILLEGAL ",
100 "ILLEGAL ",
101 "MV #,B ",
102 "MV #,C ",
103 "MV #,D ",
104 "MV #,E ",
105 "MV #,F ",
106 "MAY impl ",
107 "MYA impl ",
108 "MAS impl ",
109 "CSA impl ",
110
111 "ILLEGAL ",
112 "ILLEGAL ",
113 "STX abs,X ",
114 "ILLEGAL ",
115 "ILLEGAL ",
116 "ILLEGAL ",
117 "SWI impl ",
118 "RTI impl ",
119 "CLC impl ",
120 "SEC impl ",
121 "CLI impl ",
122 "STI impl ",
123 "STV impl ",
124 "CLV impl ",
125 "ILLEGAL ",
126 "ILLEGAL ",
127
128 "ILLEGAL ",
129 "ILLEGAL ",
130 "STX abs,Y ",
131 "ADD A,B ",
132 "SUB A,B ",
133 "CMP A,B ",
134 "OR A,B ",
135 "AND A,B ",
136 "EOR A,B ",
137 "BT A,B ",
138 "LD A,A ",
139 "LD B,A ",
140 "LD C,A ",
141 "LD D,A ",
142 "LD E,A ",
143 "LD F,A ",
144
145 "ILLEGAL ",
146 "LDX # ",
147 "STX abs,XY ",
148 "ADD A,C ",
149 "SUB A,C ",
150 "CMP A,C ",
151 "OR A,C ",
152 "AND A,C ",
153 "EOR A,C ",
154 "BT A,C ",
155 "LD A,B ",
156 "LD B,B ",
157 "LD C,B ",
158 "LD D,B ",
159 "LD E,B ",
160 "LD F,B ",
161
162 "ILLEGAL ",
163 "LDX abs ",
164 "STX (ind),XY ",
165 "ADD A,D ",
166 "SUB A,D ",
167 "CMP A,D ",
168 "OR A,D ",
169 "AND A,D ",
170 "EOR A,D ",
171 "BT A,D ",
172 "LD A,C ",
173 "LD B,C ",
174 "LD C,C ",
175 "LD D,C ",
176 "LD E,C ",
177 "LD F,C ",
178
179 "ILLEGAL ",
180 "LDX abs,X ",
181 "ILLEGAL ",
182 "ADD A,E ",
183 "SUB A,E ",
184 "CMP A,E ",
185 "OR A,E ",
186 "AND A,E ",
187 "EOR A,E ",
188 "BT A,E ",
189 "LD A,D ",
190 "LD B,D ",
191 "LD C,D ",
192 "LD D,D ",
193 "LD E,D ",
194 "LD F,D ",
195
196 "ILLEGAL ",
197 "LDX abs,Y ",
198 "ILLEGAL ",
199 "ADD A,F ",
200 "SUB A,F ",
201 "CMP A,F ",
202 "OR A,F ",
203 "AND A,F ",
204 "EOR A,F ",
205 "BT A,F ",
206 "LD A,E ",
207 "LD B,E ",
208 "LD C,E ",
209 "LD D,E ",
210 "LD E,E ",
211 "LD F,E ",
212
213 "ILLEGAL ",
214 "LDX abs,XY ",
215 "ILLEGAL ",
216 "NOP impl ",
217 "HLT impl ",
218 "ILLEGAL ",
219 "ILLEGAL ",
220 "ILLEGAL ",
221 "ILLEGAL ",
222 "ILLEGAL ",
223 "LD A,F ",
224 "LD B,F ",
225 "LD C,F ",
226 "LD D,F ",
227 "LD E,F ",
228 "LD F,F ",
229
230 "ILLEGAL ",
231 "LDX (ind),XY ",
232 "ADI # ",
233 "SBI # ",
234 "CPI # ",
235 "ORI # ",
236 "ANI # ",
237 "XRI # ",
238 "ILLEGAL ",
239 "ILLEGAL ",
240 "ILLEGAL ",
241 "ILLEGAL ",
242 "ILLEGAL ",
243 "ILLEGAL ",
244 "ILLEGAL ",
245 "ILLEGAL ",
246
247 "LDA # ",
248 "TST abs ",
249 "INC abs ",
250 "DEC abs ",
251 "RCR abs ",
252 "RLC abs ",
253 "ASL abs ",
254 "SAR abs ",
255 "COM abs ",
256 "RAL abs ",
257 "ROR abs ",
258 "LX #,A ",
259 "ILLEGAL ",
260 "LODS # ",
261 "PUSH ,A ",
262 "POP A, ",
263
264 "LDA abs ",
265 "TST abs,X ",
266 "INC abs,X ",
267 "DEC abs,X ",
268 "RCR abs,X ",
269 "RLC abs,X ",
270 "ASL abs,X ",
271 "SAR abs,X ",
272 "COM abs,X ",
273 "RAL abs,X ",
274 "ROR abs,X ",
275 "ILLEGAL ",
276 "STO abs ",
277 "LODS abs ",
278 "PUSH ,s ",
279 "POP s, ",
280
281 "LDA abs,X ",
282 "TST abs,Y ",
283 "INC abs,Y ",
284 "DEC abs,Y ",
285 "RCR abs,Y ",
286 "RLC abs,Y ",
287 "ASL abs,Y ",
288 "SAR abs,Y ",
289 "COM abs,Y ",
290 "RAL abs,Y ",
291 "ROR abs,Y ",
292 "ILLEGAL ",
293 "STO abs,X ",
294 "LODS abs,X ",
295 "PUSH ,B ",
296 "POP B, ",
297
298 "LDA abs,Y ",
299 "TST abs,XY ",
300 "INC abs,XY ",
301 "DEC abs,XY ",
302 "RCR abs,XY ",
303 "RLC abs,XY ",
304 "ASL abs,XY ",
305 "SAR abs,XY ",
306 "COM abs,XY ",
307 "RAL abs,XY ",
308 "ROR abs,XY ",
309 "ILLEGAL ",
310 "STO abs,Y ",
311 "LODS abs,Y ",
312 "PUSH ,C ",
313 "POP C, ",
314
315 "LDA abs,XY ",
316 "TSTA A,A ",
317 "INCA A,A ",
318 "DECA A,A ",
319 "RCRA A,A ",
320 "RLCA A,A ",
321 "ASLA A,A ",
322 "SARA A,A ",
323 "COMA A,A ",
324 "RALA A,A ",
325 "RORA A,A ",
326 "RTN impl ",
327 "STO abs,XY ",
328 "LODS abs,XY ",
329 "PUSH ,D ",
330 "POP D, ",
331
332 "LDA (ind),XY ",
333 "DEX impl ",
334 "INX impl ",
335 "DEY impl ",
336 "INCY impl ",
337 "ILLEGAL ",
338 "ILLEGAL ",
339 "ILLEGAL ",
340 "ILLEGAL ",
341 "JSR abs ",
342 "JMP abs ",
343 "ILLEGAL ",
344 "STO (ind),XY ",
345 "LODS (ind),XY",
346 "PUSH ,E ",
347 "POP E, ",
348
349 "BRA rel ",
350 "BCC rel ",
351 "BCS rel ",
352 "BNE rel ",
353 "BEQ rel ",
354 "BVC rel ",
355 "BVS rel ",
356 "BMI rel ",
357 "BPL rel ",
358 "BGE rel ",
359 "BLE rel ",
360 "BGT rel ",
361 "BLT rel ",
362 "ILLEGAL ",
363 "PUSH ,F ",
364 "POP F, ",
365
366};
367
368////////////////////////////////////////////////////////////////////////////////
369// Simulator/Emulator (Start) //
370////////////////////////////////////////////////////////////////////////////////
371
372BYTE fetch()
373{
374 BYTE byte = 0;
375
376 if ((ProgramCounter >= 0) && (ProgramCounter <= MEMORY_SIZE))
377 {
378 memory_in_range = true;
379 byte = Memory[ProgramCounter];
380 ProgramCounter++;
381 }
382 else
383 {
384 memory_in_range = false;
385 }
386 return byte;
387}
388
389////////////////////////////////////////////////////////////////////////////////
390// DECLARE FLAGS //
391////////////////////////////////////////////////////////////////////////////////
392
393
394void set_flag_n(BYTE inReg)
395{
396 BYTE reg;
397 reg = inReg;
398 if ((reg & 0x80) != 0) // msbit set
399 {
400 Flags = Flags | FLAG_N;
401 }
402 else
403 {
404 Flags = Flags & (0xFF - FLAG_N);
405 }
406}
407
408void set_flag_z(BYTE inReg) { //same as n with z replaced
409
410 BYTE reg;
411 reg = inReg;
412 if (reg == 0) // msbit is set
413 {
414 Flags = Flags | FLAG_Z;
415 }
416 else
417 {
418 Flags = Flags & (0xFF - FLAG_Z);
419 }
420}
421
422void set_flag_i(BYTE inReg) {
423
424}
425
426void set_flag_c(WORD data) {
427 if (data >= 0x100) {
428 Flags = Flags | FLAG_C; //Set carry flag
429 }
430 else {
431 Flags = Flags & (0xFF - FLAG_C); //Clear carry flag
432 }
433}
434
435void set_flag_v(BYTE in1, BYTE in2, BYTE out1) {
436 BYTE reg1in;
437 BYTE reg2in;
438 BYTE regOut;
439 reg1in = in1;
440 reg2in = in2;
441 regOut = out1;
442 if ((((reg1in & 0x80) == 0x80) && ((reg2in & 0x80) == 0x80) && ((regOut & 0x80) != 0x80)) //overflow
443 || (((reg1in & 0x80) != 0x80) && ((reg2in & 0x80) != 0x80) && ((regOut & 0x80) == 0x80))) {//overflow
444 Flags = Flags | FLAG_V;
445 }
446 else {
447 Flags = Flags & (0xFF - FLAG_V);
448 }
449}
450
451void set_flag_16_z(WORD inReg) { //16 bit z flag
452
453 WORD reg;
454 reg = inReg;
455 if (reg == 0) // msbit is set
456 {
457 Flags = Flags | FLAG_Z;
458 }
459 else
460 {
461 Flags = Flags & (0xFF - FLAG_Z);
462 }
463}
464
465void set_flag_16_n(WORD inReg) //16 bit n flag
466{
467 WORD reg;
468 reg = inReg;
469 if ((reg & 0x8000) != 0) {
470 Flags = Flags | FLAG_N;
471 }
472 else
473 {
474 Flags = Flags & (0xFF - FLAG_N);
475 }
476}
477
478void set_flags_16_nz(WORD data) { //16 bit n&z flags
479 set_flag_16_z(data);
480 set_flag_16_n(data);
481}
482
483void set_flags_nz(BYTE data) {
484 set_flag_z(data);
485 set_flag_n (data);
486}
487
488void set_flags_cnvz(WORD data, BYTE in1, BYTE in2 ) { //Set flags C, N, Z & V
489 set_flag_z((BYTE)data);
490 set_flag_n((BYTE)data);
491 set_flag_c(data);
492 set_flag_v(in1, in2, (BYTE)data);
493}
494
495
496
497////////////////////////////////////////////////////////////////////////////////
498// MY LITTLE FUNCTIONS //
499////////////////////////////////////////////////////////////////////////////////
500
501WORD temp_word;//
502BYTE param1;
503BYTE param2;
504
505
506void branch(BYTE in_LB) {
507 BYTE LB = 0;
508 WORD offset = 0;
509
510 LB = in_LB;
511 offset = (WORD)LB;
512 //if sign or most significant bit is 1 then adds leading ones
513 //if sign or most significant bit is 0 then leading zeros (does nothing)
514 if((offset & 0x80)!= 0) {
515 offset += 0xFF00;
516 }
517 ProgramCounter += offset;
518}
519
520void addFunction(BYTE sourceRegister) {
521
522 param1 = Registers[REGISTER_A];
523 param2 = sourceRegister;
524
525 temp_word = (WORD)param1 + (WORD)param2;
526
527 if ((Flags & FLAG_C != 0)) {
528 temp_word++;
529 }
530
531 if (temp_word >= 0x100) {
532 Flags = Flags | FLAG_C; // Set carry flag
533 }
534 else {
535 Flags = Flags & (0xFF - FLAG_C); //Clear carry flag
536 }
537
538 set_flag_n((BYTE)temp_word);
539 set_flag_z((BYTE)temp_word);
540 set_flag_v(param1, param2, (BYTE)temp_word);
541
542 Registers[REGISTER_A] = (BYTE)temp_word;
543}
544
545
546void subFunction(BYTE sourceRegister) {
547 param1 = Registers[REGISTER_A];
548 param2 = sourceRegister;
549 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_C];
550 if ((Flags & FLAG_C) != 0)
551 {
552 temp_word--;
553 }
554 set_flags_cnvz(temp_word, Registers[REGISTER_A], Registers[REGISTER_C]);
555 set_flag_v(temp_word, -Registers[REGISTER_A], Registers[REGISTER_B]);
556 Registers[REGISTER_A] = (BYTE)temp_word;
557}
558
559void orFunction(BYTE sourceRegister) {
560
561 param1 = Registers[REGISTER_A];
562 param2 = sourceRegister;
563
564 temp_word = (WORD)param1 | (WORD)param2;
565
566 set_flag_n((BYTE)temp_word);
567 set_flag_z((BYTE)temp_word);
568
569 Registers[REGISTER_A] = (BYTE)temp_word;
570 Flags = Flags & (0xFF - FLAG_V);
571}
572
573void eorFunction(BYTE sourceRegister) {
574
575 param1 = Registers[REGISTER_A];
576 param2 = sourceRegister;
577
578 temp_word = (WORD)param1 ^ (WORD)param2;
579
580 set_flag_n((BYTE)temp_word);
581 set_flag_z((BYTE)temp_word);
582
583 Registers[REGISTER_A] = (BYTE)temp_word;
584 Flags = Flags & (0xFF - FLAG_V);
585}
586
587
588void btFunction(BYTE sourceRegister) {
589
590 param1 = Registers[REGISTER_A];
591 param2 = sourceRegister;
592
593 temp_word = (WORD)param1 & (WORD)param2;
594
595 set_flag_n((BYTE)temp_word);
596 set_flag_z((BYTE)temp_word);
597
598 Flags = Flags & (0xFF - FLAG_V);
599}
600
601void cmpFunction(BYTE sourceRegister) {
602
603 param1 = Registers[REGISTER_A];
604 param2 = sourceRegister;
605
606 temp_word = (WORD)param1 - (WORD)param2;
607 if (temp_word >= 0x100) {
608 Flags = Flags | FLAG_C; // Set carry flag
609 }
610 else {
611 Flags = Flags & (0xFF - FLAG_C); // Clear carry flag
612 }
613 set_flag_n((BYTE)temp_word);
614 set_flag_z((BYTE)temp_word);
615 set_flag_v(param1, -param2, (BYTE)temp_word);
616}
617
618void andFunction(BYTE sourceRegister) {
619
620 param1 = Registers[REGISTER_A];
621 param2 = sourceRegister;
622
623 temp_word = (WORD)param1 & (WORD)param2;
624
625 set_flag_n((BYTE)temp_word);
626 set_flag_z((BYTE)temp_word);
627
628 Registers[REGISTER_A] = (BYTE)temp_word;
629 Flags = Flags & (0xFF - FLAG_V);
630}
631
632////////////////////////////////////////////////////////////////////////////////
633// GROUP ONE //
634////////////////////////////////////////////////////////////////////////////////
635
636void Group_1(BYTE opcode)
637{
638 BYTE LB = 0;
639 BYTE HB = 0;
640 WORD address = 0;
641 WORD data = 0;
642 WORD temp_word;
643 WORD offset;
644 BYTE param1;
645 BYTE param2;
646 BYTE saved_flags;
647
648 switch (opcode)
649 {
650 /////////////////////////// LDA //////////////////////////////////
651
652 //LDA - Loads Memory into Accumulator - Uses Flags N & Z//
653 case 0x90: //LDA (Hashtag) Immidiate
654 data = fetch();
655 set_flags_nz(data);
656 Registers[REGISTER_A] = data;
657 break;
658
659 case 0xA0: //LDA Absolute
660 HB = fetch();
661 LB = fetch();
662 address += (WORD)((WORD)HB << 8) + LB;
663 if (address >= 0 && address < MEMORY_SIZE) {
664 Registers[REGISTER_A] = Memory[address];
665 set_flags_nz(Registers[REGISTER_A]);
666 }
667 break;
668
669 case 0xB0: //LDA Absolute Index X
670 address += Index_Registers[REGISTER_X];
671 HB = fetch();
672 LB = fetch();
673 address += (WORD)((WORD)HB << 8) + LB;
674 if (address >= 0 && address < MEMORY_SIZE) {
675 Registers[REGISTER_A] = Memory[address];
676 set_flags_nz(Registers[REGISTER_A]);
677 }
678 break;
679
680 case 0xC0: //LDA Absolute Index Y
681 address += Index_Registers[REGISTER_Y];
682 HB = fetch();
683 LB = fetch();
684 address += (WORD)((WORD)HB << 8) + LB;
685 if (address >= 0 && address < MEMORY_SIZE) {
686 Registers[REGISTER_A] = Memory[address];
687 set_flags_nz(Registers[REGISTER_A]);
688 }
689 break;
690
691 case 0xD0: //LDA Absolute XY
692 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8)
693 + Index_Registers[REGISTER_X];
694 HB = fetch();
695 LB = fetch();
696 address += (WORD)((WORD)HB << 8) + LB;
697 if (address >= 0 && address < MEMORY_SIZE) {
698 Registers[REGISTER_A] = Memory[address];
699 set_flags_nz(Registers[REGISTER_A]);
700 }
701 break;
702
703 case 0xE0: //LDA Index XY
704 HB = fetch();
705 LB = fetch();
706 address = (WORD)((WORD)HB << 8) + LB;
707 HB = Memory[address];
708 LB = Memory[address + 1];
709 address = (WORD)((WORD)HB << 8) + LB;
710 address += Index_Registers[REGISTER_X];
711 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8);
712 if (address >= 0 && address < MEMORY_SIZE) {
713 Registers[REGISTER_A] = Memory[address];
714 set_flags_nz(Registers[REGISTER_A]);
715 }
716 break;
717
718 /////////////////////////// STO //////////////////////////////////
719
720 //STO - Stores Accumulator into Memory - Flags N & Z //
721 case 0xAC: //STO Absolute
722 HB = fetch();
723 LB = fetch();
724 address += (WORD)((WORD)HB << 8) + LB;
725 if (address >= 0 && address < MEMORY_SIZE) {
726 set_flags_nz(Registers[REGISTER_A]);
727 Memory[address] = Registers[REGISTER_A];
728 }
729 break;
730
731 case 0xBC: //STO Absolute X
732 address += Index_Registers[REGISTER_X];
733 HB = fetch();
734 LB = fetch();
735 address += (WORD)((WORD)HB << 8) + LB;
736 if (address >= 0 && address < MEMORY_SIZE) {
737 set_flags_nz(Registers[REGISTER_A]);
738 Memory[address] = Registers[REGISTER_A];
739 }
740 break;
741
742 case 0xCC: //STO Absolute Y
743 address += Index_Registers[REGISTER_Y];
744 HB = fetch();
745 LB = fetch();
746 address += (WORD)((WORD)HB << 8) + LB;
747 if (address >= 0 && address < MEMORY_SIZE) {
748 set_flags_nz(Registers[REGISTER_A]);
749 Memory[address] = Registers[REGISTER_A];
750 }
751 break;
752
753 case 0xDC: //STO Absolute XY
754 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8)
755 + Index_Registers[REGISTER_X];
756 HB = fetch();
757 LB = fetch();
758 address += (WORD)((WORD)HB << 8) + LB;
759 if (address >= 0 && address < MEMORY_SIZE) {
760 set_flags_nz(Registers[REGISTER_A]);
761 Memory[address] = Registers[REGISTER_A];
762 }
763
764 break;
765
766 case 0xEC: //STO Index XY
767 HB = fetch();
768 LB = fetch();
769 address = (WORD)((WORD)HB << 8) + LB;
770 HB = Memory[address];
771 LB = Memory[address + 1];
772 address = (WORD)((WORD)HB << 8) + LB;
773 address += Index_Registers[REGISTER_X];
774 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8);
775 if (address >= 0 && address < MEMORY_SIZE) {
776 set_flags_nz(Registers[REGISTER_A]);
777 Memory[address] = Registers[REGISTER_A];
778 }
779 break;
780
781 /////////////////////////// STX //////////////////////////////////
782
783 //STX - Stores register X into Memory - Flags N Z//
784 case 0x02: //STX Absolute
785 HB = fetch();
786 LB = fetch();
787 address += (WORD)((WORD)HB << 8) + LB;
788 if (address >= 0 && address < MEMORY_SIZE) {
789 set_flags_nz(Index_Registers[REGISTER_X]);
790 Memory[address] = Index_Registers[REGISTER_X];
791 }
792 break;
793
794 case 0x12: //STX Absolute X
795 address += Index_Registers[REGISTER_X];
796 HB = fetch();
797 LB = fetch();
798 address += (WORD)((WORD)HB << 8) + LB;
799 if (address >= 0 && address < MEMORY_SIZE) {
800 set_flags_nz(Index_Registers[REGISTER_X]);
801 Memory[address] = Index_Registers[REGISTER_X];
802 }
803 break;
804
805 case 0x22: //STX Absolute Y
806 address += Index_Registers[REGISTER_Y];
807 HB = fetch();
808 LB = fetch();
809 address += (WORD)((WORD)HB << 8) + LB;
810 if (address >= 0 && address < MEMORY_SIZE) {
811 set_flags_nz(Index_Registers[REGISTER_X]);
812 Memory[address] = Index_Registers[REGISTER_X];
813 }
814 break;
815
816 case 0x32: //STX Absolute XY
817 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
818 HB = fetch();
819 LB = fetch();
820 address += (WORD)((WORD)HB << 8) + LB;
821 if (address >= 0 && address < MEMORY_SIZE) {
822 set_flags_nz(Index_Registers[REGISTER_X]);
823 Memory[address] = Index_Registers[REGISTER_X];
824 }
825 break;
826
827 case 0x42: //STX Index XY
828 HB = fetch();
829 LB = fetch();
830 address = (WORD)((WORD)HB << 8) + LB;
831 HB = Memory[address];
832 LB = Memory[address + 1];
833 address = (WORD)((WORD)HB << 8) + LB;
834 address += Index_Registers[REGISTER_X];
835 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8);
836 if (address >= 0 && address < MEMORY_SIZE) {
837 set_flags_nz(Index_Registers[REGISTER_X]);
838 Memory[address] = Index_Registers[REGISTER_X];
839 }
840 break;
841
842 /////////////////////////// MV //////////////////////////////////
843
844 //MV - Loads Memory into register - Flags N Z//
845 case 0x07: //MV
846 data = fetch();
847 set_flags_nz(data);
848 Registers[REGISTER_B] = data;
849 break;
850
851 case 0x08: //MV
852 data = fetch();
853 set_flags_nz(data);
854 Registers[REGISTER_C] = data;
855 break;
856
857 case 0x09: //MV
858 data = fetch();
859 set_flags_nz(data);
860 Registers[REGISTER_D] = data;
861 break;
862
863 case 0x0A: //MV
864 data = fetch();
865 set_flags_nz(data);
866 Registers[REGISTER_E] = data;
867 break;
868
869 case 0x0B: //MV
870 data = fetch();
871 set_flags_nz(data);
872 Registers[REGISTER_F] = data;
873 break;
874
875 /////////////////////////// LX //////////////////////////////////
876
877
878 //LX - Loads Memory into AB register pair - Flags N Z //
879 case 0x9B: //LX
880 data = fetch();
881 Registers[REGISTER_A] = data;
882 Registers[REGISTER_B] = data;
883 set_flags_16_nz(StackPointer);
884 break;
885
886 /////////////////////////// LODS //////////////////////////////////
887
888 //LODS - Loads Memory into Stackpointer - Flags N Z//
889 case 0x9D: //LODS
890 data = fetch();
891 StackPointer = data << 8;
892 StackPointer += fetch();
893 set_flags_16_nz(StackPointer);
894 break;
895
896 case 0xAD: //LODS Absolute
897 HB = fetch();
898 LB = fetch();
899 address += (WORD)((WORD)HB << 8) + LB;
900 if (address >= 0 && address < MEMORY_SIZE - 1) {
901 StackPointer = (WORD)Memory[address] << 8;
902 StackPointer += Memory[address + 1];
903 set_flags_16_nz(StackPointer);
904 }
905 break;
906
907 case 0xBD: //LODS Absolute X
908 address += Index_Registers[REGISTER_X];
909 HB = fetch();
910 LB = fetch();
911 address += (WORD)((WORD)HB << 8) + LB;
912 if (address >= 0 && address < MEMORY_SIZE - 1) {
913 StackPointer = (WORD)Memory[address] << 8;
914 StackPointer += Memory[address + 1];
915 set_flags_16_nz(StackPointer);
916 }
917 break;
918
919 case 0xCD: //LODS Absolute Y
920 address += Index_Registers[REGISTER_Y];
921 HB = fetch();
922 LB = fetch();
923 address += (WORD)((WORD)HB << 8) + LB;
924 if (address >= 0 && address < MEMORY_SIZE - 1) {
925 StackPointer = (WORD)Memory[address] << 8;
926 StackPointer += Memory[address + 1];
927 set_flags_16_nz(StackPointer);
928 }
929 break;
930
931 case 0xDD: //LODS Absolute XY
932 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
933 HB = fetch();
934 LB = fetch();
935 address += (WORD)((WORD)HB << 8) + LB;
936 if (address >= 0 && address < MEMORY_SIZE - 1) {
937 StackPointer = (WORD)Memory[address] << 8;
938 StackPointer += Memory[address + 1];
939 set_flags_16_nz(StackPointer);
940 }
941 break;
942
943 case 0xED: //LODS Index XY
944 HB = fetch();
945 LB = fetch();
946 address = (WORD)((WORD)HB << 8) + LB;
947 HB = Memory[address];
948 LB = Memory[address + 1];
949 address = (WORD)((WORD)HB << 8) + LB;
950 address += Index_Registers[REGISTER_X];
951 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8);
952 if (address >= 0 && address < MEMORY_SIZE - 1) {
953 Memory[address] = Registers[REGISTER_A];
954 StackPointer = (WORD)Memory[address] << 8;
955 StackPointer += Memory[address + 1];
956 set_flags_16_nz(StackPointer);
957 }
958 break;
959
960 /////////////////////////// LDX //////////////////////////////////
961
962 //LDX - Loads Memory into register X - Flags N Z//
963 case 0x31: //LDX Immidiate
964 data = fetch();
965 set_flags_nz(data);
966 Index_Registers[REGISTER_X] = data;
967 break;
968
969 case 0x41: //LDX Absolute
970 HB = fetch();
971 LB = fetch();
972 address += (WORD)((WORD)HB << 8) + LB;
973 if (address >= 0 && address < MEMORY_SIZE) {
974 Index_Registers[REGISTER_X] = Memory[address];
975 set_flags_nz(Index_Registers[REGISTER_X]);
976 }
977 break;
978
979 case 0x51: //LDX Absolute Index X
980 address += Index_Registers[REGISTER_X];
981 HB = fetch();
982 LB = fetch();
983 address += (WORD)((WORD)HB << 8) + LB;
984 if (address >= 0 && address < MEMORY_SIZE) {
985 Index_Registers[REGISTER_X] = Memory[address];
986 set_flags_nz(Index_Registers[REGISTER_X]);
987 }
988 break;
989
990 case 0x61: //LDX Absolute Index Y
991 address += Index_Registers[REGISTER_Y];
992 HB = fetch();
993 LB = fetch();
994 address += (WORD)((WORD)HB << 8) + LB;
995 if (address >= 0 && address < MEMORY_SIZE) {
996 Index_Registers[REGISTER_X] = Memory[address];
997 set_flags_nz(Index_Registers[REGISTER_X]);
998 }
999 break;
1000
1001 case 0x71: //LDX Absolute XY
1002 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8)
1003 + Index_Registers[REGISTER_X];
1004 HB = fetch();
1005 LB = fetch();
1006 address += (WORD)((WORD)HB << 8) + LB;
1007 if (address >= 0 && address < MEMORY_SIZE) {
1008 Index_Registers[REGISTER_X] = Memory[address];
1009 set_flags_nz(Index_Registers[REGISTER_X]);
1010 }
1011 break;
1012
1013 case 0x81: //LDX Index XY
1014 HB = fetch();
1015 LB = fetch();
1016 address = (WORD)((WORD)HB << 8) + LB;
1017 HB = Memory[address];
1018 LB = Memory[address + 1];
1019 address = (WORD)((WORD)HB << 8) + LB;
1020 address += Index_Registers[REGISTER_X];
1021 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8);
1022 if (address >= 0 && address < MEMORY_SIZE) {
1023 Index_Registers[REGISTER_X] = Memory[address];
1024 set_flags_nz(Index_Registers[REGISTER_X]);
1025 }
1026 break;
1027
1028 /////////////////////////// ADD //////////////////////////////////
1029
1030 //ADD - Register added to Accumulator with Carry - Flags V N Z C //
1031 case 0x23: //ADD A to B
1032 addFunction(Registers[REGISTER_B]);
1033 break;
1034
1035 case 0x33: //ADD A to C
1036 addFunction(Registers[REGISTER_C]);
1037 break;
1038
1039 case 0x43: //ADD A to D
1040 addFunction(Registers[REGISTER_D]);
1041 break;
1042
1043 case 0x53: //ADD A to E
1044 addFunction(Registers[REGISTER_E]);
1045
1046 break;
1047
1048 case 0x63: //ADD A to F
1049 addFunction(Registers[REGISTER_F]);
1050 break;
1051
1052 /////////////////////////// SUB //////////////////////////////////
1053
1054 //SUB - Register subtracted to Accumulator with Carry - Flags N C Z V//
1055 case 0x24: //SUB A to B
1056 subFunction(Registers[REGISTER_B]);
1057 break;
1058
1059 case 0x34: //SUB A to C
1060 subFunction(Registers[REGISTER_C]);
1061 break;
1062
1063 case 0x44: //SUB A to D
1064 subFunction(Registers[REGISTER_D]);
1065
1066 break;
1067
1068 case 0x54: //SUB A to E
1069 subFunction(Registers[REGISTER_E]);
1070
1071 break;
1072
1073 case 0x64: //SUB A to F
1074 subFunction(Registers[REGISTER_F]);
1075
1076 break;
1077
1078 case 0x25: //CMP
1079 cmpFunction(Registers[REGISTER_B]);
1080 break;
1081
1082 /////////////////////////// CMP //////////////////////////////////
1083
1084 //CMP - Register compared to Accumulator - Flags V N Z C//
1085 case 0x35: //CMP
1086 cmpFunction(Registers[REGISTER_C]);
1087 break;
1088
1089 case 0x45: //CMP
1090 cmpFunction(Registers[REGISTER_D]);
1091 break;
1092
1093 case 0x55: //CMP
1094 cmpFunction(Registers[REGISTER_E]);
1095 break;
1096
1097 case 0x65: //CMP
1098 cmpFunction(Registers[REGISTER_F]);
1099 break;
1100
1101 /////////////////////////// MAS //////////////////////////////////
1102
1103 //MAS - Transters Accumulator to Status register//
1104 case 0x0E: //MAS
1105 Flags = Registers[REGISTER_A];
1106 break;
1107
1108 /////////////////////////// CSA //////////////////////////////////
1109
1110 //CSA - Transters Status register to Accumulator//
1111 case 0x0F: //CSA impl - status reg to acc
1112 Registers[REGISTER_A] = Flags;
1113 break;
1114
1115 /////////////////////////// MAY //////////////////////////////////
1116
1117 //MAY - Transters Accumulator to register Y - Flags N//
1118 case 0x0C: //MAY
1119 Registers[REGISTER_A] = Index_Registers[REGISTER_Y];
1120 set_flag_n((BYTE)Registers[REGISTER_A]);
1121 break;
1122
1123 /////////////////////////// MYA //////////////////////////////////
1124
1125 //MYA - Transters register Y to Accumulator - Flags N Z //
1126 case 0x0D: //MYA impl
1127 Index_Registers[REGISTER_Y] = Registers[REGISTER_A];
1128 set_flags_nz(data);
1129 Registers[REGISTER_Y] = data;
1130 break;
1131
1132 /////////////////////////// CLC //////////////////////////////////
1133
1134 case 0x18: //CLC -Clear carry flag
1135 Flags = Flags & (0xFF - FLAG_C); //0xff masks the variable so it leaves only the value in the last 8 bits and ignores all the rest of the bits
1136 break; //so becomes 255 from previously 00000000000000000000000011111111
1137
1138 /////////////////////////// SEC //////////////////////////////////
1139
1140 case 0x19: //SEC -Set carry flag
1141 Flags = Flags | FLAG_C;
1142 break;
1143
1144 /////////////////////////// CLI //////////////////////////////////
1145
1146 case 0x1A: //CLI - Clear interupt flag
1147 Flags = Flags & (0xFF - FLAG_I);
1148 break;
1149
1150 /////////////////////////// STI //////////////////////////////////
1151
1152 case 0x1B: //STI - Set interupt flag
1153 Flags = Flags | FLAG_I;
1154 break;
1155
1156 /////////////////////////// CLV //////////////////////////////////
1157
1158 case 0x1D: //CLV - Clear overflow flag
1159 Flags = Flags & (0xFF - FLAG_V);
1160 break;
1161
1162 /////////////////////////// STV //////////////////////////////////
1163
1164 case 0x1C: //STV - Set overflow flag
1165 Flags = Flags | FLAG_V;
1166 break;
1167
1168 /////////////////////////// PUSH //////////////////////////////////
1169
1170 //PUSH - Pushes Register onto the Stack//
1171 case 0x9E: //PUSH (Push Register onto Stack)
1172 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) { //Check that address held in the SP is valid
1173 Memory[StackPointer] = Registers[REGISTER_A];
1174 StackPointer--;
1175 }
1176 break;
1177
1178 case 0xAE: //PUSH (Push Register onto Stack)
1179 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) { //Check that address held in the SP is valid
1180 Flags = Registers[REGISTER_A];
1181 StackPointer--;
1182 }
1183 break;
1184
1185 case 0xBE: //PUSH (Push Register onto Stack)
1186 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) { //Check that address held in the SP is valid
1187 Memory[StackPointer] = Registers[REGISTER_B];
1188 StackPointer--;
1189 }
1190 break;
1191
1192 case 0xCE: //PUSH (Push Register onto Stack)
1193 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) { //Check that address held in the SP is valid
1194 Memory[StackPointer] = Registers[REGISTER_C];
1195 StackPointer--;
1196 }
1197 break;
1198
1199 case 0xDE: //PUSH (Push Register onto Stack)
1200 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) { //Check that address held in the SP is valid
1201 Memory[StackPointer] = Registers[REGISTER_D];
1202 StackPointer--;
1203 }
1204 break;
1205
1206 case 0xEE: //PUSH (Push Register onto Stack)
1207 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) { //Check that address held in the SP is valid
1208 Memory[StackPointer] = Registers[REGISTER_E];
1209 StackPointer--;
1210 }
1211 break;
1212
1213 case 0xFE: //PUSH (Push Register onto Stack)
1214 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) { //Check that address held in the SP is valid
1215 Memory[StackPointer] = Registers[REGISTER_F];
1216 StackPointer--;
1217 }
1218 break;
1219
1220 /////////////////////////// POP //////////////////////////////////
1221
1222 //POP - Pop the top of the Stack into the Register
1223 case 0x9F: //POP
1224 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) { //Check that address held in the SP is valid
1225 StackPointer++;
1226 Registers[REGISTER_A] = Memory[StackPointer];
1227 }
1228 break;
1229
1230 case 0xAF: //POP
1231 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) { //Check that address held in the SP is valid
1232 StackPointer++;
1233 Flags = Memory[StackPointer];
1234 }
1235 break;
1236
1237 case 0xBF: //POP
1238 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) { //Check that address held in the SP is valid
1239 StackPointer++;
1240 Registers[REGISTER_B] = Memory[StackPointer];
1241 }
1242 break;
1243
1244 case 0xCF: //POP
1245 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) { //Check that address held in the SP is valid
1246 StackPointer++;
1247 Registers[REGISTER_C] = Memory[StackPointer];
1248 }
1249 break;
1250
1251 case 0xDF: //POP
1252 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) { //Check that address held in the SP is valid
1253 StackPointer++;
1254 Registers[REGISTER_D] = Memory[StackPointer];
1255 }
1256 break;
1257
1258 case 0xEF: //POP
1259 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) { //Check that address held in the SP is valid
1260 StackPointer++;
1261 Registers[REGISTER_E] = Memory[StackPointer];
1262 }
1263 break;
1264
1265 case 0xFF: //POP
1266 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) { //Check that address held in the SP is valid
1267 StackPointer++;
1268 Registers[REGISTER_F] = Memory[StackPointer];
1269 }
1270 break;
1271
1272 /////////////////////////// JMP //////////////////////////////////
1273
1274 //JMP - Loads Memory into ProgramCounter
1275 case 0xEA: //JMP Abs
1276 HB = fetch();
1277 LB = fetch();
1278 address = ((WORD)HB << 8) + (WORD)LB;
1279 ProgramCounter = address;
1280 break;
1281
1282 /////////////////////////// JSR //////////////////////////////////
1283
1284 //JSR - Jump to subroutine //
1285 case 0xE9: //JSR
1286 HB = fetch();
1287 LB = fetch();
1288 address = ((WORD)HB << 8) + (WORD)LB;
1289 if ((StackPointer >= 2) && (StackPointer < MEMORY_SIZE)) {
1290 Memory[StackPointer] = (BYTE)(ProgramCounter & 0xFF);
1291 StackPointer--;
1292 Memory[StackPointer] = (BYTE)((ProgramCounter >> 8) & 0xFF);
1293 StackPointer--;
1294 }
1295 ProgramCounter = address;
1296 break;
1297
1298 /////////////////////////// RTN //////////////////////////////////
1299
1300 //RTN - pulls two bytes off of stack and puts them into program counter register
1301 case 0xDB: //RTN
1302 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 2)) {
1303 StackPointer++;
1304 HB = Memory[StackPointer];
1305 StackPointer++;
1306 LB = Memory[StackPointer];
1307 }
1308 ProgramCounter = ((WORD)HB << 8) + (WORD)LB;
1309 break;
1310
1311 /////////////////////////// INCA //////////////////////////////////
1312
1313 //INCA - Increment Memory or Accumulator - Flags N Z//
1314 case 0xD2: //INCA
1315 ++Registers[REGISTER_A];
1316 set_flag_n((BYTE)Registers[REGISTER_A]); //no point in calling nz function as it too is 2 lines of code
1317 set_flag_z((BYTE)Registers[REGISTER_A]); //so becomes 255 from previously 00000000000000000000000011111111
1318 break;
1319
1320 /////////////////////////// INX //////////////////////////////////
1321
1322 //INX - Increments register X - Flags Z
1323 case 0xE2: //INX (increment reg X)
1324 ++Index_Registers[REGISTER_X];
1325 set_flag_z((BYTE)Index_Registers[REGISTER_X]); //was in pp without (BYTE) same as INCA with change of register
1326 break;
1327
1328 /////////////////////////// DEX //////////////////////////////////
1329
1330 //DEX - Decrements register X - Flags Z
1331 case 0xE1: //DEX (decrement reg X)
1332 --Index_Registers[REGISTER_X];
1333 set_flag_z((BYTE)Index_Registers[REGISTER_X]); //was in pp without (BYTE) same as INCA with change of register
1334 break;
1335
1336 /////////////////////////// AND //////////////////////////////////
1337
1338 //AND - Register bitwise and with Accumulator - Flags N Z//
1339 case 0x27: //AND
1340 andFunction(Registers[REGISTER_B]);
1341 break;
1342
1343 case 0x37: //AND
1344 andFunction(Registers[REGISTER_C]);
1345 break;
1346
1347 case 0x47: //AND
1348 andFunction(Registers[REGISTER_D]);
1349 break;
1350
1351 case 0x57: //AND
1352 andFunction(Registers[REGISTER_E]);
1353 break;
1354
1355 case 0x67: //AND
1356 andFunction(Registers[REGISTER_F]);
1357 break;
1358
1359 /////////////////////////// BT //////////////////////////////////
1360
1361 //BT -Register Bit tested with Accumulator - Flags N Z//
1362 case 0x29: //BT
1363 btFunction(Registers[REGISTER_B]);
1364 break;
1365
1366 case 0x39: //BT
1367 btFunction(Registers[REGISTER_C]);
1368 break;
1369
1370 case 0x49: //BT
1371 btFunction(Registers[REGISTER_D]);
1372 break;
1373
1374 case 0x59: //BT
1375 btFunction(Registers[REGISTER_E]);
1376 break;
1377
1378 case 0x69: //BT
1379 btFunction(Registers[REGISTER_F]);
1380 break;
1381
1382 /////////////////////////// ADI //////////////////////////////////
1383
1384 //ADI - Data added to Accumulator with Carry - Flags N C Z V//
1385 case 0x82: //ADI
1386 data = fetch();
1387 temp_word = (WORD)Registers[REGISTER_A] + (WORD)data;
1388 if ((Flags & FLAG_C) != 0)
1389 {
1390 temp_word++;
1391 }
1392 set_flags_cnvz(temp_word, Registers[REGISTER_A], data);
1393 Registers[REGISTER_A] = (BYTE)temp_word;
1394 break;
1395
1396 /////////////////////////// SBI //////////////////////////////////
1397
1398 //SBI - Data subtracted to # 0x83 Accumulator with Carry - Flags C N Z V//
1399 case 0x83: //SBI
1400 data = fetch();
1401 temp_word = (WORD)Registers[REGISTER_A] - (WORD)data;
1402 if ((Flags & FLAG_C) != 0)
1403 {
1404 temp_word++;
1405 }
1406 set_flags_cnvz(temp_word, Registers[REGISTER_A], data);
1407 Registers[REGISTER_A] = (BYTE)temp_word;
1408 break;
1409
1410 /////////////////////////// CPI //////////////////////////////////
1411
1412 //CPI - Data compared to Accumulator - Flags N Z C V//
1413 case 0x84: //CPI
1414 data = fetch();
1415 temp_word = (WORD)Registers[REGISTER_A] - (WORD)data;
1416 if ((Flags & FLAG_C) != 0)
1417 {
1418 temp_word++;
1419 }
1420 set_flags_cnvz(temp_word, Registers[REGISTER_A], data);
1421 break;
1422
1423 /////////////////////////// OR //////////////////////////////////
1424
1425 //OR - Register bitwise inclusive or with Accumulator - Flags N Z
1426 case 0x26: //OR
1427 orFunction(Registers[REGISTER_B]);
1428 break;
1429
1430 case 0x36: //OR
1431 orFunction(Registers[REGISTER_C]);
1432 break;
1433
1434 case 0x46: //OR
1435 orFunction(Registers[REGISTER_D]);
1436 break;
1437
1438 case 0x56: //OR
1439 orFunction(Registers[REGISTER_E]);
1440 break;
1441
1442 case 0x66: //OR
1443 orFunction(Registers[REGISTER_F]);
1444 break;
1445
1446 /////////////////////////// EOR //////////////////////////////////
1447
1448 //EOR - Register bitwise exclusive or with Accumulator - Flags N Z//
1449 case 0x28: //EOR
1450 eorFunction(Registers[REGISTER_B]);
1451 break;
1452
1453 case 0x38: //EOR
1454 eorFunction(Registers[REGISTER_C]);
1455 break;
1456
1457 case 0x48: //EOR
1458 eorFunction(Registers[REGISTER_D]);
1459 break;
1460
1461 case 0x58: //EOR
1462 eorFunction(Registers[REGISTER_E]);
1463 break;
1464
1465 case 0x68: //EOR
1466 eorFunction(Registers[REGISTER_F]);
1467 break;
1468
1469 /////////////////////////// INC //////////////////////////////////
1470
1471 //INC - Increment Memory or Accumulator - Flags N Z//
1472 case 0x92: //INC Absolute
1473 HB = fetch();
1474 LB = fetch();
1475 address += (WORD)((WORD)HB << 8) + LB;
1476 if (address >= 0 && address < MEMORY_SIZE) {
1477 ++Memory[address];
1478 }
1479 set_flag_n((BYTE)Memory[address]);
1480 set_flag_z((BYTE)Memory[address]);
1481 break;
1482
1483 case 0xA2: //INC Absolute X
1484 address += Index_Registers[REGISTER_X];
1485 HB = fetch();
1486 LB = fetch();
1487 address += (WORD)((WORD)HB << 8) + LB;
1488 if (address >= 0 && address < MEMORY_SIZE) {
1489 ++Memory[address];
1490 }
1491 set_flag_n((BYTE)Memory[address]);
1492 set_flag_z((BYTE)Memory[address]);
1493 break;
1494
1495 case 0xB2: //INC Absolute Y
1496 address += Index_Registers[REGISTER_Y];
1497 HB = fetch();
1498 LB = fetch();
1499 address += (WORD)((WORD)HB << 8) + LB;
1500 if (address >= 0 && address < MEMORY_SIZE) {
1501 ++Memory[address];
1502 }
1503 set_flag_n((BYTE)Memory[address]);
1504 set_flag_z((BYTE)Memory[address]);
1505 break;
1506
1507 case 0xC2: //INC Absolute XY
1508 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8)
1509 + Index_Registers[REGISTER_X];
1510 HB = fetch();
1511 LB = fetch();
1512 address += (WORD)((WORD)HB << 8) + LB;
1513 if (address >= 0 && address < MEMORY_SIZE) {
1514 ++Memory[address];
1515 }
1516 set_flag_n((BYTE)Memory[address]);
1517 set_flag_z((BYTE)Memory[address]);
1518 break;
1519
1520 /////////////////////////// DEC //////////////////////////////////
1521
1522 //DEC - Decrement Memory or Accumulator - Flags N Z//
1523 case 0x93: //DEC
1524 HB = fetch();
1525 LB = fetch();
1526 address += (WORD)((WORD)HB << 8) + LB;
1527 if (address >= 0 && address < MEMORY_SIZE) {
1528 --Memory[address];
1529 }
1530 set_flag_n((BYTE)Memory[address]);
1531 set_flag_z((BYTE)Memory[address]);
1532 break;
1533
1534 case 0xA3: //DEC
1535 address += Index_Registers[REGISTER_X];
1536 HB = fetch();
1537 LB = fetch();
1538 address += (WORD)((WORD)HB << 8) + LB;
1539 if (address >= 0 && address < MEMORY_SIZE) {
1540 --Memory[address];
1541 }
1542 set_flag_n((BYTE)Memory[address]);
1543 set_flag_z((BYTE)Memory[address]);
1544 break;
1545
1546 case 0xB3: //DEC
1547 address += Index_Registers[REGISTER_Y];
1548 HB = fetch();
1549 LB = fetch();
1550 address += (WORD)((WORD)HB << 8) + LB;
1551 if (address >= 0 && address < MEMORY_SIZE) {
1552 --Memory[address];
1553 }
1554 set_flag_n((BYTE)Memory[address]);
1555 set_flag_z((BYTE)Memory[address]);
1556 break;
1557
1558 case 0xC3: //DEC
1559 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8)
1560 + Index_Registers[REGISTER_X];
1561 HB = fetch();
1562 LB = fetch();
1563 address += (WORD)((WORD)HB << 8) + LB;
1564 if (address >= 0 && address < MEMORY_SIZE) {
1565 --Memory[address];
1566 }
1567 set_flag_n((BYTE)Memory[address]);
1568 set_flag_z((BYTE)Memory[address]);
1569 break;
1570
1571 /////////////////////////// DECA //////////////////////////////////
1572
1573 //DECA - Decrement Memory or Accumulator - Flags N Z//
1574 case 0xD3: //DECA
1575 --Registers[REGISTER_A];
1576 set_flag_n((BYTE)Registers[REGISTER_A]);
1577 set_flag_z((BYTE)Registers[REGISTER_A]); //was in pp without (BYTE)
1578 break;
1579
1580 /////////////////////////// INCY //////////////////////////////////
1581
1582 //INCY - Increments register Y - Flags Z
1583 case 0xE4: //INCY (increment reg Y)
1584 ++Index_Registers[REGISTER_Y];
1585 set_flag_z((BYTE)Index_Registers[REGISTER_Y]); //was in pp without (BYTE) same as INCA with change of register
1586 break;
1587
1588 /////////////////////////// DEY //////////////////////////////////
1589
1590 //DEY - Decrements register Y - Flags Z
1591 case 0xE3: //DEY (decrements reg Y)
1592 --Index_Registers[REGISTER_Y];
1593 set_flag_z((BYTE)Index_Registers[REGISTER_Y]); //was in pp without (BYTE) same as INCA with change of register
1594 break;
1595
1596 /////////////////////////// NOP //////////////////////////////////
1597
1598 case 0x73: //NOP - No Operation
1599 //Empty area as 'no operation'
1600 break;
1601
1602 //ANI - Data bitwise and with Accumulator - Flags N Z//
1603 case 0x86: //ANI
1604 data = fetch();
1605 Registers[REGISTER_A] = Registers[REGISTER_A] & data;
1606 set_flag_n((BYTE)Registers[REGISTER_A]);
1607 set_flag_z((BYTE)Registers[REGISTER_A]);
1608 break;
1609
1610 /////////////////////////// ORI //////////////////////////////////
1611
1612 //ORI - Data bitwise inclusive or with Accumulator - Flags N Z//
1613 case 0x85: //ORI
1614 data = fetch();
1615 Registers[REGISTER_A] = Registers[REGISTER_A] | data;
1616 set_flag_n((BYTE)Registers[REGISTER_A]);
1617 set_flag_z((BYTE)Registers[REGISTER_A]);
1618 break;
1619
1620 /////////////////////////// XRI //////////////////////////////////
1621
1622 //XRI - Data bitwise exclusive or with Accumulator - Flags N Z//
1623 case 0x87: //XRI
1624 data = fetch();
1625 Registers[REGISTER_A] = Registers[REGISTER_A] ^ data;
1626 set_flag_n((BYTE)Registers[REGISTER_A]);
1627 set_flag_z((BYTE)Registers[REGISTER_A]);
1628 break;
1629
1630 /////////////////////////// HLT //////////////////////////////////
1631
1632 case 0x74: //HLT - Wait for interupt
1633 halt = true;
1634 break;
1635
1636 /////////////////////////// TSTA //////////////////////////////////
1637
1638 case 0xD1: //TSTA
1639 HB = fetch();
1640 LB = fetch();
1641 address += (WORD)((WORD)HB << 8) + LB;
1642 address += address & Registers[REGISTER_A];
1643 set_flags_nz((BYTE)Registers[REGISTER_A]);
1644 break;
1645
1646 /////////////////////////// TST //////////////////////////////////
1647
1648 //TST - Bit test Memory or Accumulator - Flags N Z//
1649 case 0x91: //TST
1650 HB = fetch();
1651 LB = fetch();
1652 address += (WORD)((WORD)HB << 8) + LB;
1653 address += address & Registers[REGISTER_A];
1654 set_flags_nz((BYTE)Memory[address]);
1655 break;
1656
1657 case 0xA1: //TST abs,X
1658 HB = fetch();
1659 LB = fetch();
1660 address += (WORD)((WORD)HB << 8) + LB;
1661 address += address & Index_Registers[REGISTER_X];
1662 set_flags_nz((BYTE)Memory[address]);
1663 break;
1664
1665 case 0xB1: //TST abs,Y
1666 HB = fetch();
1667 LB = fetch();
1668 address += (WORD)((WORD)HB << 8) + LB;
1669 address += address & Index_Registers[REGISTER_Y];
1670 set_flags_nz((BYTE)Memory[address]);
1671 break;
1672
1673 case 0xC1: //TST abs,XY
1674 HB = fetch();
1675 LB = fetch();
1676 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1677 address += (WORD)((WORD)HB << 8) + LB;
1678 set_flags_nz((BYTE)Memory[address]);
1679 break;
1680
1681 /////////////////////////// BRA //////////////////////////////////
1682
1683 case 0xF0: //BRA (relative addressing mode (similar to JMP))
1684 LB = fetch(); //(treated as 2-s compliment)
1685 branch(LB);
1686 break;
1687
1688 /////////////////////////// BCS /////////////////////////////////
1689
1690 case 0xF2: //BCS - Branch on Carry set
1691 LB = fetch();
1692 offset = (WORD)LB;
1693 if ((Flags & FLAG_C) != 0) {
1694 if ((offset & 0x80) != 0) {
1695 offset = offset + 0xFF00;
1696 }
1697 address = ProgramCounter + offset;
1698 ProgramCounter = address;
1699 }
1700 break;
1701
1702 /////////////////////////// BCC //////////////////////////////////
1703
1704 case 0XF1: //BCC - Branch on Carry clear
1705 LB = fetch();
1706 offset = (WORD)LB;
1707 if ((Flags & FLAG_C) == 0) {
1708 if ((offset & 0x80) != 0) {
1709 offset = offset + 0xFF00;
1710 }
1711 address = ProgramCounter + offset;
1712 ProgramCounter = address;
1713 }
1714 break;
1715
1716 /////////////////////////// BNE //////////////////////////////////
1717
1718 case 0xF3: //BNE -Branch on result not Zero
1719 LB = fetch();
1720 if ((Flags & FLAG_Z) == 0) { //Branch if result is not 0 (z flag not set)
1721 branch(LB);
1722 }
1723 break;
1724
1725 /////////////////////////// BEQ //////////////////////////////////
1726
1727 case 0xF4: //BEQ - Branch on result equal to Zero
1728 LB = fetch();
1729 if ((Flags & FLAG_Z) == FLAG_Z) { //Branch if result is 0 (z flag set)
1730 branch(LB);
1731 }
1732 break;
1733
1734 /////////////////////////// BVC //////////////////////////////////
1735
1736 case 0xF5: //BVC - Branch on overflow clear
1737 LB = fetch();
1738 if ((Flags & FLAG_V) == 0) { //Branch if V flag is not set
1739 branch(LB);
1740 }
1741 break;
1742
1743 /////////////////////////// BVS //////////////////////////////////
1744
1745 case 0xF6: //BVS - Branch on overflow set
1746 LB = fetch();
1747 if ((Flags & FLAG_V) == FLAG_V) { //Branch if V flag is set
1748 branch(LB);
1749 }
1750 break;
1751
1752 /////////////////////////// BMI //////////////////////////////////
1753
1754 case 0xF7: //BMI - Branch on negative result
1755 LB = fetch();
1756 if ((Flags & FLAG_N) == FLAG_N) { //Branch if result is negative (n flag set)
1757 branch(LB);
1758 }
1759 break;
1760
1761 /////////////////////////// BPL //////////////////////////////////
1762
1763 case 0xF8: //BPL - Branch on positive result
1764 LB = fetch();
1765 if ((Flags & FLAG_N) == 0) { //Branch if N flag is not set (result isnt negative)
1766 branch(LB);
1767 }
1768 break;
1769
1770 /////////////////////////// BGE //////////////////////////////////
1771
1772 case 0xF9: //BGE - Branch on result less than or equal to zer
1773 LB = fetch();
1774 if (((Flags & FLAG_Z) == FLAG_Z) || (((Flags & FLAG_N) == 0) != ((Flags & FLAG_V) == FLAG_V))) {
1775 branch(LB);
1776 }
1777 break;
1778
1779 /////////////////////////// BLE //////////////////////////////////
1780
1781 case 0xFA: //BLE - Branch on result greater then or equal to zero
1782 LB = fetch();
1783 if (((Flags & FLAG_Z) == FLAG_Z) || (((Flags & FLAG_N) == FLAG_N) != ((Flags & FLAG_V) == FLAG_V))) {
1784 branch(LB);
1785 }
1786 break;
1787
1788 /////////////////////////// BGT //////////////////////////////////
1789
1790 case 0xFB: //BGT - Branch on result less than zero
1791 LB = fetch();
1792 if (((Flags & FLAG_Z) == 0) && (((Flags & FLAG_N) == 0) != ((Flags & FLAG_V) == FLAG_V))) {
1793 branch(LB);
1794 }
1795 break;
1796
1797 /////////////////////////// BLT //////////////////////////////////
1798
1799 case 0xFC: //BLT - Branch on result greater then zero
1800 LB = fetch();
1801 if (((Flags & FLAG_Z) == 0) && (((Flags & FLAG_N) == FLAG_N) != ((Flags & FLAG_V) == FLAG_V))) {
1802 branch(LB);
1803 }
1804 break;
1805
1806 /////////////////////////// SAR //////////////////////////////////
1807
1808 //SAR - Arithmetic shift right Memory or Accumulator - Flags C N Z//
1809 case 0x97: //SAR (abs,Y)
1810
1811 HB = fetch();
1812 LB = fetch();
1813 address += (WORD)((WORD)HB << 8) + LB;
1814 if (address >= 0 && address < MEMORY_SIZE)
1815 {
1816 temp_word = Memory[address];
1817 if (temp_word >= 0x100)
1818 {
1819 //set carry flag
1820 Flags = Flags | FLAG_C;
1821 }
1822 else
1823 {
1824 //clear carry flag
1825 Flags = Flags & (0xFF - FLAG_C);
1826 }
1827
1828 set_flag_z((BYTE)temp_word);
1829 set_flag_n((BYTE)temp_word);
1830
1831 if ((temp_word & 0x01) != 0)
1832 {
1833 Flags |= FLAG_C;
1834 }
1835 //Shifts temp_word one place right
1836 temp_word >>= 1;
1837 //Sets the negative flag
1838 if ((Flags & FLAG_N) != 0)
1839 {
1840 temp_word |= 0x80;
1841 }
1842 //Puts the shifted address back into memory
1843 Memory[address] = (BYTE)temp_word;
1844 }
1845 break;
1846
1847 case 0xA7: //SAR (abs,X)
1848 address += Index_Registers[REGISTER_X];
1849 HB = fetch();
1850 LB = fetch();
1851 address += (WORD)((WORD)HB << 8) + LB;
1852 if (address >= 0 && address < MEMORY_SIZE)
1853 {
1854 temp_word = Memory[address];
1855 if (temp_word >= 0x100)
1856 {
1857 //set carry flag
1858 Flags = Flags | FLAG_C;
1859 }
1860 else
1861 {
1862 //clear carry flag
1863 Flags = Flags & (0xFF - FLAG_C);
1864 }
1865
1866 set_flag_z((BYTE)temp_word);
1867 set_flag_n((BYTE)temp_word);
1868
1869 if ((temp_word & 0x01) != 0)
1870 {
1871 Flags |= FLAG_C;
1872 }
1873 //Shifts temp_word one place right
1874 temp_word >>= 1;
1875 //Sets the negative flag
1876 if ((Flags & FLAG_N) != 0)
1877 {
1878 temp_word |= 0x80;
1879 }
1880 //Puts the shifted address back into memory
1881 Memory[address] = (BYTE)temp_word;
1882 }
1883 break;
1884
1885 case 0xB7: //SAR (abs,Y)
1886 address += Index_Registers[REGISTER_Y];
1887 HB = fetch();
1888 LB = fetch();
1889 address += (WORD)((WORD)HB << 8) + LB;
1890 if (address >= 0 && address < MEMORY_SIZE)
1891 {
1892 temp_word = Memory[address];
1893 if (temp_word >= 0x100)
1894 {
1895 //set carry flag
1896 Flags = Flags | FLAG_C;
1897 }
1898 else
1899 {
1900 //clear carry flag
1901 Flags = Flags & (0xFF - FLAG_C);
1902 }
1903
1904 set_flag_z((BYTE)temp_word);
1905 set_flag_n((BYTE)temp_word);
1906
1907 if ((temp_word & 0x01) != 0)
1908 {
1909 Flags |= FLAG_C;
1910 }
1911 //Shifts temp_word one place right
1912 temp_word >>= 1;
1913 //Sets the negative flag
1914 if ((Flags & FLAG_N) != 0)
1915 {
1916 temp_word |= 0x80;
1917 }
1918 //Puts the shifted address back into memory
1919 Memory[address] = (BYTE)temp_word;
1920 }
1921 break;
1922
1923 case 0xC7: //SAR (abs,X & Y)
1924 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1925 HB = fetch();
1926 LB = fetch();
1927 address += (WORD)((WORD)HB << 8) + LB;
1928 if (address >= 0 && address < MEMORY_SIZE)
1929 {
1930 temp_word = Memory[address];
1931 if (temp_word >= 0x100)
1932 {
1933 //set carry flag
1934 Flags = Flags | FLAG_C;
1935 }
1936 else
1937 {
1938 //clear carry flag
1939 Flags = Flags & (0xFF - FLAG_C);
1940 }
1941
1942 set_flag_z((BYTE)temp_word);
1943 set_flag_n((BYTE)temp_word);
1944
1945 if ((temp_word & 0x01) != 0)
1946 {
1947 Flags |= FLAG_C;
1948 }
1949 //Shifts temp_word one place right
1950 temp_word >>= 1;
1951 //Sets the negative flag
1952 if ((Flags & FLAG_N) != 0)
1953 {
1954 temp_word |= 0x80;
1955 }
1956 //Puts the shifted address back into memory
1957 Memory[address] = (BYTE)temp_word;
1958 }
1959 break;
1960
1961 /////////////////////////// COMA //////////////////////////////////
1962
1963 case 0xD8: // COMA
1964 temp_word = ~Registers[REGISTER_A];
1965 Registers[REGISTER_A] = (BYTE)temp_word;
1966 set_flag_n((BYTE)temp_word);
1967 set_flag_z((BYTE)temp_word);
1968 set_flag_c((WORD)temp_word);
1969 Registers[REGISTER_A] = temp_word;
1970 break;
1971
1972 /////////////////////////// COM //////////////////////////////////
1973
1974 case 0x98: // COM abs
1975 HB = fetch();
1976 LB = fetch();
1977 address += (WORD)((WORD)HB << 8) + LB;
1978 if (address >= 0 && address < MEMORY_SIZE) {
1979 temp_word = ~(WORD)Registers[REGISTER_A];
1980 Registers[REGISTER_A] = (BYTE)temp_word;
1981 set_flags_nz((BYTE)temp_word);
1982 set_flag_c((WORD)temp_word);
1983 Registers[REGISTER_A] = (BYTE)temp_word;
1984 }
1985 break;
1986
1987 case 0xA8: // COM abs,X
1988 address += Index_Registers[REGISTER_X];
1989 HB = fetch();
1990 LB = fetch();
1991 address += (WORD)((WORD)HB << 8) + LB;
1992 if (address >= 0 && address < MEMORY_SIZE) {
1993 temp_word = ~(WORD)Registers[REGISTER_A];
1994 Registers[REGISTER_A] = (BYTE)temp_word;
1995 set_flag_n((BYTE)temp_word);
1996 set_flag_z((BYTE)temp_word);
1997 set_flag_c((WORD)temp_word);
1998 Registers[REGISTER_A] = (BYTE)temp_word;
1999 }
2000 break;
2001
2002 case 0xB8: // COM abs,Y
2003 address += Index_Registers[REGISTER_Y];
2004 HB = fetch();
2005 LB = fetch();
2006 address += (WORD)((WORD)HB << 8) + LB;
2007 if (address >= 0 && address < MEMORY_SIZE) {
2008 temp_word = ~(WORD)Registers[REGISTER_A];
2009 Registers[REGISTER_A] = (BYTE)temp_word;
2010 set_flag_n((BYTE)temp_word);
2011 set_flag_z((BYTE)temp_word);
2012 set_flag_c((WORD)temp_word);
2013 Registers[REGISTER_A] = (BYTE)temp_word;
2014 }
2015 break;
2016
2017 case 0xC8: // COM abs,XY
2018 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8)
2019 + Index_Registers[REGISTER_X];
2020 HB = fetch();
2021 LB = fetch();
2022 address += (WORD)((WORD)HB << 8) + LB;
2023 if (address >= 0 && address < MEMORY_SIZE) {
2024 temp_word = ~(WORD)Registers[REGISTER_A];
2025 Registers[REGISTER_A] = (BYTE)temp_word;
2026 set_flag_n((BYTE)temp_word);
2027 set_flag_z((BYTE)temp_word);
2028 set_flag_c((WORD)temp_word);
2029 Registers[REGISTER_A] = (BYTE)temp_word;
2030 }
2031
2032 /////////////////////////// RLCA //////////////////////////////////
2033
2034 //RLCA - Rotate left through carry Memory or Accumulator - Flags N Z C
2035 case 0xD5: //RLCA
2036 saved_flags = Flags;
2037
2038 if ((Registers[REGISTER_A] & 0x80) == 0x80) {
2039 Flags = Flags | FLAG_C;
2040 }
2041 else {
2042 Flags = Flags & (0xFF - FLAG_C);
2043 }
2044 Registers[REGISTER_A] = (Registers[REGISTER_A] << 1) & 0xFE;
2045
2046 if ((saved_flags & FLAG_C) == FLAG_C) {
2047 Registers[REGISTER_A] = Registers[REGISTER_A] | 0x01;
2048 }
2049 set_flags_nz((BYTE)data);
2050 break;
2051
2052 /////////////////////////// RALA //////////////////////////////////
2053
2054 //RALA - Rotate left without carry Memory or Accumulator - Flags N Z//
2055 case 0xD9: //RALA
2056 temp_word = Registers[REGISTER_A];
2057 if ((temp_word & 0x80) == 0x80) {
2058 temp_word = (temp_word << 1) + 0x01;
2059 }
2060 else {
2061 temp_word = (temp_word << 1);
2062 }
2063 set_flags_nz((BYTE)temp_word);
2064 Registers[REGISTER_A] = (BYTE)temp_word;
2065 break;
2066
2067 /////////////////////////// ASLA //////////////////////////////////
2068
2069 //ASLA - Arithmetic shift left Memory or Accumulator - Flags N Z//
2070 case 0xD6: // ASLA
2071 saved_flags = Flags;
2072
2073 if ((Registers[REGISTER_A] & 0x80) == 0x80) {
2074 Flags = Flags | FLAG_C;
2075 }
2076 else {
2077 Flags = Flags & (0xFF - FLAG_C);
2078 }
2079 Registers[REGISTER_A] = (Registers[REGISTER_A] << 1) & 0xFE;
2080 set_flags_nz((BYTE)data);
2081 break;
2082
2083 /////////////////////////// SARA //////////////////////////////////
2084
2085 //SARA - Arithmetic shift right Memory or Accumulator - Flags C N Z//
2086 case 0xD7: // SARA
2087 if ((Registers[REGISTER_A] & 0x01) == 0x01) {
2088 Flags = Flags | FLAG_C;
2089 }
2090 else {
2091 Flags = Flags & (0xFF - FLAG_C);
2092 }
2093 Registers[REGISTER_A] = (Registers[REGISTER_A] >> 1) & 0x7F;
2094 if ((Flags & FLAG_N) == FLAG_N) {
2095 Registers[REGISTER_A] = Registers[REGISTER_A] | 0x80;
2096 }
2097 set_flags_nz((BYTE)data);
2098 set_flag_c((BYTE)data);
2099 break;
2100
2101 /////////////////////////// RCRA //////////////////////////////////
2102
2103 //RCRA - Rotate right through carry Memory or Accumulator - Flags N Z//
2104 case 0xD4: //RCRA
2105 saved_flags = Flags;
2106
2107 if ((Registers[REGISTER_A] & 0x80) == 0x80) {
2108 Flags = Flags | FLAG_C;
2109 }
2110 else {
2111 Flags = Flags & (0xFF - FLAG_C);
2112 }
2113 Registers[REGISTER_A] = (Registers[REGISTER_A] >> 1) & 0x7F;
2114
2115 if ((saved_flags & FLAG_C) == FLAG_C) {
2116 Registers[REGISTER_A] = Registers[REGISTER_A] | 0x80;
2117 }
2118 set_flags_nz((BYTE)Registers[REGISTER_A]);
2119 break;
2120
2121 /////////////////////////// RCR //////////////////////////////////
2122
2123 //RCR - Rotate right through carry Memory or Accumulator - Flags N Z C
2124 case 0x94: //RCR
2125 HB = fetch();
2126 LB = fetch();
2127 address += (WORD)((WORD)HB << 8) + LB;
2128 saved_flags = Flags;
2129 if (address >= 0 && address < MEMORY_SIZE) {
2130 if ((address & 0x01) == 0x01) {
2131 Flags = Flags | FLAG_C;
2132 }
2133 else {
2134 Flags = Flags & (0xFF - FLAG_C);
2135 }
2136 Memory[address] = (Memory[address] >> 1) & 0x7F;
2137
2138 if ((saved_flags & FLAG_C) == FLAG_C) {
2139 Memory[address] = Memory[address] | 0x80;
2140 }
2141 }
2142 set_flags_nz((BYTE)Memory[address]);
2143 break;
2144
2145 case 0xA4: //RCR
2146 address += Index_Registers[REGISTER_X];
2147 HB = fetch();
2148 LB = fetch();
2149 address += (WORD)((WORD)HB << 8) + LB;
2150 saved_flags = Flags;
2151 if (address >= 0 && address < MEMORY_SIZE) {
2152 if ((address & 0x01) == 0x01) {
2153 Flags = Flags | FLAG_C;
2154 }
2155 else {
2156 Flags = Flags & (0xFF - FLAG_C);
2157 }
2158 Memory[address] = (Memory[address] >> 1) & 0x7F;
2159
2160 if ((saved_flags & FLAG_C) == FLAG_C) {
2161 Memory[address] = Memory[address] | 0x80;
2162 }
2163 }
2164 set_flags_nz((BYTE)Memory[address]);
2165 break;
2166
2167 case 0xB4: //RCR
2168 address += Index_Registers[REGISTER_Y];
2169 HB = fetch();
2170 LB = fetch();
2171 address += (WORD)((WORD)HB << 8) + LB;
2172 saved_flags = Flags;
2173 if (address >= 0 && address < MEMORY_SIZE) {
2174 if ((address & 0x01) == 0x01) {
2175 Flags = Flags | FLAG_C;
2176 }
2177 else {
2178 Flags = Flags & (0xFF - FLAG_C);
2179 }
2180 Memory[address] = (Memory[address] >> 1) & 0x7F;
2181
2182 if ((saved_flags & FLAG_C) == FLAG_C) {
2183 Memory[address] = Memory[address] | 0x80;
2184 }
2185 }
2186 set_flags_nz((BYTE)Memory[address]);
2187 break;
2188
2189 case 0xC4: //RCR
2190 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8)
2191 + Index_Registers[REGISTER_X];
2192 HB = fetch();
2193 LB = fetch();
2194 address += (WORD)((WORD)HB << 8) + LB;
2195 saved_flags = Flags;
2196 if (address >= 0 && address < MEMORY_SIZE) {
2197 if ((address & 0x01) == 0x01) {
2198 Flags = Flags | FLAG_C;
2199 }
2200 else {
2201 Flags = Flags & (0xFF - FLAG_C);
2202 }
2203 Memory[address] = (Memory[address] >> 1) & 0x7F;
2204
2205 if ((saved_flags & FLAG_C) == FLAG_C) {
2206 Memory[address] = Memory[address] | 0x80;
2207 }
2208 }
2209 set_flags_nz((BYTE)Memory[address]);
2210 break;
2211
2212 /////////////////////////// RORA //////////////////////////////////
2213
2214 //RORA - Rotate right without carry Memory or Accumulator - Flags N Z//
2215 case 0xDA: //RORA
2216 temp_word = Registers[REGISTER_A];
2217 if ((temp_word & 0x01) == 0x01) {
2218 temp_word = (temp_word >> 1) + 0x80;
2219 }
2220 else {
2221 temp_word = (temp_word << 1);
2222 }
2223 set_flags_nz((BYTE)temp_word);
2224 Registers[REGISTER_A] = (BYTE)temp_word;
2225 break;
2226
2227 /////////////////////////// ROR //////////////////////////////////
2228
2229 //ROR - Rotate right without carry Memory or Accumulator - Flags N Z//
2230 case 0x9A: //ROR
2231 HB = fetch();
2232 LB = fetch();
2233 address += (WORD)((WORD)HB << 8) + LB;
2234 if (address >= 0 && address < MEMORY_SIZE) {
2235 temp_word = Memory[address];
2236 if ((temp_word & 0x01) == 0x01) {
2237 temp_word = (temp_word >> 1) + 0x80;
2238 }
2239 else {
2240 temp_word = (temp_word >> 1);
2241 }
2242 }
2243 set_flags_nz((BYTE)Memory[address]);
2244 Memory[address] = (BYTE)temp_word;
2245 break;
2246
2247 case 0xAA: //ROR
2248 address += Index_Registers[REGISTER_X];
2249 HB = fetch();
2250 LB = fetch();
2251 address += (WORD)((WORD)HB << 8) + LB;
2252 if (address >= 0 && address < MEMORY_SIZE) {
2253 temp_word = Memory[address];
2254 if ((temp_word & 0x01) == 0x01) {
2255 temp_word = (temp_word >> 1) + 0x80;
2256 }
2257 else {
2258 temp_word = (temp_word >> 1);
2259 }
2260 }
2261 set_flags_nz((BYTE)Memory[address]);
2262 Memory[address] = (BYTE)temp_word;
2263 break;
2264
2265 case 0xBA: //ROR
2266 address += Index_Registers[REGISTER_Y];
2267 HB = fetch();
2268 LB = fetch();
2269 address += (WORD)((WORD)HB << 8) + LB;
2270 saved_flags = Flags;
2271 if (address >= 0 && address < MEMORY_SIZE) {
2272 temp_word = Memory[address];
2273 if ((temp_word & 0x01) == 0x01) {
2274 temp_word = (temp_word >> 1) + 0x80;
2275 }
2276 else {
2277 temp_word = (temp_word >> 1);
2278 }
2279 }
2280 set_flags_nz((BYTE)Memory[address]);
2281 Memory[address] = (BYTE)temp_word;
2282 break;
2283
2284 case 0xCA: //ROR
2285 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2286 HB = fetch();
2287 LB = fetch();
2288 address += (WORD)((WORD)HB << 8) + LB;
2289 saved_flags = Flags;
2290 if (address >= 0 && address < MEMORY_SIZE) {
2291 temp_word = Memory[address];
2292 if ((temp_word & 0x01) == 0x01) {
2293 temp_word = (temp_word >> 1) + 0x80;
2294 }
2295 else {
2296 temp_word = (temp_word >> 1);
2297 }
2298 }
2299 set_flags_nz((BYTE)Memory[address]);
2300 Memory[address] = (BYTE)temp_word;
2301 break;
2302
2303 /////////////////////////// RAL //////////////////////////////////
2304
2305 //RAL - Rotate left without carry Memory or Accumulator - Flags N Z//
2306 case 0x99: //RAL
2307 HB = fetch();
2308 LB = fetch();
2309 address += (WORD)((WORD)HB << 8) + LB;
2310 if (address >= 0 && address < MEMORY_SIZE) {
2311 temp_word = Memory[address];
2312 if ((temp_word & 0x80) == 0x80) {
2313 temp_word = (temp_word << 1) + 0x01;
2314 }
2315 else {
2316 temp_word = (temp_word << 1);
2317 }
2318 }
2319 set_flags_nz((BYTE)Memory[address]);
2320 Memory[address] = (BYTE)temp_word;
2321 break;
2322
2323 case 0xA9: //RAL
2324 address += Index_Registers[REGISTER_X];
2325 HB = fetch();
2326 LB = fetch();
2327 address += (WORD)((WORD)HB << 8) + LB;
2328 if (address >= 0 && address < MEMORY_SIZE) {
2329 temp_word = Memory[address];
2330 if ((temp_word & 0x80) == 0x80) {
2331 temp_word = (temp_word << 1) + 0x01;
2332 }
2333 else {
2334 temp_word = (temp_word << 1);
2335 }
2336 }
2337 set_flags_nz((BYTE)Memory[address]);
2338 Memory[address] = (BYTE)temp_word;
2339 break;
2340
2341 case 0xB9: //RAL
2342 address += Index_Registers[REGISTER_Y];
2343 HB = fetch();
2344 LB = fetch();
2345 address += (WORD)((WORD)HB << 8) + LB;
2346 saved_flags = Flags;
2347 if (address >= 0 && address < MEMORY_SIZE) {
2348 temp_word = Memory[address];
2349 if ((temp_word & 0x80) == 0x80) {
2350 temp_word = (temp_word << 1) + 0x01;
2351 }
2352 else {
2353 temp_word = (temp_word << 1);
2354 }
2355 }
2356 set_flags_nz((BYTE)Memory[address]);
2357 Memory[address] = (BYTE)temp_word;
2358 break;
2359
2360 case 0xC9: //RAL
2361 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2362 HB = fetch();
2363 LB = fetch();
2364 address += (WORD)((WORD)HB << 8) + LB;
2365 saved_flags = Flags;
2366 if (address >= 0 && address < MEMORY_SIZE) {
2367 temp_word = Memory[address];
2368 if ((temp_word & 0x80) == 0x80) {
2369 temp_word = (temp_word << 1) + 0x01;
2370 }
2371 else {
2372 temp_word = (temp_word << 1);
2373 }
2374 }
2375 set_flags_nz((BYTE)Memory[address]);
2376 Memory[address] = (BYTE)temp_word;
2377 break;
2378}
2379}
2380
2381
2382////////////////////////////////////////////////////////////////////////////////
2383// GROUP TWO //
2384////////////////////////////////////////////////////////////////////////////////
2385
2386void Group_2_Move(BYTE opcode) {
2387 BYTE source = opcode >> 4; //top four bits point at one register....shift right to keep only top four
2388 BYTE destination = opcode & 0x0F;//takes bottom four bits
2389 int destReg = 0;
2390 int sourceReg = 0;
2391
2392 /////////////////////////// LD //////////////////////////////////
2393
2394 switch (source) { //COMBO OF DEST AND SOURCE GIVE REGISTERS ADDRESSES TO FOR MEMORY ADRESSER AT BOTTOM
2395 case 0x02://top four bits from op code
2396 sourceReg = REGISTER_A;
2397 break;
2398
2399 case 0x03:
2400 sourceReg = REGISTER_B;
2401 break;
2402
2403 case 0x04:
2404 sourceReg = REGISTER_C;
2405 break;
2406
2407 case 0x05:
2408 sourceReg = REGISTER_D;
2409 break;
2410
2411 case 0x06:
2412 sourceReg = REGISTER_E;
2413 break;
2414
2415 case 0x07:
2416 sourceReg = REGISTER_F;
2417 break;
2418 }
2419
2420 switch (destination) {
2421 case 0x0A:
2422 destReg = REGISTER_A;
2423 break;
2424
2425 case 0x0B:
2426 destReg = REGISTER_B;
2427 break;
2428
2429 case 0x0C:
2430 destReg = REGISTER_C;
2431 break;
2432
2433 case 0x0D:
2434 destReg = REGISTER_D;
2435 break;
2436
2437 case 0x0E:
2438 destReg = REGISTER_E;
2439 break;
2440
2441 case 0x0F:
2442 destReg = REGISTER_F;
2443 break;
2444 }
2445 Registers[destReg] = Registers[sourceReg];//code to assign sourcereg to dest reg
2446}
2447
2448
2449void execute(BYTE opcode)
2450{
2451 if (((opcode >= 0x2A) && (opcode <= 0x2F))
2452 || ((opcode >= 0x3A) && (opcode <= 0x3F))
2453 || ((opcode >= 0x4A) && (opcode <= 0x4F))
2454 || ((opcode >= 0x5A) && (opcode <= 0x5F))
2455 || ((opcode >= 0x6A) && (opcode <= 0x6F))
2456 || ((opcode >= 0x7A) && (opcode <= 0x7F)))
2457 {
2458 Group_2_Move(opcode);
2459 }
2460 else
2461 {
2462 Group_1(opcode);
2463 }
2464}
2465
2466void emulate()
2467{
2468 BYTE opcode;
2469 int sanity;
2470
2471 sanity = 0;
2472 ProgramCounter = 0;
2473 halt = false;
2474 memory_in_range = true;
2475
2476 printf(" A B C D E F X Y SP\n");
2477
2478 while ((!halt) && (memory_in_range)) {
2479 sanity++;
2480 if (sanity > 500) halt = true;
2481 printf("%04X ", ProgramCounter); // Print current address
2482 opcode = fetch();
2483 execute(opcode);
2484
2485 printf("%s ", opcode_mneumonics[opcode]); // Print current opcode
2486
2487 printf("%02X ", Registers[REGISTER_A]);
2488 printf("%02X ", Registers[REGISTER_B]);
2489 printf("%02X ", Registers[REGISTER_C]);
2490 printf("%02X ", Registers[REGISTER_D]);
2491 printf("%02X ", Registers[REGISTER_E]);
2492 printf("%02X ", Registers[REGISTER_F]);
2493 printf("%02X ", Index_Registers[REGISTER_X]);
2494 printf("%02X ", Index_Registers[REGISTER_Y]);
2495 printf("%04X ", StackPointer); // Print Stack Pointer
2496
2497 if ((Flags & FLAG_I) == FLAG_I)
2498 {
2499 printf("I=1 ");
2500 }
2501 else
2502 {
2503 printf("I=0 ");
2504 }
2505 if ((Flags & FLAG_V) == FLAG_V)
2506 {
2507 printf("V=1 ");
2508 }
2509 else
2510 {
2511 printf("V=0 ");
2512 }
2513 if ((Flags & FLAG_N) == FLAG_N)
2514 {
2515 printf("N=1 ");
2516 }
2517 else
2518 {
2519 printf("N=0 ");
2520 }
2521 if ((Flags & FLAG_Z) == FLAG_Z)
2522 {
2523 printf("Z=1 ");
2524 }
2525 else
2526 {
2527 printf("Z=0 ");
2528 }
2529 if ((Flags & FLAG_C) == FLAG_C)
2530 {
2531 printf("C=1 ");
2532 }
2533 else
2534 {
2535 printf("C=0 ");
2536 }
2537
2538 printf("\n"); // New line
2539 }
2540
2541 printf("\n"); // New line
2542}
2543
2544
2545////////////////////////////////////////////////////////////////////////////////
2546// Simulator/Emulator (End) //
2547////////////////////////////////////////////////////////////////////////////////
2548
2549
2550void initialise_filenames() {
2551 int i;
2552
2553 for (i = 0; i<MAX_FILENAME_SIZE; i++) {
2554 hex_file[i] = '\0';
2555 trc_file[i] = '\0';
2556 }
2557}
2558
2559
2560
2561
2562int find_dot_position(char *filename) {
2563 int dot_position;
2564 int i;
2565 char chr;
2566
2567 dot_position = 0;
2568 i = 0;
2569 chr = filename[i];
2570
2571 while (chr != '\0') {
2572 if (chr == '.') {
2573 dot_position = i;
2574 }
2575 i++;
2576 chr = filename[i];
2577 }
2578
2579 return (dot_position);
2580}
2581
2582
2583int find_end_position(char *filename) {
2584 int end_position;
2585 int i;
2586 char chr;
2587
2588 end_position = 0;
2589 i = 0;
2590 chr = filename[i];
2591
2592 while (chr != '\0') {
2593 end_position = i;
2594 i++;
2595 chr = filename[i];
2596 }
2597
2598 return (end_position);
2599}
2600
2601
2602bool file_exists(char *filename) {
2603 bool exists;
2604 FILE *ifp;
2605
2606 exists = false;
2607
2608 if ((ifp = fopen(filename, "r")) != NULL) {
2609 exists = true;
2610
2611 fclose(ifp);
2612 }
2613
2614 return (exists);
2615}
2616
2617
2618
2619void create_file(char *filename) {
2620 FILE *ofp;
2621
2622 if ((ofp = fopen(filename, "w")) != NULL) {
2623 fclose(ofp);
2624 }
2625}
2626
2627
2628
2629bool getline(FILE *fp, char *buffer) {
2630 bool rc;
2631 bool collect;
2632 char c;
2633 int i;
2634
2635 rc = false;
2636 collect = true;
2637
2638 i = 0;
2639 while (collect) {
2640 c = getc(fp);
2641
2642 switch (c) {
2643 case EOF:
2644 if (i > 0) {
2645 rc = true;
2646 }
2647 collect = false;
2648 break;
2649
2650 case '\n':
2651 if (i > 0) {
2652 rc = true;
2653 collect = false;
2654 buffer[i] = '\0';
2655 }
2656 break;
2657
2658 default:
2659 buffer[i] = c;
2660 i++;
2661 break;
2662 }
2663 }
2664
2665 return (rc);
2666}
2667
2668
2669
2670
2671
2672
2673void load_and_run(int args, _TCHAR** argv) {
2674 char chr;
2675 int ln;
2676 int dot_position;
2677 int end_position;
2678 long i;
2679 FILE *ifp;
2680 long address;
2681 long load_at;
2682 int code;
2683
2684 // Prompt for the .hex file
2685
2686 printf("\n");
2687 printf("Enter the hex filename (.hex): ");
2688
2689 if (args == 2) {
2690 ln = 0;
2691 chr = argv[1][ln];
2692 while (chr != '\0')
2693 {
2694 if (ln < MAX_FILENAME_SIZE)
2695 {
2696 hex_file[ln] = chr;
2697 trc_file[ln] = chr;
2698 ln++;
2699 }
2700 chr = argv[1][ln];
2701 }
2702 }
2703 else {
2704 ln = 0;
2705 chr = '\0';
2706 while (chr != '\n') {
2707 chr = getchar();
2708
2709 switch (chr) {
2710 case '\n':
2711 break;
2712 default:
2713 if (ln < MAX_FILENAME_SIZE) {
2714 hex_file[ln] = chr;
2715 trc_file[ln] = chr;
2716 ln++;
2717 }
2718 break;
2719 }
2720 }
2721
2722 }
2723 // Tidy up the file names
2724
2725 dot_position = find_dot_position(hex_file);
2726 if (dot_position == 0) {
2727 end_position = find_end_position(hex_file);
2728
2729 hex_file[end_position + 1] = '.';
2730 hex_file[end_position + 2] = 'h';
2731 hex_file[end_position + 3] = 'e';
2732 hex_file[end_position + 4] = 'x';
2733 hex_file[end_position + 5] = '\0';
2734 }
2735 else {
2736 hex_file[dot_position + 0] = '.';
2737 hex_file[dot_position + 1] = 'h';
2738 hex_file[dot_position + 2] = 'e';
2739 hex_file[dot_position + 3] = 'x';
2740 hex_file[dot_position + 4] = '\0';
2741 }
2742
2743 dot_position = find_dot_position(trc_file);
2744 if (dot_position == 0) {
2745 end_position = find_end_position(trc_file);
2746
2747 trc_file[end_position + 1] = '.';
2748 trc_file[end_position + 2] = 't';
2749 trc_file[end_position + 3] = 'r';
2750 trc_file[end_position + 4] = 'c';
2751 trc_file[end_position + 5] = '\0';
2752 }
2753 else {
2754 trc_file[dot_position + 0] = '.';
2755 trc_file[dot_position + 1] = 't';
2756 trc_file[dot_position + 2] = 'r';
2757 trc_file[dot_position + 3] = 'c';
2758 trc_file[dot_position + 4] = '\0';
2759 }
2760
2761 if (file_exists(hex_file)) {
2762 // Clear Registers and Memory
2763
2764 Registers[REGISTER_A] = 0;
2765 Registers[REGISTER_B] = 0;
2766 Registers[REGISTER_C] = 0;
2767 Registers[REGISTER_D] = 0;
2768 Registers[REGISTER_E] = 0;
2769 Registers[REGISTER_F] = 0;
2770 Index_Registers[REGISTER_X] = 0;
2771 Index_Registers[REGISTER_Y] = 0;
2772 Flags = 0;
2773 ProgramCounter = 0;
2774 StackPointer = 0;
2775
2776 for (i = 0; i<MEMORY_SIZE; i++) {
2777 Memory[i] = 0x00;
2778 }
2779
2780 // Load hex file
2781
2782 if ((ifp = fopen(hex_file, "r")) != NULL) {
2783 printf("Loading file...\n\n");
2784
2785 load_at = 0;
2786
2787 while (getline(ifp, InputBuffer)) {
2788 if (sscanf(InputBuffer, "L=%x", &address) == 1) {
2789 load_at = address;
2790 }
2791 else if (sscanf(InputBuffer, "%x", &code) == 1) {
2792 if ((load_at >= 0) && (load_at <= MEMORY_SIZE)) {
2793 Memory[load_at] = (BYTE)code;
2794 }
2795 load_at++;
2796 }
2797 else {
2798 printf("ERROR> Failed to load instruction: %s \n", InputBuffer);
2799 }
2800 }
2801
2802 fclose(ifp);
2803 }
2804
2805 // Emulate
2806
2807 emulate();
2808 }
2809 else {
2810 printf("\n");
2811 printf("ERROR> Input file %s does not exist!\n", hex_file);
2812 printf("\n");
2813 }
2814}
2815
2816void building(int args, _TCHAR** argv) {
2817 char buffer[1024];
2818 load_and_run(args, argv);
2819 sprintf(buffer, "0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X",
2820 Memory[TEST_ADDRESS_1],
2821 Memory[TEST_ADDRESS_2],
2822 Memory[TEST_ADDRESS_3],
2823 Memory[TEST_ADDRESS_4],
2824 Memory[TEST_ADDRESS_5],
2825 Memory[TEST_ADDRESS_6],
2826 Memory[TEST_ADDRESS_7],
2827 Memory[TEST_ADDRESS_8],
2828 Memory[TEST_ADDRESS_9],
2829 Memory[TEST_ADDRESS_10],
2830 Memory[TEST_ADDRESS_11],
2831 Memory[TEST_ADDRESS_12]
2832 );
2833 sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
2834}
2835
2836
2837
2838void test_and_mark() {
2839 char buffer[1024];
2840 bool testing_complete;
2841 int len = sizeof(SOCKADDR);
2842 char chr;
2843 int i;
2844 int j;
2845 bool end_of_program;
2846 long address;
2847 long load_at;
2848 int code;
2849 int mark;
2850 int passed;
2851
2852 printf("\n");
2853 printf("Automatic Testing and Marking\n");
2854 printf("\n");
2855
2856 testing_complete = false;
2857
2858 sprintf(buffer, "Test Student %s", STUDENT_NUMBER);
2859 sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
2860
2861 while (!testing_complete) {
2862 memset(buffer, '\0', sizeof(buffer));
2863
2864 if (recvfrom(sock, buffer, sizeof(buffer) - 1, 0, (SOCKADDR *)&client_addr, &len) != SOCKET_ERROR) {
2865 printf("Incoming Data: %s \n", buffer);
2866
2867 //if (strcmp(buffer, "Testing complete") == 1)
2868 if (sscanf(buffer, "Testing complete %d", &mark) == 1) {
2869 testing_complete = true;
2870 printf("Current mark = %d\n", mark);
2871
2872 }
2873 else if (sscanf(buffer, "Tests passed %d", &passed) == 1) {
2874 //testing_complete = true;
2875 printf("Passed = %d\n", passed);
2876
2877 }
2878 else if (strcmp(buffer, "Error") == 0) {
2879 printf("ERROR> Testing abnormally terminated\n");
2880 testing_complete = true;
2881 }
2882 else {
2883 // Clear Registers and Memory
2884
2885 Registers[REGISTER_A] = 0;
2886 Registers[REGISTER_B] = 0;
2887 Registers[REGISTER_C] = 0;
2888 Registers[REGISTER_D] = 0;
2889 Registers[REGISTER_E] = 0;
2890 Registers[REGISTER_F] = 0;
2891 Index_Registers[REGISTER_X] = 0;
2892 Index_Registers[REGISTER_Y] = 0;
2893 Flags = 0;
2894 ProgramCounter = 0;
2895 StackPointer = 0;
2896 for (i = 0; i<MEMORY_SIZE; i++) {
2897 Memory[i] = 0;
2898 }
2899
2900 // Load hex file
2901
2902 i = 0;
2903 j = 0;
2904 load_at = 0;
2905 end_of_program = false;
2906 FILE *ofp;
2907 fopen_s(&ofp, "branch.txt", "a");
2908
2909 while (!end_of_program) {
2910 chr = buffer[i];
2911 switch (chr) {
2912 case '\0':
2913 end_of_program = true;
2914
2915 case ',':
2916 if (sscanf(InputBuffer, "L=%x", &address) == 1) {
2917 load_at = address;
2918 }
2919 else if (sscanf(InputBuffer, "%x", &code) == 1) {
2920 if ((load_at >= 0) && (load_at <= MEMORY_SIZE)) {
2921 Memory[load_at] = (BYTE)code;
2922 fprintf(ofp, "%02X\n", (BYTE)code);
2923 }
2924 load_at++;
2925 }
2926 else {
2927 printf("ERROR> Failed to load instruction: %s \n", InputBuffer);
2928 }
2929 j = 0;
2930 break;
2931
2932 default:
2933 InputBuffer[j] = chr;
2934 j++;
2935 break;
2936 }
2937 i++;
2938 }
2939 fclose(ofp);
2940 // Emulate
2941
2942 if (load_at > 1) {
2943 emulate();
2944 // Send and store results
2945 sprintf(buffer, "%02X%02X %02X%02X %02X%02X %02X%02X %02X%02X %02X%02X",
2946 Memory[TEST_ADDRESS_1],
2947 Memory[TEST_ADDRESS_2],
2948 Memory[TEST_ADDRESS_3],
2949 Memory[TEST_ADDRESS_4],
2950 Memory[TEST_ADDRESS_5],
2951 Memory[TEST_ADDRESS_6],
2952 Memory[TEST_ADDRESS_7],
2953 Memory[TEST_ADDRESS_8],
2954 Memory[TEST_ADDRESS_9],
2955 Memory[TEST_ADDRESS_10],
2956 Memory[TEST_ADDRESS_11],
2957 Memory[TEST_ADDRESS_12]
2958 );
2959 sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
2960 }
2961 }
2962 }
2963 }
2964}
2965
2966
2967
2968int _tmain(int argc, _TCHAR* argv[])
2969{
2970 char chr;
2971 char dummy;
2972
2973 printf("\n");
2974 printf("Microprocessor Emulator\n");
2975 printf("UWE Computer and Network Systems Assignment 1\n");
2976 printf("\n");
2977
2978 initialise_filenames();
2979
2980 if (WSAStartup(MAKEWORD(2, 2), &data) != 0) return(0);
2981
2982 sock = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); // Here we create our socket, which will be a UDP socket (SOCK_DGRAM).
2983 if (!sock) {
2984 // Creation failed!
2985 }
2986
2987 memset(&server_addr, 0, sizeof(SOCKADDR_IN));
2988 server_addr.sin_family = AF_INET;
2989 server_addr.sin_addr.s_addr = inet_addr(IP_ADDRESS_SERVER);
2990 server_addr.sin_port = htons(PORT_SERVER);
2991
2992 memset(&client_addr, 0, sizeof(SOCKADDR_IN));
2993 client_addr.sin_family = AF_INET;
2994 client_addr.sin_addr.s_addr = inet_addr("127.0.0.1");
2995 client_addr.sin_port = htons(PORT_CLIENT);
2996
2997 chr = '\0';
2998 while ((chr != 'e') && (chr != 'E'))
2999 {
3000 printf("\n");
3001 printf("Please select option\n");
3002 printf("L - Load and run a hex file\n");
3003 printf("T - Have the server test and mark your emulator\n");
3004 printf("E - Exit\n");
3005 if (argc == 2) { building(argc, argv); exit(0); }
3006 printf("Enter option: ");
3007 chr = getchar();
3008 if (chr != 0x0A)
3009 {
3010 dummy = getchar(); // read in the <CR>
3011 }
3012 printf("\n");
3013
3014 switch (chr)
3015 {
3016 case 'L':
3017 case 'l':
3018 load_and_run(argc, argv);
3019 break;
3020
3021 case 'T':
3022 case 't':
3023 test_and_mark();
3024 break;
3025
3026 default:
3027 break;
3028 }
3029 }
3030
3031 closesocket(sock);
3032 WSACleanup();
3033
3034
3035 return 0;
3036}