ZS7MHzTU

1/*
2* Author: Jan Klimaszewski (17026846)
3* Created: 05/02/2019
4* Revised: 20/02/2019
5* Description: Program that emulates the Chimera-2016-I Processor
6* User advice: none
7*/
8
9#include "stdafx.h"
10#include <winsock2.h>
11
12#pragma comment(lib, "wsock32.lib")
13
14
15#define STUDENT_NUMBER    "17026846"
16
17#define IP_ADDRESS_SERVER "127.0.0.1"
18
19#define PORT_SERVER 0x1984 // We define a port that we are going to use.
20#define PORT_CLIENT 0x1985 // We define a port that we are going to use.
21
22#define WORD  unsigned short
23#define DWORD unsigned long
24#define BYTE  unsigned char
25
26#define MAX_FILENAME_SIZE 500
27#define MAX_BUFFER_SIZE   500
28
29SOCKADDR_IN server_addr;
30SOCKADDR_IN client_addr;
31
32SOCKET sock;  // This is our socket, it is the handle to the IO address to read/write packets
33
34WSADATA data;
35
36char InputBuffer[MAX_BUFFER_SIZE];
37
38char hex_file[MAX_BUFFER_SIZE];
39char trc_file[MAX_BUFFER_SIZE];
40
41//////////////////////////
42//   Registers          //
43//////////////////////////
44
45#define FLAG_Z  0x80
46#define FLAG_I  0x20
47#define FLAG_N  0x08
48#define FLAG_C  0x01
49#define REGISTER_M  5
50#define REGISTER_A  4
51#define REGISTER_H  3
52#define REGISTER_L  2
53#define REGISTER_C  1
54#define REGISTER_B  0
55#define REGISTER_X 0
56#define REGISTER_Y 1
57BYTE Index_Registers[2];
58
59BYTE Registers[6];
60BYTE Flags;
61WORD ProgramCounter;
62WORD StackPointer;
63
64
65////////////
66// Memory //
67////////////
68
69#define MEMORY_SIZE 65536
70
71BYTE Memory[MEMORY_SIZE];
72
73#define TEST_ADDRESS_1  0x01FA
74#define TEST_ADDRESS_2  0x01FB
75#define TEST_ADDRESS_3  0x01FC
76#define TEST_ADDRESS_4  0x01FD
77#define TEST_ADDRESS_5  0x01FE
78#define TEST_ADDRESS_6  0x01FF
79#define TEST_ADDRESS_7  0x0200
80#define TEST_ADDRESS_8  0x0201
81#define TEST_ADDRESS_9  0x0202
82#define TEST_ADDRESS_10  0x0203
83#define TEST_ADDRESS_11  0x0204
84#define TEST_ADDRESS_12  0x0205
85
86
87///////////////////////
88// Control variables //
89///////////////////////
90
91bool memory_in_range = true;
92bool halt = false;
93
94
95///////////////////////
96// Disassembly table //
97///////////////////////
98
99char opcode_mneumonics[][14] =
100{
101"ILLEGAL     ",
102"ILLEGAL     ",
103"SWI impl     ",
104"RTI impl     ",
105"STO abs      ",
106"STOX abs     ",
107"STOY abs     ",
108"JMPR abs     ",
109"CCC abs      ",
110"CCS abs      ",
111"CNE abs      ",
112"CEQ abs      ",
113"CMI abs      ",
114"CPL abs      ",
115"ILLEGAL     ",
116"STOS abs     ",
117
118"ILLEGAL     ",
119"ILLEGAL     ",
120"ILLEGAL     ",
121"ILLEGAL     ",
122"STO abs,X    ",
123"STOX abs,X   ",
124"STOY abs,X   ",
125"NOP impl     ",
126"WAI impl     ",
127"ILLEGAL     ",
128"ILLEGAL     ",
129"ILLEGAL     ",
130"ADI  #       ",
131"CPI  #       ",
132"ANI  #       ",
133"STOS abs,X   ",
134
135"LODS  #      ",
136"LDX  #       ",
137"LODY  #      ",
138"RT impl      ",
139"STO abs,Y    ",
140"STOX abs,Y   ",
141"STOY abs,Y   ",
142"MVR  #,B     ",
143"MVR  #,C     ",
144"MVR  #,L     ",
145"MVR  #,H     ",
146"TAY impl     ",
147"TYA impl     ",
148"MSA impl     ",
149"ILLEGAL     ",
150"STOS abs,Y   ",
151
152"LODS abs     ",
153"LDX abs      ",
154"LODY abs     ",
155"ILLEGAL     ",
156"STO abs,XY   ",
157"STOX abs,XY  ",
158"STOY abs,XY  ",
159"ILLEGAL     ",
160"JUMP abs     ",
161"JCC abs      ",
162"JCS abs      ",
163"JNE abs      ",
164"JEQ abs      ",
165"JMI abs      ",
166"JPL abs      ",
167"STOS abs,XY  ",
168
169"LODS abs,X   ",
170"LDX abs,X    ",
171"LODY abs,X   ",
172"LD  #        ",
173"STO zpg      ",
174"STOX zpg     ",
175"STOY zpg     ",
176"ILLEGAL     ",
177"ILLEGAL     ",
178"ILLEGAL     ",
179"DEX impl     ",
180"INX impl     ",
181"DEY impl     ",
182"INY impl     ",
183"ILLEGAL     ",
184"STOS zpg     ",
185
186"LODS abs,Y   ",
187"LDX abs,Y    ",
188"LODY abs,Y   ",
189"LD abs       ",
190"TEST abs     ",
191"INC abs      ",
192"DEC abs      ",
193"RR abs       ",
194"RCL abs      ",
195"SAL abs      ",
196"SHR abs      ",
197"COM abs      ",
198"NEG abs      ",
199"RAL abs      ",
200"ROR abs      ",
201"CLR abs      ",
202
203"LODS abs,XY  ",
204"LDX abs,XY   ",
205"LODY abs,XY  ",
206"LD abs,X     ",
207"TEST abs,X   ",
208"INC abs,X    ",
209"DEC abs,X    ",
210"RR abs,X     ",
211"RCL abs,X    ",
212"SAL abs,X    ",
213"SHR abs,X    ",
214"COM abs,X    ",
215"NEG abs,X    ",
216"RAL abs,X    ",
217"ROR abs,X    ",
218"CLR abs,X    ",
219
220"LODS zpg     ",
221"LDX zpg      ",
222"LODY zpg     ",
223"LD abs,Y     ",
224"TEST abs,Y   ",
225"INC abs,Y    ",
226"DEC abs,Y    ",
227"RR abs,Y     ",
228"RCL abs,Y    ",
229"SAL abs,Y    ",
230"SHR abs,Y    ",
231"COM abs,Y    ",
232"NEG abs,Y    ",
233"RAL abs,Y    ",
234"ROR abs,Y    ",
235"CLR abs,Y    ",
236
237"ILLEGAL     ",
238"ILLEGAL     ",
239"ILLEGAL     ",
240"LD abs,XY    ",
241"TEST abs,XY  ",
242"INC abs,XY   ",
243"DEC abs,XY   ",
244"RR abs,XY    ",
245"RCL abs,XY   ",
246"SAL abs,XY   ",
247"SHR abs,XY   ",
248"COM abs,XY   ",
249"NEG abs,XY   ",
250"RAL abs,XY   ",
251"ROR abs,XY   ",
252"CLR abs,XY   ",
253
254"ILLEGAL     ",
255"ILLEGAL     ",
256"ILLEGAL     ",
257"LD zpg       ",
258"TESTA A,A    ",
259"INCA A,A     ",
260"DECA A,A     ",
261"RRA A,A      ",
262"RCLA A,A     ",
263"SALA A,A     ",
264"SHRA A,A     ",
265"COMA A,A     ",
266"NEGA A,0     ",
267"RALA A,A     ",
268"RORA A,A     ",
269"CLRA A,0     ",
270
271"MV A,A       ",
272"MV B,A       ",
273"MV C,A       ",
274"MV L,A       ",
275"MV H,A       ",
276"MV M,A       ",
277"CLC impl     ",
278"SEC impl     ",
279"CLI impl     ",
280"SEI impl     ",
281"CMC impl     ",
282"ILLEGAL     ",
283"ILLEGAL     ",
284"ILLEGAL     ",
285"PUSH  ,A     ",
286"POP A,       ",
287
288"MV A,B       ",
289"MV B,B       ",
290"MV C,B       ",
291"MV L,B       ",
292"MV H,B       ",
293"MV M,B       ",
294"ADC A,B      ",
295"SBC A,B      ",
296"ADD A,B      ",
297"SUB A,B      ",
298"CMP A,B      ",
299"OR A,B       ",
300"AND A,B      ",
301"XOR A,B      ",
302"PUSH  ,s     ",
303"POP s,       ",
304
305"MV A,C       ",
306"MV B,C       ",
307"MV C,C       ",
308"MV L,C       ",
309"MV H,C       ",
310"MV M,C       ",
311"ADC A,C      ",
312"SBC A,C      ",
313"ADD A,C      ",
314"SUB A,C      ",
315"CMP A,C      ",
316"OR A,C       ",
317"AND A,C      ",
318"XOR A,C      ",
319"PUSH  ,B     ",
320"POP B,       ",
321
322"MV A,L       ",
323"MV B,L       ",
324"MV C,L       ",
325"MV L,L       ",
326"MV H,L       ",
327"MV M,L       ",
328"ADC A,L      ",
329"SBC A,L      ",
330"ADD A,L      ",
331"SUB A,L      ",
332"CMP A,L      ",
333"OR A,L       ",
334"AND A,L      ",
335"XOR A,L      ",
336"PUSH  ,C     ",
337"POP C,       ",
338
339"MV A,H       ",
340"MV B,H       ",
341"MV C,H       ",
342"MV L,H       ",
343"MV H,H       ",
344"MV M,H       ",
345"ADC A,H      ",
346"SBC A,H      ",
347"ADD A,H      ",
348"SUB A,H      ",
349"CMP A,H      ",
350"OR A,H       ",
351"AND A,H      ",
352"XOR A,H      ",
353"PUSH  ,L     ",
354"POP L,       ",
355
356"MV A,M       ",
357"MV B,M       ",
358"MV C,M       ",
359"MV L,M       ",
360"MV H,M       ",
361"MV -,-       ",
362"ADC A,M      ",
363"SBC A,M      ",
364"ADD A,M      ",
365"SUB A,M      ",
366"CMP A,M      ",
367"OR A,M       ",
368"AND A,M      ",
369"XOR A,M      ",
370"PUSH  ,H     ",
371"POP H,       ",
372
373};
374
375////////////////////////////////////////////////////////////////////////////////
376//                           Simulator/Emulator (Start)                       //
377////////////////////////////////////////////////////////////////////////////////
378BYTE fetch()
379{
380	BYTE byte = 0;
381
382	if ((ProgramCounter >= 0) && (ProgramCounter <= MEMORY_SIZE))
383	{
384		memory_in_range = true;
385		byte = Memory[ProgramCounter];
386		ProgramCounter++;
387	}
388	else
389	{
390		memory_in_range = false;
391	}
392	return byte;
393}
394
395void set_flag_n(BYTE inReg) {
396	BYTE reg;
397	reg = inReg;
398
399	if ((reg & 0x80) != 0) // msbit set
400	{
401		Flags = Flags | FLAG_N;
402	}
403	else
404	{
405		Flags = Flags & (0xFF - FLAG_N);
406	}
407}
408
409void set_flag_z(BYTE inReg) {
410
411	BYTE reg;
412	reg = inReg;
413
414	if (reg == 0) // msbit set
415	{
416		Flags = Flags | FLAG_Z;
417	}
418	else
419	{
420		Flags = Flags & (0xFF - FLAG_Z);
421	}
422}
423
424void Group_1(BYTE opcode) {
425	BYTE LB = 0;
426	BYTE HB = 0;
427	BYTE saved_flags = 0;
428	WORD address = 0;
429	WORD data = 0;
430	WORD temp_word = 0;
431
432	switch (opcode) {
433	case 0x43: //LD Immediate
434		data = fetch();
435		Registers[REGISTER_A] = data;
436		set_flag_n((BYTE)Registers[REGISTER_A]);
437		set_flag_z((BYTE)Registers[REGISTER_A]);
438		break;
439
440	case 0x53: //LD Absoulute
441		LB = fetch();
442		HB = fetch();
443		address += (WORD)((WORD)HB << 8) + LB;
444		if (address >= 0 && address < MEMORY_SIZE) {
445			Registers[REGISTER_A] = Memory[address];
446		}
447		set_flag_n((BYTE)Registers[REGISTER_A]);
448		set_flag_z((BYTE)Registers[REGISTER_A]);
449		break;
450
451	case 0x63://LD Absoulte X
452		address += Index_Registers[REGISTER_X];
453		LB = fetch();
454		HB = fetch();
455		address += (WORD)((WORD)HB << 8) + LB;
456		if (address >= 0 && address < MEMORY_SIZE) {
457			Registers[REGISTER_A] = Memory[address];
458		}
459		set_flag_n((BYTE)Registers[REGISTER_A]);
460		set_flag_z((BYTE)Registers[REGISTER_A]);
461		break;
462
463	case 0x73://LD Absoulte Y
464		address += Index_Registers[REGISTER_Y];
465		LB = fetch();
466		HB = fetch();
467		address += (WORD)((WORD)HB << 8) + LB;
468		if (address >= 0 && address < MEMORY_SIZE) {
469			Registers[REGISTER_A] = Memory[address];
470		}
471		set_flag_n((BYTE)Registers[REGISTER_A]);
472		set_flag_z((BYTE)Registers[REGISTER_A]);
473		break;
474
475	case 0x83://LD Absoulte XY
476		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
477		LB = fetch();
478		HB = fetch();
479		address += (WORD)((WORD)HB << 8) + LB;
480		if (address >= 0 && address < MEMORY_SIZE) {
481			Registers[REGISTER_A] = Memory[address];
482		}
483		set_flag_n((BYTE)Registers[REGISTER_A]);
484		set_flag_z((BYTE)Registers[REGISTER_A]);
485		break;
486
487	case 0x93://LD zpg
488		address += 0x0000 | (WORD)fetch();
489		if (address >= 0 && address < MEMORY_SIZE) {
490			Registers[REGISTER_A] = Memory[address];
491		}
492		set_flag_n((BYTE)Registers[REGISTER_A]);
493		set_flag_z((BYTE)Registers[REGISTER_A]);
494		break;
495
496	case 0x04://STO Absolute
497		LB = fetch();
498		HB = fetch();
499		address += (WORD)((WORD)HB << 8) + LB;
500		if (address >= 0 && address < MEMORY_SIZE) {
501			Memory[address] = Registers[REGISTER_A];
502		}
503		set_flag_n((BYTE)Memory[address]);
504		set_flag_z((BYTE)Memory[address]);
505		break;
506
507	case 0x14://STO Absolute X
508		address += Index_Registers[REGISTER_X];
509		LB = fetch();
510		HB = fetch();
511		address += (WORD)((WORD)HB << 8) + LB;
512		if (address >= 0 && address < MEMORY_SIZE) {
513			Memory[address] = Registers[REGISTER_A];
514		}
515		set_flag_n((BYTE)Memory[address]);
516		set_flag_z((BYTE)Memory[address]);
517		break;
518
519	case 0x24: //STO Absolute Y
520		address += Index_Registers[REGISTER_Y];
521		LB = fetch();
522		HB = fetch();
523		address += (WORD)((WORD)HB << 8) + LB;
524		if (address >= 0 && address < MEMORY_SIZE) {
525			Memory[address] = Registers[REGISTER_A];
526		}
527		set_flag_n((BYTE)Memory[address]);
528		set_flag_z((BYTE)Memory[address]);
529		break;
530
531	case 0x34://STO Absolute XY
532		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
533		LB = fetch();
534		HB = fetch();
535		address += (WORD)((WORD)HB << 8) + LB;
536		if (address >= 0 && address < MEMORY_SIZE) {
537			Memory[address] = Registers[REGISTER_A];
538		}
539		set_flag_n((BYTE)Memory[address]);
540		set_flag_z((BYTE)Memory[address]);
541		break;
542
543	case 0x44://STO zpg
544		address += 0x0000 | (WORD)fetch();
545		if (address >= 0 && address < MEMORY_SIZE) {
546			Memory[address] = Registers[REGISTER_A];
547		}
548		set_flag_n((BYTE)Memory[address]);
549		set_flag_z((BYTE)Memory[address]);
550		break;
551
552	case 0x21://LDX Immediate
553		data = fetch();
554		Index_Registers[REGISTER_X] = data;
555		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
556		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
557		break;
558
559	case 0x31: //LDX Absoulute
560		LB = fetch();
561		HB = fetch();
562		address += (WORD)((WORD)HB << 8) + LB;
563		if (address >= 0 && address < MEMORY_SIZE) {
564			Index_Registers[REGISTER_X] = Memory[address];
565		}
566		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
567		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
568		break;
569
570	case 0x41://LDX Absoulte X
571		address += Index_Registers[REGISTER_X];
572		LB = fetch();
573		HB = fetch();
574		address += (WORD)((WORD)HB << 8) + LB;
575		if (address >= 0 && address < MEMORY_SIZE) {
576			Index_Registers[REGISTER_X] = Memory[address];
577		}
578		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
579		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
580		break;
581
582	case 0x51://LDX Absoulte Y
583		address += Index_Registers[REGISTER_Y];
584		LB = fetch();
585		HB = fetch();
586		address += (WORD)((WORD)HB << 8) + LB;
587		if (address >= 0 && address < MEMORY_SIZE) {
588			Index_Registers[REGISTER_X] = Memory[address];
589		}
590		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
591		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
592		break;
593
594	case 0x61://LDX Absoulte XY
595		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
596		LB = fetch();
597		HB = fetch();
598		address += (WORD)((WORD)HB << 8) + LB;
599		if (address >= 0 && address < MEMORY_SIZE) {
600			Index_Registers[REGISTER_X] = Memory[address];
601		}
602		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
603		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
604		break;
605
606	case 0x71://LDX zpg
607		address += 0x0000 | (WORD)fetch();
608		if (address >= 0 && address < MEMORY_SIZE) {
609			Index_Registers[REGISTER_X] = Memory[address];
610		}
611		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
612		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
613		break;
614
615	case 0x22://LODY Immediate
616		data = fetch();
617		Index_Registers[REGISTER_Y] = data;
618		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
619		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
620		break;
621
622	case 0x32: //LODY Absoulute
623		LB = fetch();
624		HB = fetch();
625		address += (WORD)((WORD)HB << 8) + LB;
626		if (address >= 0 && address < MEMORY_SIZE) {
627			Index_Registers[REGISTER_Y] = Memory[address];
628		}
629		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
630		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
631		break;
632
633	case 0x42://LODY Absoulte X
634		address += Index_Registers[REGISTER_X];
635		LB = fetch();
636		HB = fetch();
637		address += (WORD)((WORD)HB << 8) + LB;
638		if (address >= 0 && address < MEMORY_SIZE) {
639			Index_Registers[REGISTER_Y] = Memory[address];
640		}
641		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
642		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
643		break;
644
645	case 0x52://LODY Absoulte Y
646		address += Index_Registers[REGISTER_Y];
647		LB = fetch();
648		HB = fetch();
649		address += (WORD)((WORD)HB << 8) + LB;
650		if (address >= 0 && address < MEMORY_SIZE) {
651			Index_Registers[REGISTER_Y] = Memory[address];
652		}
653		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
654		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
655		break;
656
657	case 0x62://LODY Absoulte XY
658		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
659		LB = fetch();
660		HB = fetch();
661		address += (WORD)((WORD)HB << 8) + LB;
662		if (address >= 0 && address < MEMORY_SIZE) {
663			Index_Registers[REGISTER_Y] = Memory[address];
664		}
665		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
666		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
667		break;
668
669	case 0x72://LODY zpg
670		address += 0x0000 | (WORD)fetch();
671		if (address >= 0 && address < MEMORY_SIZE) {
672			Index_Registers[REGISTER_Y] = Memory[address];
673		}
674		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
675		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
676		break;
677
678	case 0x27://Register B MVR Intermediate
679		data = fetch();
680		Registers[REGISTER_B] = data;
681		set_flag_n((BYTE)Registers[REGISTER_B]);
682		set_flag_z((BYTE)Registers[REGISTER_B]);
683		break;
684
685	case 0x28://Register C MVR Intermediate
686		data = fetch();
687		Registers[REGISTER_C] = data;
688		set_flag_n((BYTE)Registers[REGISTER_C]);
689		set_flag_z((BYTE)Registers[REGISTER_C]);
690		break;
691
692	case 0x29://Register L MVR Intermediate
693		data = fetch();
694		Registers[REGISTER_L] = data;
695		set_flag_n((BYTE)Registers[REGISTER_L]);
696		set_flag_z((BYTE)Registers[REGISTER_L]);
697		break;
698
699	case 0x2A://Register H MVR Intermediate
700		data = fetch();
701		Registers[REGISTER_H] = data;
702		set_flag_n((BYTE)Registers[REGISTER_H]);
703		set_flag_z((BYTE)Registers[REGISTER_H]);
704		break;
705
706	case 0x20://LODS Immediate
707		data = fetch();
708		StackPointer = data;
709		StackPointer += (WORD)fetch() << 8;
710		set_flag_n((BYTE)StackPointer);
711		set_flag_z((BYTE)StackPointer);
712		break;
713
714	case 0x30://LODS Absoulte
715		LB = fetch();
716		HB = fetch();
717		address += (WORD)((WORD)HB << 8) + LB;
718		if (address >= 0 && address < MEMORY_SIZE - 1) {
719			StackPointer = Memory[address];
720			StackPointer += (WORD)Memory[address + 1] << 8;
721		}
722		set_flag_n((BYTE)StackPointer);
723		set_flag_z((BYTE)StackPointer);
724		break;
725
726	case 0x40://LODS Absoulte X
727		address += Index_Registers[REGISTER_X];
728		LB = fetch();
729		HB = fetch();
730		address += (WORD)((WORD)HB << 8) + LB;
731		if (address >= 0 && address < MEMORY_SIZE - 1) {
732			StackPointer = Memory[address];
733			StackPointer += (WORD)Memory[address + 1] << 8;
734		}
735		set_flag_n((BYTE)StackPointer);
736		set_flag_z((BYTE)StackPointer);
737		break;
738
739	case 0x50://LODS Absoulte Y
740		address += Index_Registers[REGISTER_Y];
741		LB = fetch();
742		HB = fetch();
743		address += (WORD)((WORD)HB << 8) + LB;
744		if (address >= 0 && address < MEMORY_SIZE - 1) {
745			StackPointer = Memory[address];
746			StackPointer += (WORD)Memory[address + 1] << 8;
747		}
748		set_flag_n((BYTE)StackPointer);
749		set_flag_z((BYTE)StackPointer);
750		break;
751
752	case 0x60://LODS Absolute XY
753		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
754		LB = fetch();
755		HB = fetch();
756		address += (WORD)((WORD)HB << 8) + LB;
757		if (address >= 0 && address < MEMORY_SIZE - 1) {
758			StackPointer = Memory[address];
759			StackPointer += (WORD)Memory[address + 1] << 8;
760		}
761		set_flag_n((BYTE)StackPointer);
762		set_flag_z((BYTE)StackPointer);
763		break;
764
765	case 0x70://LODS zpg
766		address += 0x0000 | (WORD)fetch();
767		if (address >= 0 && address < MEMORY_SIZE - 1) {
768			StackPointer = Memory[address];
769			StackPointer += (WORD)Memory[address + 1] << 8;
770		}
771		set_flag_n((BYTE)StackPointer);
772		set_flag_z((BYTE)StackPointer);
773		break;
774
775	case 0x0F://STOS Absoulte
776		LB = fetch();
777		HB = fetch();
778		address += (WORD)((WORD)HB << 8) + LB;
779		if (address >= 0 && address < MEMORY_SIZE - 1) {
780			HB = (BYTE)(StackPointer >> 8);
781			LB = (BYTE)StackPointer;
782			Memory[address] = LB;
783			Memory[address + 1] = HB;
784		}
785		set_flag_n((BYTE)StackPointer);
786		set_flag_z((BYTE)StackPointer);
787		break;
788
789	case 0x1F://STOS Absoulte X
790		address += Index_Registers[REGISTER_X];
791		LB = fetch();
792		HB = fetch();
793		address += (WORD)((WORD)HB << 8) + LB;
794		if (address >= 0 && address < MEMORY_SIZE - 1) {
795			HB = (BYTE)(StackPointer >> 8);
796			LB = (BYTE)StackPointer;
797			Memory[address] = LB;
798			Memory[address + 1] = HB;
799
800		}
801		set_flag_n((BYTE)StackPointer);
802		set_flag_z((BYTE)StackPointer);
803		break;
804
805	case 0x2F://STOS Absoulte Y
806		address += Index_Registers[REGISTER_Y];
807		LB = fetch();
808		HB = fetch();
809		address += (WORD)((WORD)HB << 8) + LB;
810		if (address >= 0 && address < MEMORY_SIZE - 1) {
811			HB = (BYTE)(StackPointer >> 8);
812			LB = (BYTE)StackPointer;
813			Memory[address] = LB;
814			Memory[address + 1] = HB;
815		}
816		set_flag_n((BYTE)StackPointer);
817		set_flag_z((BYTE)StackPointer);
818		break;
819
820	case 0x3F://STOS Absolute XY
821		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
822		LB = fetch();
823		HB = fetch();
824		address += (WORD)((WORD)HB << 8) + LB;
825		if (address >= 0 && address < MEMORY_SIZE - 1) {
826			HB = (BYTE)(StackPointer >> 8);
827			LB = (BYTE)StackPointer;
828			Memory[address] = LB;
829			Memory[address + 1] = HB;
830		}
831		set_flag_n((BYTE)StackPointer);
832		set_flag_z((BYTE)StackPointer);
833		break;
834
835	case 0x4F://STOS zpg
836		address += 0x0000 | (WORD)fetch();
837		if (address >= 0 && address < MEMORY_SIZE - 1) {
838			HB = (BYTE)(StackPointer >> 8);
839			LB = (BYTE)StackPointer;
840			Memory[address] = LB;
841			Memory[address + 1] = HB;
842		}
843		set_flag_n((BYTE)StackPointer);
844		set_flag_z((BYTE)StackPointer);
845		break;
846
847	case 0x05://STOX Absolute
848		LB = fetch();
849		HB = fetch();
850		address += (WORD)((WORD)HB << 8) + LB;
851		if (address >= 0 && address < MEMORY_SIZE) {
852			Memory[address] = Index_Registers[REGISTER_X];
853		}
854		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
855		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
856		break;
857
858	case 0x15://STOX Absolute X
859		address += Index_Registers[REGISTER_X];
860		LB = fetch();
861		HB = fetch();
862		address += (WORD)((WORD)HB << 8) + LB;
863		if (address >= 0 && address < MEMORY_SIZE) {
864			Memory[address] = Index_Registers[REGISTER_X];
865		}
866		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
867		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
868		break;
869
870	case 0x25: //STOX Absolute Y
871		address += Index_Registers[REGISTER_Y];
872		LB = fetch();
873		HB = fetch();
874		address += (WORD)((WORD)HB << 8) + LB;
875		if (address >= 0 && address < MEMORY_SIZE) {
876			Memory[address] = Index_Registers[REGISTER_X];
877		}
878		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
879		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
880		break;
881
882	case 0x35://STOX Absolute XY
883		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
884		LB = fetch();
885		HB = fetch();
886		address += (WORD)((WORD)HB << 8) + LB;
887		if (address >= 0 && address < MEMORY_SIZE) {
888			Memory[address] = Index_Registers[REGISTER_X];
889		}
890		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
891		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
892		break;
893
894	case 0x45://STOX zpg
895		address += 0x0000 | (WORD)fetch();
896		if (address >= 0 && address < MEMORY_SIZE) {
897			Memory[address] = Index_Registers[REGISTER_X];
898		}
899		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
900		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
901		break;
902
903	case 0x06://STOY Absolute
904		LB = fetch();
905		HB = fetch();
906		address += (WORD)((WORD)HB << 8) + LB;
907		if (address >= 0 && address < MEMORY_SIZE) {
908			Memory[address] = Index_Registers[REGISTER_Y];
909		}
910		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
911		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
912		break;
913
914	case 0x16://STOY Absolute X
915		address += Index_Registers[REGISTER_X];
916		LB = fetch();
917		HB = fetch();
918		address += (WORD)((WORD)HB << 8) + LB;
919		if (address >= 0 && address < MEMORY_SIZE) {
920			Memory[address] = Index_Registers[REGISTER_Y];
921		}
922		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
923		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
924		break;
925
926	case 0x26: //STOY Absolute Y
927		address += Index_Registers[REGISTER_Y];
928		LB = fetch();
929		HB = fetch();
930		address += (WORD)((WORD)HB << 8) + LB;
931		if (address >= 0 && address < MEMORY_SIZE) {
932			Memory[address] = Index_Registers[REGISTER_Y];
933		}
934		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
935		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
936		break;
937
938	case 0x36://STOY Absolute XY
939		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
940		LB = fetch();
941		HB = fetch();
942		address += (WORD)((WORD)HB << 8) + LB;
943		if (address >= 0 && address < MEMORY_SIZE) {
944			Memory[address] = Index_Registers[REGISTER_Y];
945		}
946		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
947		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
948		break;
949
950	case 0x46://STOY zpg
951		address += 0x0000 | (WORD)fetch();
952		if (address >= 0 && address < MEMORY_SIZE) {
953			Memory[address] = Index_Registers[REGISTER_Y];
954		}
955		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
956		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
957		break;
958
959	case 0xB6://ADC A,B
960		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_B];
961		if ((Flags & FLAG_C) != 0)
962		{
963			temp_word++;
964		}
965		if (temp_word >= 0x100)
966		{
967			Flags = Flags | FLAG_C;
968		}
969		else
970		{
971			Flags = Flags & (0xFF - FLAG_C);
972		}
973		set_flag_n((BYTE)temp_word);
974		set_flag_z((BYTE)temp_word);
975		Registers[REGISTER_A] = (BYTE)temp_word;
976		break;
977
978	case 0xC6://ADC A,C
979		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_C];
980		if ((Flags & FLAG_C) != 0)
981		{
982			temp_word++;
983		}
984		if (temp_word >= 0x100)
985		{
986			Flags = Flags | FLAG_C;
987		}
988		else
989		{
990			Flags = Flags & (0xFF - FLAG_C);
991		}
992		set_flag_n((BYTE)temp_word);
993		set_flag_z((BYTE)temp_word);
994		Registers[REGISTER_A] = (BYTE)temp_word;
995		break;
996
997	case 0xD6://ADC A,L
998		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_L];
999		if ((Flags & FLAG_C) != 0)
1000		{
1001			temp_word++;
1002		}
1003		if (temp_word >= 0x100)
1004		{
1005			Flags = Flags | FLAG_C;
1006		}
1007		else
1008		{
1009			Flags = Flags & (0xFF - FLAG_C);
1010		}
1011		set_flag_n((BYTE)temp_word);
1012		set_flag_z((BYTE)temp_word);
1013		Registers[REGISTER_A] = (BYTE)temp_word;
1014		break;
1015
1016	case 0xE6://ADC A,H
1017		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_H];
1018		if ((Flags & FLAG_C) != 0)
1019		{
1020			temp_word++;
1021		}
1022		if (temp_word >= 0x100)
1023		{
1024			Flags = Flags | FLAG_C;
1025		}
1026		else
1027		{
1028			Flags = Flags & (0xFF - FLAG_C);
1029		}
1030		set_flag_n((BYTE)temp_word);
1031		set_flag_z((BYTE)temp_word);
1032		Registers[REGISTER_A] = (BYTE)temp_word;
1033		break;
1034
1035	case 0xF6://ADC A,M
1036		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_M];
1037		if ((Flags & FLAG_C) != 0)
1038		{
1039			temp_word++;
1040		}
1041		if (temp_word >= 0x100)
1042		{
1043			Flags = Flags | FLAG_C;
1044		}
1045		else
1046		{
1047			Flags = Flags & (0xFF - FLAG_C);
1048		}
1049		set_flag_n((BYTE)temp_word);
1050		set_flag_z((BYTE)temp_word);
1051		Registers[REGISTER_A] = (BYTE)temp_word;
1052		break;
1053
1054	case 0xB8://ADD A,B
1055		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_B];
1056		if (temp_word >= 0x100)
1057		{
1058			Flags = Flags | FLAG_C;
1059		}
1060		else
1061		{
1062			Flags = Flags & (0xFF - FLAG_C);
1063		}
1064		set_flag_n((BYTE)temp_word);
1065		set_flag_z((BYTE)temp_word);
1066		Registers[REGISTER_A] = (BYTE)temp_word;
1067		break;
1068
1069	case 0xC8://ADD A,C
1070		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_C];
1071		if (temp_word >= 0x100)
1072		{
1073			Flags = Flags | FLAG_C;
1074		}
1075		else
1076		{
1077			Flags = Flags & (0xFF - FLAG_C);
1078		}
1079		set_flag_n((BYTE)temp_word);
1080		set_flag_z((BYTE)temp_word);
1081		Registers[REGISTER_A] = (BYTE)temp_word;
1082		break;
1083
1084	case 0xD8://ADD A,L
1085		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_L];
1086		if (temp_word >= 0x100)
1087		{
1088			Flags = Flags | FLAG_C;
1089		}
1090		else
1091		{
1092			Flags = Flags & (0xFF - FLAG_C);
1093		}
1094		set_flag_n((BYTE)temp_word);
1095		set_flag_z((BYTE)temp_word);
1096		Registers[REGISTER_A] = (BYTE)temp_word;
1097		break;
1098
1099	case 0xE8://ADD A,H
1100		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_H];
1101		if (temp_word >= 0x100)
1102		{
1103			Flags = Flags | FLAG_C;
1104		}
1105		else
1106		{
1107			Flags = Flags & (0xFF - FLAG_C);
1108		}
1109		set_flag_n((BYTE)temp_word);
1110		set_flag_z((BYTE)temp_word);
1111		Registers[REGISTER_A] = (BYTE)temp_word;
1112		break;
1113
1114	case 0xF8://ADD A,M
1115		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_M];
1116		if (temp_word >= 0x100)
1117		{
1118			Flags = Flags | FLAG_C;
1119		}
1120		else
1121		{
1122			Flags = Flags & (0xFF - FLAG_C);
1123		}
1124		set_flag_n((BYTE)temp_word);
1125		set_flag_z((BYTE)temp_word);
1126		Registers[REGISTER_A] = (BYTE)temp_word;
1127		break;
1128
1129	case 0xBA://CMP A,B
1130		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_B];
1131		if (temp_word >= 0x100) {
1132			Flags = Flags | FLAG_C; // Set carry flag
1133		}
1134		else {
1135			Flags = Flags & (0xFF - FLAG_C); // Clear carry flag
1136		}
1137		set_flag_n((BYTE)temp_word);
1138		set_flag_z((BYTE)temp_word);
1139		break;
1140
1141	case 0xCA://CMP A,C
1142		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_C];
1143		if (temp_word >= 0x100) {
1144			Flags = Flags | FLAG_C; // Set carry flag
1145		}
1146		else {
1147			Flags = Flags & (0xFF - FLAG_C); // Clear carry flag
1148		}
1149		set_flag_n((BYTE)temp_word);
1150		set_flag_z((BYTE)temp_word);
1151		break;
1152
1153	case 0xDA://CMP A,L
1154		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_L];
1155		if (temp_word >= 0x100) {
1156			Flags = Flags | FLAG_C; // Set carry flag
1157		}
1158		else {
1159			Flags = Flags & (0xFF - FLAG_C); // Clear carry flag
1160		}
1161		set_flag_n((BYTE)temp_word);
1162		set_flag_z((BYTE)temp_word);
1163		break;
1164
1165	case 0xEA://CMP A,H
1166		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_H];
1167		if (temp_word >= 0x100)
1168		{
1169			Flags = Flags | FLAG_C; // Set carry flag
1170		}
1171		else
1172		{
1173			Flags = Flags & (0xFF - FLAG_C); // Clear carry flag
1174		}
1175		set_flag_n((BYTE)temp_word);
1176		set_flag_z((BYTE)temp_word);
1177		break;
1178
1179	case 0xFA://CMP A,M
1180		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_M];
1181		if (temp_word >= 0x100)
1182		{
1183			Flags = Flags | FLAG_C; // Set carry flag
1184		}
1185		else
1186		{
1187			Flags = Flags & (0xFF - FLAG_C); // Clear carry flag
1188		}
1189		set_flag_n((BYTE)temp_word);
1190		set_flag_z((BYTE)temp_word);
1191		break;
1192
1193	case 0x2D://MSA
1194		Registers[REGISTER_A] = Flags;
1195		break;
1196
1197	case 0x2B://TAY
1198		Index_Registers[REGISTER_Y] = Registers[REGISTER_A];
1199		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
1200		break;
1201
1202	case 0x2C://TYA
1203		Registers[REGISTER_A] = Index_Registers[REGISTER_Y];
1204		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
1205		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
1206		break;
1207
1208	case 0xA6://CLC
1209		Flags = Flags & (0xFF - FLAG_C);
1210		break;
1211
1212	case 0xA7://SEC
1213		Flags = Flags | FLAG_C;
1214		break;
1215
1216	case 0xA8://CLI
1217		Flags = Flags & (0xFF - FLAG_I);
1218		break;
1219
1220	case 0xA9://SEI
1221		Flags = Flags | FLAG_I;
1222		break;
1223
1224	case 0xAA://CMC
1225		Flags = Flags ^ FLAG_C;
1226		break;
1227
1228	case 0xAE://PUSH REGISTER A
1229		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1230			StackPointer--;
1231			Memory[StackPointer] = Registers[REGISTER_A];
1232		}
1233		break;
1234
1235	case 0xBE://PUSH FLAGS
1236		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1237			StackPointer--;
1238			Memory[StackPointer] = Flags;
1239		}
1240		break;
1241
1242	case 0xCE://PUSH REGISTER B
1243		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1244			StackPointer--;
1245			Memory[StackPointer] = Registers[REGISTER_B];
1246		}
1247		break;
1248
1249	case 0xDE://PUSH REGISTER C
1250		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1251			StackPointer--;
1252			Memory[StackPointer] = Registers[REGISTER_C];
1253		}
1254		break;
1255
1256	case 0xEE://PUSH REGISTER L
1257		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1258			StackPointer--;
1259			Memory[StackPointer] = Registers[REGISTER_L];
1260		}
1261		break;
1262
1263	case 0xFE://PUSH REGISTER H
1264		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1265			StackPointer--;
1266			Memory[StackPointer] = Registers[REGISTER_H];
1267		}
1268		break;
1269
1270	case 0xAF://POP REGISTER A
1271		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1272			Registers[REGISTER_A] = Memory[StackPointer];
1273			StackPointer++;
1274		}
1275		break;
1276
1277	case 0xBF://POP FLAGS
1278		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1279			Flags = Memory[StackPointer];
1280			StackPointer++;
1281		}
1282		break;
1283
1284	case 0xCF://POP REGISTER B
1285		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1286			Registers[REGISTER_B] = Memory[StackPointer];
1287			StackPointer++;
1288		}
1289		break;
1290
1291	case 0xDF://POP REGISTER C
1292		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1293			Registers[REGISTER_C] = Memory[StackPointer];
1294			StackPointer++;
1295		}
1296		break;
1297
1298	case 0xEF://POP REGISTER L
1299		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1300			Registers[REGISTER_L] = Memory[StackPointer];
1301			StackPointer++;
1302		}
1303		break;
1304
1305	case 0xFF://POP REGISTER H
1306		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1307			Registers[REGISTER_H] = Memory[StackPointer];
1308			StackPointer++;
1309		}
1310		break;
1311
1312	case 0x38: //JUMP abs
1313		LB = fetch();
1314		HB = fetch();
1315		address = ((WORD)HB << 8) + (WORD)LB;
1316		ProgramCounter = address;
1317		break;
1318
1319	case 0x07://JMPR abs
1320		HB = fetch();
1321		LB = fetch();
1322		if ((StackPointer >= 2) && (StackPointer < MEMORY_SIZE)) {
1323			StackPointer--;
1324			Memory[StackPointer] = (BYTE)((ProgramCounter >> 8) & 0xFF);
1325			StackPointer--;
1326			Memory[StackPointer] = (BYTE)(ProgramCounter & 0xFF);
1327			ProgramCounter = address;
1328		}
1329		break;
1330
1331	case 0x23: //RT impl
1332		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 2)) {
1333			LB = Memory[StackPointer];
1334			StackPointer++;
1335			HB = Memory[StackPointer];
1336			StackPointer++;
1337			ProgramCounter = ((WORD)HB << 8) + (WORD)LB;
1338		}
1339		break;
1340
1341	case 0x39://JCC
1342		LB = fetch();
1343		HB = fetch();
1344		address = ((WORD)HB << 8) + (WORD)LB;
1345		if ((Flags & FLAG_C) == 0)
1346		{
1347			ProgramCounter = address;
1348		}
1349		break;
1350
1351	case 0x3A://JCS
1352		LB = fetch();
1353		HB = fetch();
1354		address = ((WORD)HB << 8) + (WORD)LB;
1355		if ((Flags & FLAG_C) == FLAG_C)
1356		{
1357			ProgramCounter = address;
1358		}
1359		break;
1360
1361	case 0x3B://JNE abs
1362		LB = fetch();
1363		HB = fetch();
1364		address = ((WORD)HB << 8) + (WORD)LB;
1365		if ((Flags & FLAG_Z) == 0)
1366		{
1367			ProgramCounter = address;
1368		}
1369		break;
1370
1371	case 0x3C://JEQ
1372		LB = fetch();
1373		HB = fetch();
1374		address = ((WORD)HB << 8) + (WORD)LB;
1375		if ((Flags & FLAG_Z) == FLAG_Z)
1376		{
1377			ProgramCounter = address;
1378		}
1379		break;
1380
1381	case 0x3D://JMI abs
1382		LB = fetch();
1383		HB = fetch();
1384		address = ((WORD)HB << 8) + (WORD)LB;
1385		if ((Flags & FLAG_N) == FLAG_N)
1386		{
1387			ProgramCounter = address;
1388		}
1389		break;
1390
1391	case 0x3E://JPL abs
1392		LB = fetch();
1393		HB = fetch();
1394		address = ((WORD)HB << 8) + (WORD)LB;
1395		if ((Flags & FLAG_N) == 0)
1396		{
1397			ProgramCounter = address;
1398		}
1399		break;
1400
1401		//////////////// CCC
1402	case 0x08: // CCC
1403		LB = fetch();
1404		HB = fetch();
1405		address = ((WORD)HB << 8) + (WORD)LB;
1406		if ((Flags & FLAG_C) == 0) {
1407			Memory[StackPointer] = ProgramCounter;
1408			StackPointer--;
1409			ProgramCounter = address;
1410		}
1411		break;
1412
1413
1414		/////////////// CCS
1415	case 0x09: // CCS
1416		LB = fetch();
1417		HB = fetch();
1418		address = ((WORD)HB << 8) + (WORD)LB;
1419
1420		if ((Flags & FLAG_C) != 0) {
1421			Memory[StackPointer] = ProgramCounter;
1422			StackPointer--;
1423			ProgramCounter = address;
1424		}
1425		break;
1426
1427		////////////// CNE
1428	case 0x0A: // CNE
1429		LB = fetch();
1430		HB = fetch();
1431		address = ((WORD)HB << 8) + (WORD)LB;
1432
1433		if ((Flags & FLAG_Z) == 0) {
1434			Memory[StackPointer] = ProgramCounter;
1435			StackPointer--;
1436			ProgramCounter = address;
1437		}
1438		break;
1439
1440		/////////////// CEQ
1441	case 0x0B: // CEQ
1442		LB = fetch();
1443		HB = fetch();
1444		address = ((WORD)HB << 8) + (WORD)LB;
1445
1446		if ((Flags & FLAG_Z) != 0) {
1447			Memory[StackPointer] = ProgramCounter;
1448			StackPointer--;
1449			ProgramCounter = address;
1450		}
1451		break;
1452
1453		///////////////// CMI
1454	case 0x0C: // CMI
1455		LB = fetch();
1456		HB = fetch();
1457		address = ((WORD)HB << 8) + (WORD)LB;
1458
1459		if ((Flags & FLAG_N) != 0) {
1460			Memory[StackPointer] = ProgramCounter;
1461			StackPointer--;
1462			ProgramCounter = address;
1463		}
1464		break;
1465
1466		///////////////// CPL
1467	case 0x0D: // CPL
1468		LB = fetch();
1469		HB = fetch();
1470		address = ((WORD)HB << 8) + (WORD)LB;
1471
1472		if ((Flags & FLAG_N) == 0) {
1473			Memory[StackPointer] = ProgramCounter;
1474			StackPointer--;
1475			ProgramCounter = address;
1476		}
1477		break;
1478
1479	case 0x95: //INCA
1480		++Registers[REGISTER_A];
1481		set_flag_n(Registers[REGISTER_A]);
1482		set_flag_z(Registers[REGISTER_A]);
1483		break;
1484
1485	case 0xBC: // AND Register A,B
1486		temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_B];
1487		set_flag_n((BYTE)temp_word);
1488		set_flag_z((BYTE)temp_word);
1489		Registers[REGISTER_A] = (BYTE)temp_word;
1490		break;
1491
1492	case 0xCC: // AND Register A,C
1493		temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_C];
1494		set_flag_n((BYTE)temp_word);
1495		set_flag_z((BYTE)temp_word);
1496		Registers[REGISTER_A] = (BYTE)temp_word;
1497		break;
1498
1499	case 0xDC: // AND Register A,L
1500		temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_L];
1501		set_flag_n((BYTE)temp_word);
1502		set_flag_z((BYTE)temp_word);
1503		Registers[REGISTER_A] = (BYTE)temp_word;
1504		break;
1505
1506	case 0xEC: // AND Register A,H
1507		temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_H];
1508		set_flag_n((BYTE)temp_word);
1509		set_flag_z((BYTE)temp_word);
1510		Registers[REGISTER_A] = (BYTE)temp_word;
1511		break;
1512
1513	case 0xFC: // AND Register A,M
1514		temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_M];
1515		set_flag_n((BYTE)temp_word);
1516		set_flag_z((BYTE)temp_word);
1517		Registers[REGISTER_A] = (BYTE)temp_word;
1518		break;
1519
1520	case 0x9F: //CLRA
1521		Registers[REGISTER_A] = 0;
1522		Flags = Flags | FLAG_Z;
1523		Flags = Flags & (0xFF - FLAG_N);
1524		Flags = Flags & (0xFF - FLAG_C);
1525		break;
1526
1527	case 0x55: // INC abs
1528		LB = fetch();
1529		HB = fetch();
1530		address += (WORD)((WORD)HB << 8) + LB;
1531		++Memory[address];
1532		set_flag_n(Memory[address]);
1533		set_flag_z(Memory[address]);
1534		break;
1535
1536	case 0x65: // INC abs X
1537		address += Index_Registers[REGISTER_X];
1538		LB = fetch();
1539		HB = fetch();
1540		address += (WORD)((WORD)HB << 8) + LB;
1541		if (address >= 0 && address < MEMORY_SIZE)
1542		{
1543			++Memory[address];
1544		}
1545		set_flag_n(Memory[address]);
1546		set_flag_z(Memory[address]);
1547		break;
1548
1549	case 0x75: // INC abs Y
1550		address += Index_Registers[REGISTER_Y];
1551		LB = fetch();
1552		HB = fetch();
1553		address += (WORD)((WORD)HB << 8) + LB;
1554		if (address >= 0 && address < MEMORY_SIZE)
1555		{
1556			++Memory[address];
1557		}
1558		set_flag_n(Memory[address]);
1559		set_flag_z(Memory[address]);
1560		break;
1561
1562	case 0x85: // INC abs XY
1563		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1564		LB = fetch();
1565		HB = fetch();
1566		address += (WORD)((WORD)HB << 8) + LB;
1567		if (address >= 0 && address < MEMORY_SIZE)
1568		{
1569			++Memory[address];
1570		}
1571		set_flag_n(Memory[address]);
1572		set_flag_z(Memory[address]);
1573		break;
1574
1575	case 0x5F: // CLR abs
1576		LB = fetch();
1577		HB = fetch();
1578		address += (WORD)((WORD)HB << 8) + LB;
1579		Memory[address] = 0;
1580		Flags = Flags | FLAG_Z;
1581		Flags = Flags & (0xFF - FLAG_N);
1582		Flags = Flags & (0xFF - FLAG_C);
1583		break;
1584
1585	case 0x6F: // CLR abs X
1586		address += Index_Registers[REGISTER_X];
1587		LB = fetch();
1588		HB = fetch();
1589		address += (WORD)((WORD)HB << 8) + LB;
1590		Memory[address] = 0;
1591		Flags = Flags | FLAG_Z;
1592		Flags = Flags & (0xFF - FLAG_N);
1593		Flags = Flags & (0xFF - FLAG_C);
1594		break;
1595
1596	case 0x7F: // CLR abs Y
1597		address += Index_Registers[REGISTER_Y];
1598		LB = fetch();
1599		HB = fetch();
1600		address += (WORD)((WORD)HB << 8) + LB;
1601		Memory[address] = 0;
1602		Flags = Flags | FLAG_Z;
1603		Flags = Flags & (0xFF - FLAG_N);
1604		Flags = Flags & (0xFF - FLAG_C);
1605		break;
1606
1607	case 0x8F: // CLR abs XY
1608		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1609		LB = fetch();
1610		HB = fetch();
1611		address += (WORD)((WORD)HB << 8) + LB;
1612		Memory[address] = 0;
1613		Flags = Flags | FLAG_Z;
1614		Flags = Flags & (0xFF - FLAG_N);
1615		Flags = Flags & (0xFF - FLAG_C);
1616		break;
1617
1618	case 0x4A: // DEX imply
1619		Index_Registers[REGISTER_X]--;
1620		set_flag_z(Index_Registers[REGISTER_X]);
1621		break;
1622
1623	case 0x4B: //INX impl
1624		++Index_Registers[REGISTER_X];
1625		set_flag_z(Index_Registers[REGISTER_X]);
1626		break;
1627
1628	case 0x4C: //DEY impl
1629		Index_Registers[REGISTER_Y]--;
1630		set_flag_z(Index_Registers[REGISTER_Y]);
1631		break;
1632
1633	case 0x4D: //INY impl
1634		++Index_Registers[REGISTER_Y];
1635		set_flag_z(Index_Registers[REGISTER_Y]);
1636		break;
1637
1638	case 0xB7: //SBC A,B
1639		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_B];
1640		if ((Flags & FLAG_C) != 0)
1641		{
1642			temp_word--;
1643		}
1644		if (temp_word >= 0x100)
1645		{
1646			Flags = Flags | FLAG_C;
1647		}
1648		else
1649		{
1650			Flags = Flags & (0xFF - FLAG_C);
1651		}
1652		set_flag_n((BYTE)temp_word);
1653		set_flag_z((BYTE)temp_word);
1654		Registers[REGISTER_A] = (BYTE)temp_word;
1655		break;
1656
1657	case 0xC7: //SBC A,C
1658		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_C];
1659		if ((Flags & FLAG_C) != 0)
1660		{
1661			temp_word--;
1662		}
1663		if (temp_word >= 0x100)
1664		{
1665			Flags = Flags | FLAG_C;
1666		}
1667		else
1668		{
1669			Flags = Flags & (0xFF - FLAG_C);
1670		}
1671		set_flag_n((BYTE)temp_word);
1672		set_flag_z((BYTE)temp_word);
1673		Registers[REGISTER_A] = (BYTE)temp_word;
1674		break;
1675
1676	case 0xD7: //SBC A,L
1677		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_L];
1678		if ((Flags & FLAG_C) != 0)
1679		{
1680			temp_word--;
1681		}
1682		if (temp_word >= 0x100)
1683		{
1684			Flags = Flags | FLAG_C;
1685		}
1686		else
1687		{
1688			Flags = Flags & (0xFF - FLAG_C);
1689		}
1690		set_flag_n((BYTE)temp_word);
1691		set_flag_z((BYTE)temp_word);
1692		Registers[REGISTER_A] = (BYTE)temp_word;
1693		break;
1694
1695	case 0xE7: //SBC A,H
1696		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_H];
1697		if ((Flags & FLAG_C) != 0)
1698		{
1699			temp_word--;
1700		}
1701		if (temp_word >= 0x100)
1702		{
1703			Flags = Flags | FLAG_C;
1704		}
1705		else
1706		{
1707			Flags = Flags & (0xFF - FLAG_C);
1708		}
1709		set_flag_n((BYTE)temp_word);
1710		set_flag_z((BYTE)temp_word);
1711		Registers[REGISTER_A] = (BYTE)temp_word;
1712		break;
1713
1714	case 0xF7: //SBC A,M
1715		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_M];
1716		if ((Flags & FLAG_C) != 0)
1717		{
1718			temp_word--;
1719		}
1720		if (temp_word >= 0x100)
1721		{
1722			Flags = Flags | FLAG_C;
1723		}
1724		else
1725		{
1726			Flags = Flags & (0xFF - FLAG_C);
1727		}
1728		set_flag_n((BYTE)temp_word);
1729		set_flag_z((BYTE)temp_word);
1730		Registers[REGISTER_A] = (BYTE)temp_word;
1731		break;
1732
1733	case 0xBB: //OR A,B
1734		temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_B];
1735		set_flag_n((BYTE)temp_word);
1736		set_flag_z((BYTE)temp_word);
1737		Registers[REGISTER_A] = (BYTE)temp_word;
1738		break;
1739
1740	case 0xCB: //OR A,C
1741		temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_C];
1742		set_flag_n((BYTE)temp_word);
1743		set_flag_z((BYTE)temp_word);
1744		Registers[REGISTER_A] = (BYTE)temp_word;
1745		break;
1746
1747	case 0xDB: //OR A,L
1748		temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_L];
1749		set_flag_n((BYTE)temp_word);
1750		set_flag_z((BYTE)temp_word);
1751		Registers[REGISTER_A] = (BYTE)temp_word;
1752		break;
1753
1754	case 0xEB: //OR A,H
1755		temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_H];
1756		set_flag_n((BYTE)temp_word);
1757		set_flag_z((BYTE)temp_word);
1758		Registers[REGISTER_A] = (BYTE)temp_word;
1759		break;
1760
1761	case 0xFB: //OR A,M
1762		temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_M];
1763		set_flag_n((BYTE)temp_word);
1764		set_flag_z((BYTE)temp_word);
1765		Registers[REGISTER_A] = (BYTE)temp_word;
1766		break;
1767
1768	case 0x9B: //COMA
1769		Registers[REGISTER_A] = Registers[REGISTER_A] ^ 0xFF;
1770		Flags = Flags | FLAG_C;
1771		set_flag_n(Registers[REGISTER_A]);
1772		set_flag_z(Registers[REGISTER_A]);
1773		break;
1774
1775	case 0xB9: //SUB A,B
1776		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_B];
1777		if (temp_word >= 0x100)
1778		{
1779			Flags = Flags | FLAG_C;
1780		}
1781		else
1782		{
1783			Flags = Flags & (0xFF - FLAG_C);
1784		}
1785		set_flag_n((BYTE)temp_word);
1786		set_flag_z((BYTE)temp_word);
1787		Registers[REGISTER_A] = (BYTE)temp_word;
1788		break;
1789
1790	case 0xC9: //SUB A,C
1791		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_C];
1792		if (temp_word >= 0x100)
1793		{
1794			Flags = Flags | FLAG_C;
1795		}
1796		else
1797		{
1798			Flags = Flags & (0xFF - FLAG_C);
1799		}
1800		set_flag_n((BYTE)temp_word);
1801		set_flag_z((BYTE)temp_word);
1802		Registers[REGISTER_A] = (BYTE)temp_word;
1803		break;
1804
1805	case 0xD9: //SUB A,L
1806		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_L];
1807		if (temp_word >= 0x100)
1808		{
1809			Flags = Flags | FLAG_C;
1810		}
1811		else
1812		{
1813			Flags = Flags & (0xFF - FLAG_C);
1814		}
1815		set_flag_n((BYTE)temp_word);
1816		set_flag_z((BYTE)temp_word);
1817		Registers[REGISTER_A] = (BYTE)temp_word;
1818		break;
1819
1820	case 0xE9: //SUB A,H
1821		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_H];
1822		if (temp_word >= 0x100)
1823		{
1824			Flags = Flags | FLAG_C;
1825		}
1826		else
1827		{
1828			Flags = Flags & (0xFF - FLAG_C);
1829		}
1830		set_flag_n((BYTE)temp_word);
1831		set_flag_z((BYTE)temp_word);
1832		Registers[REGISTER_A] = (BYTE)temp_word;
1833		break;
1834
1835	case 0xF9: //SUB A,C
1836		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_M];
1837		if (temp_word >= 0x100)
1838		{
1839			Flags = Flags | FLAG_C;
1840		}
1841		else
1842		{
1843			Flags = Flags & (0xFF - FLAG_C);
1844		}
1845		set_flag_n((BYTE)temp_word);
1846		set_flag_z((BYTE)temp_word);
1847		Registers[REGISTER_A] = (BYTE)temp_word;
1848		break;
1849
1850	case 0xBD: //XOR A,B
1851		temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_B];
1852		set_flag_n((BYTE)temp_word);
1853		set_flag_z((BYTE)temp_word);
1854		Registers[REGISTER_A] = (BYTE)temp_word;
1855		break;
1856
1857	case 0xCD: //XOR A,C
1858		temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_C];
1859		set_flag_n((BYTE)temp_word);
1860		set_flag_z((BYTE)temp_word);
1861		Registers[REGISTER_A] = (BYTE)temp_word;
1862		break;
1863
1864	case 0xDD: //XOR A,L
1865		temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_L];
1866		set_flag_n((BYTE)temp_word);
1867		set_flag_z((BYTE)temp_word);
1868		Registers[REGISTER_A] = (BYTE)temp_word;
1869		break;
1870
1871	case 0xED: //XOR A,H
1872		temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_H];
1873		set_flag_n((BYTE)temp_word);
1874		set_flag_z((BYTE)temp_word);
1875		Registers[REGISTER_A] = (BYTE)temp_word;
1876		break;
1877
1878	case 0xFD: //XOR A,M
1879		temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_M];
1880		set_flag_n((BYTE)temp_word);
1881		set_flag_z((BYTE)temp_word);
1882		Registers[REGISTER_A] = (BYTE)temp_word;
1883		break;
1884
1885	case 0x54: //TEST Absolute
1886		LB = fetch();
1887		HB = fetch();
1888		address += (WORD)((WORD)HB << 8) + LB;
1889		data = Memory[address];
1890		set_flag_n(data);
1891		set_flag_z(data);
1892		break;
1893
1894	case 0x64: //TEST Absolute X
1895		address += Index_Registers[REGISTER_X];
1896		LB = fetch();
1897		HB = fetch();
1898		address += (WORD)((WORD)HB << 8) + LB;
1899		data = Memory[address];
1900		set_flag_n(data);
1901		set_flag_z(data);
1902		break;
1903
1904	case 0x74: //TEST Absolute Y
1905		address += Index_Registers[REGISTER_Y];
1906		LB = fetch();
1907		HB = fetch();
1908		address += (WORD)((WORD)HB << 8) + LB;
1909		data = Memory[address];
1910		set_flag_n(data);
1911		set_flag_z(data);
1912		break;
1913
1914	case 0x84: //TEST Absolute X,Y
1915		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1916		LB = fetch();
1917		HB = fetch();
1918		address += (WORD)((WORD)HB << 8) + LB;
1919		data = Memory[address];
1920		set_flag_n(data);
1921		set_flag_z(data);
1922		break;
1923
1924	case 0x56: //DEC Absolute
1925		LB = fetch();
1926		HB = fetch();
1927		address += (WORD)((WORD)HB << 8) + LB;
1928		Memory[address]--;
1929		set_flag_n(Memory[address]);
1930		set_flag_z(Memory[address]);
1931		break;
1932
1933	case 0x66: //DEC Absolute X
1934		address += Index_Registers[REGISTER_X];
1935		LB = fetch();
1936		HB = fetch();
1937		address += (WORD)((WORD)HB << 8) + LB;
1938		if (address >= 0 && address < MEMORY_SIZE)
1939		{
1940			Memory[address]--;
1941		}
1942		set_flag_n(Memory[address]);
1943		set_flag_z(Memory[address]);
1944		break;
1945
1946	case 0x76: //DEC Absolute Y
1947		address += Index_Registers[REGISTER_Y];
1948		LB = fetch();
1949		HB = fetch();
1950		address += (WORD)((WORD)HB << 8) + LB;
1951		if (address >= 0 && address < MEMORY_SIZE)
1952		{
1953			Memory[address]--;
1954		}
1955		set_flag_n(Memory[address]);
1956		set_flag_z(Memory[address]);
1957		break;
1958
1959	case 0x86: //DEC Absolute X,Y
1960		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1961		LB = fetch();
1962		HB = fetch();
1963		address += (WORD)((WORD)HB << 8) + LB;
1964		if (address >= 0 && address < MEMORY_SIZE)
1965		{
1966			Memory[address]--;
1967		}
1968		set_flag_n(Memory[address]);
1969		set_flag_z(Memory[address]);
1970		break;
1971
1972	case 0x59: //SAL Absolute
1973		LB = fetch();
1974		HB = fetch();
1975		address = (WORD)((WORD)HB << 8) + LB;
1976		saved_flags = Flags;
1977
1978		if ((Memory[address] & 0x80) == 0x80) {
1979			Flags = Flags | FLAG_C;
1980		}
1981		else {
1982			Flags = Flags & (0xFF - FLAG_C);
1983		}
1984
1985		Memory[address] = (Memory[address] << 1) & 0xFE;
1986
1987		set_flag_n(Memory[address]);
1988		set_flag_z(Memory[address]);
1989		break;
1990
1991	case 0x69: //SAL Absolute X
1992		address += Index_Registers[REGISTER_X];
1993		LB = fetch();
1994		HB = fetch();
1995		address = (WORD)((WORD)HB << 8) + LB;
1996		saved_flags = Flags;
1997
1998		if ((Memory[address] & 0x80) == 0x80) {
1999			Flags = Flags | FLAG_C;
2000		}
2001		else {
2002			Flags = Flags & (0xFF - FLAG_C);
2003		}
2004
2005		Memory[address] = (Memory[address] << 1) & 0xFE;
2006
2007		set_flag_n(Memory[address]);
2008		set_flag_z(Memory[address]);
2009		break;
2010
2011	case 0x79: //SAL Absolute Y
2012		address += Index_Registers[REGISTER_Y];
2013		LB = fetch();
2014		HB = fetch();
2015		address = (WORD)((WORD)HB << 8) + LB;
2016		saved_flags = Flags;
2017
2018		if ((Memory[address] & 0x80) == 0x80) {
2019			Flags = Flags | FLAG_C;
2020		}
2021		else {
2022			Flags = Flags & (0xFF - FLAG_C);
2023		}
2024
2025		Memory[address] = (Memory[address] << 1) & 0xFE;
2026
2027		set_flag_n(Memory[address]);
2028		set_flag_z(Memory[address]);
2029		break;
2030
2031	case 0x89: //SAL Absolute X,Y
2032		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2033		LB = fetch();
2034		HB = fetch();
2035		address = (WORD)((WORD)HB << 8) + LB;
2036		saved_flags = Flags;
2037
2038		if ((Memory[address] & 0x80) == 0x80) {
2039			Flags = Flags | FLAG_C;
2040		}
2041		else {
2042			Flags = Flags & (0xFF - FLAG_C);
2043		}
2044
2045		Memory[address] = (Memory[address] << 1) & 0xFE;
2046
2047		set_flag_n(Memory[address]);
2048		set_flag_z(Memory[address]);
2049		break;
2050
2051	case 0x5A: //SHR Absolute
2052		LB = fetch();
2053		HB = fetch();
2054		address = (WORD)((WORD)HB << 8) + LB;
2055		if ((Memory[address] & 0x01) == 0x01) {
2056			Flags = Flags | FLAG_C;
2057		}
2058		else {
2059			Flags = Flags & (0xFF - FLAG_C);
2060		}
2061		HB = Memory[address];
2062		Memory[address] = (Memory[address] >> 1) & 0x7F;
2063		if ((HB & 0x80) == 0x80) {
2064			Memory[address] = Memory[address] | 0x80;
2065		}
2066		set_flag_n(Memory[address]);
2067		set_flag_z(Memory[address]);
2068		break;
2069
2070	case 0x6A: //SHR Absolute X
2071		address += Index_Registers[REGISTER_X];
2072		LB = fetch();
2073		HB = fetch();
2074		address = (WORD)((WORD)HB << 8) + LB;
2075		if ((Memory[address] & 0x01) == 0x01) {
2076			Flags = Flags | FLAG_C;
2077		}
2078		else {
2079			Flags = Flags & (0xFF - FLAG_C);
2080		}
2081		HB = Memory[address];
2082		Memory[address] = (Memory[address] >> 1) & 0x7F;
2083		if ((HB & 0x80) == 0x80) {
2084			Memory[address] = Memory[address] | 0x80;
2085		}
2086		set_flag_n(Memory[address]);
2087		set_flag_z(Memory[address]);
2088		break;
2089
2090	case 0x7A: //SHR Absolute Y
2091		address += Index_Registers[REGISTER_Y];
2092		LB = fetch();
2093		HB = fetch();
2094		address = (WORD)((WORD)HB << 8) + LB;
2095		if ((Memory[address] & 0x01) == 0x01) {
2096			Flags = Flags | FLAG_C;
2097		}
2098		else {
2099			Flags = Flags & (0xFF - FLAG_C);
2100		}
2101		HB = Memory[address];
2102		Memory[address] = (Memory[address] >> 1) & 0x7F;
2103		if ((HB & 0x80) == 0x80) {
2104			Memory[address] = Memory[address] | 0x80;
2105		}
2106		set_flag_n(Memory[address]);
2107		set_flag_z(Memory[address]);
2108
2109		break;
2110
2111	case 0x8A: //SHR Absolute X,Y
2112		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2113		LB = fetch();
2114		HB = fetch();
2115		address = (WORD)((WORD)HB << 8) + LB;
2116		if ((Memory[address] & 0x01) == 0x01) {
2117			Flags = Flags | FLAG_C;
2118		}
2119		else {
2120			Flags = Flags & (0xFF - FLAG_C);
2121		}
2122		HB = Memory[address];
2123		Memory[address] = (Memory[address] >> 1) & 0x7F;
2124		if ((HB & 0x80) == 0x80) {
2125			Memory[address] = Memory[address] | 0x80;
2126		}
2127		set_flag_n(Memory[address]);
2128		set_flag_z(Memory[address]);
2129		break;
2130
2131	case 0x5C: //NEG Absolute
2132		LB = fetch();
2133		HB = fetch();
2134		address += (WORD)((WORD)HB << 8) + LB;
2135		Memory[address] = 0 - Memory[address];
2136		set_flag_n(Memory[address]);
2137		set_flag_z(Memory[address]);
2138		break;
2139
2140	case 0x6C: //NEG Absolute X
2141		address += Index_Registers[REGISTER_X];
2142
2143		LB = fetch();
2144		HB = fetch();
2145		address += (WORD)((WORD)HB << 8) + LB;
2146		Memory[address] = 0 - Memory[address];
2147		set_flag_n(Memory[address]);
2148		set_flag_z(Memory[address]);
2149		break;
2150
2151	case 0x7C: //NEG Absolute Y
2152		address += Index_Registers[REGISTER_Y];
2153
2154		LB = fetch();
2155		HB = fetch();
2156		address += (WORD)((WORD)HB << 8) + LB;
2157
2158		Memory[address] = 0 - Memory[address];
2159		set_flag_n(Memory[address]);
2160		set_flag_z(Memory[address]);
2161		break;
2162
2163	case 0x8C: //NEG Absolute X,Y
2164		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2165		LB = fetch();
2166		HB = fetch();
2167		address += (WORD)((WORD)HB << 8) + LB;
2168		Memory[address] = 0 - Memory[address];
2169
2170		set_flag_n(Memory[address]);
2171		set_flag_z(Memory[address]);
2172		break;
2173
2174	case 0x02: //SWI (IMPL)
2175		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
2176			StackPointer--;
2177			Memory[StackPointer] = Registers[REGISTER_A];
2178		}
2179		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
2180			StackPointer--;
2181			Memory[StackPointer] = (BYTE)ProgramCounter;
2182		}
2183		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
2184			StackPointer--;
2185			Memory[StackPointer] = (BYTE)(ProgramCounter >> 8);
2186		}
2187		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
2188			StackPointer--;
2189			Memory[StackPointer] = Flags;
2190		}
2191		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
2192			StackPointer--;
2193			Memory[StackPointer] = Registers[REGISTER_B];
2194		}
2195		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
2196			StackPointer--;
2197			Memory[StackPointer] = Registers[REGISTER_C];
2198		}
2199		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
2200			StackPointer--;
2201			Memory[StackPointer] = Registers[REGISTER_L];
2202		}
2203		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
2204			StackPointer--;
2205			Memory[StackPointer] = Registers[REGISTER_H];
2206		}
2207
2208		break;
2209
2210	case 0x03: //RTI (IMPL)
2211		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
2212			Registers[REGISTER_H] = Memory[StackPointer];
2213			StackPointer++;
2214		}
2215		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
2216			Registers[REGISTER_L] = Memory[StackPointer];
2217			StackPointer++;
2218		}
2219		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
2220			Registers[REGISTER_C] = Memory[StackPointer];
2221			StackPointer++;
2222		}
2223		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
2224			Registers[REGISTER_B] = Memory[StackPointer];
2225			StackPointer++;
2226		}
2227		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
2228			Flags = Memory[StackPointer];
2229			StackPointer++;
2230		}
2231		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
2232			ProgramCounter = (WORD)(Memory[StackPointer] << 8);
2233			StackPointer++;
2234		}
2235		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
2236			ProgramCounter += Memory[StackPointer];
2237			StackPointer++;
2238		}
2239		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
2240			Registers[REGISTER_A] = Memory[StackPointer];
2241			StackPointer++;
2242		}
2243		break;
2244
2245	case 0x98: //RCLA
2246		saved_flags = Flags;
2247
2248		if ((Registers[REGISTER_A] & 0x80) == 0x80) {
2249			Flags = Flags | FLAG_C;
2250		}
2251		else {
2252			Flags = Flags & (0xFF - FLAG_C);
2253		}
2254		Registers[REGISTER_A] = (Registers[REGISTER_A] << 1) & 0xFE;
2255
2256		if ((saved_flags & FLAG_C) == FLAG_C) {
2257			Registers[REGISTER_A] = Registers[REGISTER_A] | 0x01;
2258		}
2259		set_flag_n((BYTE)Registers[REGISTER_A]);
2260		set_flag_z((BYTE)Registers[REGISTER_A]);
2261		break;
2262
2263	case 0x99: //SALA
2264		saved_flags = Flags;
2265
2266		if ((Registers[REGISTER_A] & 0x80) == 0x80) {
2267			Flags = Flags | FLAG_C;
2268		}
2269		else {
2270			Flags = Flags & (0xFF - FLAG_C);
2271		}
2272		Registers[REGISTER_A] = (Registers[REGISTER_A] << 1) & 0xFE;
2273
2274		set_flag_n((BYTE)Registers[REGISTER_A]);
2275		set_flag_z((BYTE)Registers[REGISTER_A]);
2276		break;
2277
2278	case 0x9A: //SHRA
2279		if ((Registers[REGISTER_A] & 0x01) == 0x01)
2280		{
2281			Flags = Flags | FLAG_C;
2282		}
2283		else
2284		{
2285			Flags = Flags & (0xFF - FLAG_C);
2286		}
2287		Registers[REGISTER_A] = (Registers[REGISTER_A] >> 1) & 0x7F;
2288		if ((Flags & FLAG_N) == FLAG_N)
2289		{
2290			Registers[REGISTER_A] = Registers[REGISTER_A] | 0x80;
2291		}
2292		set_flag_n(Registers[REGISTER_A]);
2293		set_flag_z(Registers[REGISTER_A]);
2294		break;
2295	case 0x17: //NOP
2296		break;
2297
2298	case 0x18: //WAI
2299		halt = true;
2300		break;
2301	case 0x1C: //ADI Immediate
2302		data = fetch();
2303		temp_word = (WORD)Registers[REGISTER_A] + data;
2304		if ((Flags & FLAG_C) != 0)
2305		{
2306			temp_word++;
2307		}
2308		if (temp_word >= 0x100)
2309		{
2310			Flags = Flags | FLAG_C;
2311		}
2312		else
2313		{
2314			Flags = Flags & (0xFF - FLAG_C);
2315		}
2316		set_flag_n((BYTE)temp_word);
2317		set_flag_z((BYTE)temp_word);
2318		Registers[REGISTER_A] = (BYTE)temp_word;
2319		break;
2320		////////////////////CPI
2321	case 0x1D: // CPI
2322		data = fetch();
2323
2324		temp_word = (WORD)data - (WORD)Registers[REGISTER_A];
2325
2326		if (temp_word >= 0x100) {
2327			Flags = Flags | FLAG_C; // Set carry flag
2328		}
2329		else {
2330			Flags = Flags & (0xFF - FLAG_C);  // Clear carry flag
2331		}
2332
2333		set_flag_z((BYTE)temp_word);
2334		set_flag_n((BYTE)temp_word);
2335		break;
2336	case 0x1E: //ANI Immediate
2337		data = fetch();
2338		temp_word = (WORD)Registers[REGISTER_A] & data;
2339
2340		if (temp_word >= 0x100)
2341		{
2342			Flags = Flags | FLAG_C;
2343		}
2344		else
2345		{
2346			Flags = Flags & (0xFF - FLAG_C);
2347		}
2348		set_flag_n((BYTE)temp_word);
2349		set_flag_z((BYTE)temp_word);
2350		Registers[REGISTER_A] = (BYTE)temp_word;
2351
2352		break;
2353	case 0x94: //TESTA Register A
2354		set_flag_n(Registers[REGISTER_A]);
2355		set_flag_z(Registers[REGISTER_A]);
2356		break;
2357	case 0x96: //DECA Register A
2358		Registers[REGISTER_A]--;
2359		set_flag_n(Registers[REGISTER_A]);
2360		set_flag_z(Registers[REGISTER_A]);
2361		break;
2362	case 0x57: //RR Absolute
2363		LB = fetch();
2364		HB = fetch();
2365		address += (WORD)((WORD)HB << 8) + LB;
2366		saved_flags = Flags;
2367
2368		if ((Memory[address] & 0x01) == 0x01) {
2369			Flags = Flags | FLAG_C;
2370		}
2371		else {
2372			Flags = Flags & (0xFF - FLAG_C);
2373		}
2374		Memory[address] = (Memory[address] >> 1) & 0x7F;
2375
2376		if ((saved_flags & FLAG_C) == FLAG_C) {
2377			Memory[address] = Memory[address] | 0x80;
2378		}
2379		set_flag_n((BYTE)Memory[address]);
2380		set_flag_z((BYTE)Memory[address]);
2381		break;
2382	case 0x67: //RR Absolute X
2383		address += Index_Registers[REGISTER_X];
2384
2385		LB = fetch();
2386		HB = fetch();
2387		address += (WORD)((WORD)HB << 8) + LB;
2388		saved_flags = Flags;
2389
2390		if ((Memory[address] & 0x01) == 0x01) {
2391			Flags = Flags | FLAG_C;
2392		}
2393		else {
2394			Flags = Flags & (0xFF - FLAG_C);
2395		}
2396		Memory[address] = (Memory[address] >> 1) & 0x7F;
2397
2398		if ((saved_flags & FLAG_C) == FLAG_C) {
2399			Memory[address] = Memory[address] | 0x80;
2400		}
2401		set_flag_n((BYTE)Memory[address]);
2402		set_flag_z((BYTE)Memory[address]);
2403
2404		break;
2405	case 0x77: //RR Absolute Y
2406		address += Index_Registers[REGISTER_Y];
2407
2408		LB = fetch();
2409		HB = fetch();
2410		address += (WORD)((WORD)HB << 8) + LB;
2411		saved_flags = Flags;
2412
2413		if ((Memory[address] & 0x01) == 0x01) {
2414			Flags = Flags | FLAG_C;
2415		}
2416		else {
2417			Flags = Flags & (0xFF - FLAG_C);
2418		}
2419		Memory[address] = (Memory[address] >> 1) & 0x7F;
2420
2421		if ((saved_flags & FLAG_C) == FLAG_C) {
2422			Memory[address] = Memory[address] | 0x80;
2423		}
2424		set_flag_n((BYTE)Memory[address]);
2425		set_flag_z((BYTE)Memory[address]);
2426
2427		break;
2428	case 0x87: //RR Absolute X,Y
2429		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2430		LB = fetch();
2431		HB = fetch();
2432		address += (WORD)((WORD)HB << 8) + LB;
2433		saved_flags = Flags;
2434
2435		if ((Memory[address] & 0x01) == 0x01) {
2436			Flags = Flags | FLAG_C;
2437		}
2438		else {
2439			Flags = Flags & (0xFF - FLAG_C);
2440		}
2441		Memory[address] = (Memory[address] >> 1) & 0x7F;
2442
2443		if ((saved_flags & FLAG_C) == FLAG_C) {
2444			Memory[address] = Memory[address] | 0x80;
2445		}
2446		set_flag_n((BYTE)Memory[address]);
2447		set_flag_z((BYTE)Memory[address]);
2448
2449		break;
2450	case 0x97: //RRA Register A
2451		saved_flags = Flags;
2452
2453		if ((Registers[REGISTER_A] & 0x01) == 0x01) {
2454			Flags = Flags | FLAG_C;
2455		}
2456		else {
2457			Flags = Flags & (0xFF - FLAG_C);
2458		}
2459		Registers[REGISTER_A] = (Registers[REGISTER_A] >> 1) & 0x7F;
2460
2461		if ((saved_flags & FLAG_C) == FLAG_C) {
2462			Registers[REGISTER_A] = Registers[REGISTER_A] | 0x80;
2463		}
2464		set_flag_n((BYTE)Registers[REGISTER_A]);
2465		set_flag_z((BYTE)Registers[REGISTER_A]);
2466		break;
2467	case 0x58: //RCL Absolute
2468		LB = fetch();
2469		HB = fetch();
2470		address += (WORD)((WORD)HB << 8) + LB;
2471		saved_flags = Flags;
2472
2473		if ((Memory[address] & 0x80) == 0x80) {
2474			Flags = Flags | FLAG_C;
2475		}
2476		else {
2477			Flags = Flags & (0xFF - FLAG_C);
2478		}
2479		Memory[address] = (Memory[address] << 1) & 0xFE;
2480
2481		if ((saved_flags & FLAG_C) == FLAG_C) {
2482			Memory[address] = Memory[address] | 0x01;
2483		}
2484		set_flag_n((BYTE)Memory[address]);
2485		set_flag_z((BYTE)Memory[address]);
2486		break;
2487	case 0x68: //RCL Absolute X
2488		address += Index_Registers[REGISTER_X];
2489
2490		LB = fetch();
2491		HB = fetch();
2492		address += (WORD)((WORD)HB << 8) + LB;
2493		saved_flags = Flags;
2494
2495		if ((Memory[address] & 0x80) == 0x80) {
2496			Flags = Flags | FLAG_C;
2497		}
2498		else {
2499			Flags = Flags & (0xFF - FLAG_C);
2500		}
2501		Memory[address] = (Memory[address] << 1) & 0xFE;
2502
2503		if ((saved_flags & FLAG_C) == FLAG_C) {
2504			Memory[address] = Memory[address] | 0x01;
2505		}
2506		set_flag_n((BYTE)Memory[address]);
2507		set_flag_z((BYTE)Memory[address]);
2508		break;
2509	case 0x78: //RCL Absolute Y
2510		address += Index_Registers[REGISTER_Y];
2511
2512		LB = fetch();
2513		HB = fetch();
2514		address += (WORD)((WORD)HB << 8) + LB;
2515		saved_flags = Flags;
2516
2517		if ((Memory[address] & 0x80) == 0x80) {
2518			Flags = Flags | FLAG_C;
2519		}
2520		else {
2521			Flags = Flags & (0xFF - FLAG_C);
2522		}
2523		Memory[address] = (Memory[address] << 1) & 0xFE;
2524
2525		if ((saved_flags & FLAG_C) == FLAG_C) {
2526			Memory[address] = Memory[address] | 0x01;
2527		}
2528		set_flag_n((BYTE)Memory[address]);
2529		set_flag_z((BYTE)Memory[address]);
2530		break;
2531	case 0x88: //RCL Absolute X,Y
2532		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2533
2534		LB = fetch();
2535		HB = fetch();
2536		address += (WORD)((WORD)HB << 8) + LB;
2537		saved_flags = Flags;
2538
2539		if ((Memory[address] & 0x80) == 0x80) {
2540			Flags = Flags | FLAG_C;
2541		}
2542		else {
2543			Flags = Flags & (0xFF - FLAG_C);
2544		}
2545		Memory[address] = (Memory[address] << 1) & 0xFE;
2546
2547		if ((saved_flags & FLAG_C) == FLAG_C) {
2548			Memory[address] = Memory[address] | 0x01;
2549		}
2550		set_flag_n((BYTE)Memory[address]);
2551		set_flag_z((BYTE)Memory[address]);
2552		break;
2553	case 0x5B: //COM Absolute
2554		LB = fetch();
2555		HB = fetch();
2556		address += (WORD)((WORD)HB << 8) + LB;
2557		Memory[address] = Memory[address] ^ 0xFFFF;
2558
2559		Flags = Flags | FLAG_C;
2560		set_flag_n(Memory[address]);
2561		set_flag_z(Memory[address]);
2562		break;
2563	case 0x6B: //COM Absolute X
2564		address += Index_Registers[REGISTER_X];
2565
2566		LB = fetch();
2567		HB = fetch();
2568		address += (WORD)((WORD)HB << 8) + LB;
2569		Memory[address] = Memory[address] ^ 0xFFFF;
2570
2571		Flags = Flags | FLAG_C;
2572		set_flag_n(Memory[address]);
2573		set_flag_z(Memory[address]);
2574		break;
2575	case 0x7B: //COM Absolute Y
2576		address += Index_Registers[REGISTER_Y];
2577
2578		LB = fetch();
2579		HB = fetch();
2580		address += (WORD)((WORD)HB << 8) + LB;
2581		Memory[address] = Memory[address] ^ 0xFFFF;
2582
2583		Flags = Flags | FLAG_C;
2584		set_flag_n(Memory[address]);
2585		set_flag_z(Memory[address]);
2586		break;
2587	case 0x8B: //COM Absolute X,Y
2588		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2589		LB = fetch();
2590		HB = fetch();
2591		address += (WORD)((WORD)HB << 8) + LB;
2592		Memory[address] = Memory[address] ^ 0xFFFF;
2593
2594		Flags = Flags | FLAG_C;
2595		set_flag_n(Memory[address]);
2596		set_flag_z(Memory[address]);
2597		break;
2598	case 0x9C: //NEGA Register A
2599		Registers[REGISTER_A] = Registers[REGISTER_A] ^ 0xFF;
2600		Registers[REGISTER_A]++;
2601
2602
2603		set_flag_n(Registers[REGISTER_A]);
2604		set_flag_z(Registers[REGISTER_A]);
2605
2606		break;
2607	case 0x5D: //RAL Absolute
2608		LB = fetch();
2609		HB = fetch();
2610		address += (WORD)((WORD)HB << 8) + LB;
2611
2612		saved_flags = Flags;
2613
2614		if ((Memory[address] & 0x80) == 0x80) {
2615			Flags = Flags | FLAG_C;
2616		}
2617		else {
2618			Flags = Flags & (0xFF - FLAG_C);
2619		}
2620		Memory[address] = (Memory[address] << 1) & 0xFE;
2621
2622		if ((Flags & FLAG_C) == FLAG_C) {
2623			Memory[address] = Memory[address] | 0x01;
2624		}
2625		Flags = saved_flags;
2626		set_flag_n((BYTE)Memory[address]);
2627		set_flag_z((BYTE)Memory[address]);
2628		break;
2629	case 0x6D: //RAL Absolute X
2630		address += Index_Registers[REGISTER_X];
2631
2632		LB = fetch();
2633		HB = fetch();
2634		address += (WORD)((WORD)HB << 8) + LB;
2635
2636		saved_flags = Flags;
2637
2638		if ((Memory[address] & 0x80) == 0x80) {
2639			Flags = Flags | FLAG_C;
2640		}
2641		else {
2642			Flags = Flags & (0xFF - FLAG_C);
2643		}
2644		Memory[address] = (Memory[address] << 1) & 0xFE;
2645
2646		if ((Flags & FLAG_C) == FLAG_C) {
2647			Memory[address] = Memory[address] | 0x01;
2648		}
2649		Flags = saved_flags;
2650		set_flag_n((BYTE)Memory[address]);
2651		set_flag_z((BYTE)Memory[address]);
2652		break;
2653	case 0x7D: //RAL Absolute Y
2654		address += Index_Registers[REGISTER_Y];
2655
2656		LB = fetch();
2657		HB = fetch();
2658		address += (WORD)((WORD)HB << 8) + LB;
2659
2660		saved_flags = Flags;
2661
2662		if ((Memory[address] & 0x80) == 0x80) {
2663			Flags = Flags | FLAG_C;
2664		}
2665		else {
2666			Flags = Flags & (0xFF - FLAG_C);
2667		}
2668		Memory[address] = (Memory[address] << 1) & 0xFE;
2669
2670		if ((Flags & FLAG_C) == FLAG_C) {
2671			Memory[address] = Memory[address] | 0x01;
2672		}
2673		Flags = saved_flags;
2674		set_flag_n((BYTE)Memory[address]);
2675		set_flag_z((BYTE)Memory[address]);
2676		break;
2677	case 0x8D: //RAL Absolute X,Y
2678		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2679		LB = fetch();
2680		HB = fetch();
2681		address += (WORD)((WORD)HB << 8) + LB;
2682
2683		saved_flags = Flags;
2684
2685		if ((Memory[address] & 0x80) == 0x80) {
2686			Flags = Flags | FLAG_C;
2687		}
2688		else {
2689			Flags = Flags & (0xFF - FLAG_C);
2690		}
2691		Memory[address] = (Memory[address] << 1) & 0xFE;
2692
2693		if ((Flags & FLAG_C) == FLAG_C) {
2694			Memory[address] = Memory[address] | 0x01;
2695		}
2696		Flags = saved_flags;
2697		set_flag_n((BYTE)Memory[address]);
2698		set_flag_z((BYTE)Memory[address]);
2699		break;
2700	case 0x9D: //RALA Register A
2701		saved_flags = Flags;
2702
2703		if ((Registers[REGISTER_A] & 0x80) == 0x80) {
2704			Flags = Flags | FLAG_C;
2705		}
2706		else {
2707			Flags = Flags & (0xFF - FLAG_C);
2708		}
2709		Registers[REGISTER_A] = (Registers[REGISTER_A] << 1) & 0xFE;
2710
2711		if ((Flags & FLAG_C) == FLAG_C) {
2712			Registers[REGISTER_A] = Registers[REGISTER_A] | 0x01;
2713		}
2714		Flags = saved_flags;
2715		set_flag_n((BYTE)Registers[REGISTER_A]);
2716		set_flag_z((BYTE)Registers[REGISTER_A]);
2717		break;
2718	case 0x5E: //ROR Absolute
2719		LB = fetch();
2720		HB = fetch();
2721		address += (WORD)((WORD)HB << 8) + LB;
2722		saved_flags = Flags;
2723
2724		if ((Memory[address] & 0x01) == 0x01) {
2725			Flags = Flags | FLAG_C;
2726		}
2727		else {
2728			Flags = Flags & (0xFF - FLAG_C);
2729		}
2730		Memory[address] = (Memory[address] >> 1) & 0x7F;
2731
2732		if ((Flags & FLAG_C) == FLAG_C) {
2733			Memory[address] = Memory[address] | 0x80;
2734		}
2735		Flags = saved_flags;
2736		set_flag_n((BYTE)Memory[address]);
2737		set_flag_z((BYTE)Memory[address]);
2738		break;
2739	case 0x6E: //ROR Absolute X
2740		address += Index_Registers[REGISTER_X];
2741
2742		LB = fetch();
2743		HB = fetch();
2744		address += (WORD)((WORD)HB << 8) + LB;
2745		saved_flags = Flags;
2746
2747		if ((Memory[address] & 0x01) == 0x01) {
2748			Flags = Flags | FLAG_C;
2749		}
2750		else {
2751			Flags = Flags & (0xFF - FLAG_C);
2752		}
2753		Memory[address] = (Memory[address] >> 1) & 0x7F;
2754
2755		if ((Flags & FLAG_C) == FLAG_C) {
2756			Memory[address] = Memory[address] | 0x80;
2757		}
2758		Flags = saved_flags;
2759		set_flag_n((BYTE)Memory[address]);
2760		set_flag_z((BYTE)Memory[address]);
2761		break;
2762	case 0x7E: //ROR Absolute Y
2763		address += Index_Registers[REGISTER_Y];
2764
2765		LB = fetch();
2766		HB = fetch();
2767		address += (WORD)((WORD)HB << 8) + LB;
2768		saved_flags = Flags;
2769
2770		if ((Memory[address] & 0x01) == 0x01) {
2771			Flags = Flags | FLAG_C;
2772		}
2773		else {
2774			Flags = Flags & (0xFF - FLAG_C);
2775		}
2776		Memory[address] = (Memory[address] >> 1) & 0x7F;
2777
2778		if ((Flags & FLAG_C) == FLAG_C) {
2779			Memory[address] = Memory[address] | 0x80;
2780		}
2781		Flags = saved_flags;
2782		set_flag_n((BYTE)Memory[address]);
2783		set_flag_z((BYTE)Memory[address]);
2784		break;
2785	case 0x8E: //ROR Absolute X,Y
2786		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2787		LB = fetch();
2788		HB = fetch();
2789		address += (WORD)((WORD)HB << 8) + LB;
2790		saved_flags = Flags;
2791
2792		if ((Memory[address] & 0x01) == 0x01) {
2793			Flags = Flags | FLAG_C;
2794		}
2795		else {
2796			Flags = Flags & (0xFF - FLAG_C);
2797		}
2798		Memory[address] = (Memory[address] >> 1) & 0x7F;
2799
2800		if ((Flags & FLAG_C) == FLAG_C) {
2801			Memory[address] = Memory[address] | 0x80;
2802		}
2803		Flags = saved_flags;
2804		set_flag_n((BYTE)Memory[address]);
2805		set_flag_z((BYTE)Memory[address]);
2806
2807		break;
2808	case 0x9E: //RORA Register A
2809		saved_flags = Flags;
2810
2811		if ((Registers[REGISTER_A] & 0x01) == 0x01) {
2812			Flags = Flags | FLAG_C;
2813		}
2814		else {
2815			Flags = Flags & (0xFF - FLAG_C);
2816		}
2817		Registers[REGISTER_A] = (Registers[REGISTER_A] >> 1) & 0x7F;
2818
2819		if ((Flags & FLAG_C) == FLAG_C) {
2820			Registers[REGISTER_A] = Registers[REGISTER_A] | 0x80;
2821		}
2822		Flags = saved_flags;
2823		set_flag_n((BYTE)Registers[REGISTER_A]);
2824		set_flag_z((BYTE)Registers[REGISTER_A]);
2825		break;
2826	}
2827}
2828
2829void Group_2_Move(BYTE opcode) {
2830
2831	BYTE source = opcode >> 4;
2832	BYTE destination = opcode & 0x0F;
2833	WORD address = 0;
2834
2835	int destReg = 0;
2836	int sourceReg = 0;
2837
2838	switch (destination)
2839	{
2840	case 0x00:
2841		destReg = REGISTER_A;
2842		break;
2843
2844	case 0x01:
2845		destReg = REGISTER_B;
2846		break;
2847
2848	case 0x02:
2849		destReg = REGISTER_C;
2850		break;
2851
2852	case 0x03:
2853		destReg = REGISTER_L;
2854		break;
2855
2856	case 0x04:
2857		destReg = REGISTER_H;
2858		break;
2859
2860	case 0x05:
2861		destReg = REGISTER_M;
2862		break;
2863
2864	case 0xA0:
2865		destReg = REGISTER_A;
2866		break;
2867
2868	case 0xB0:
2869		destReg = REGISTER_A;
2870		break;
2871
2872	case 0xC0:
2873		destReg = REGISTER_A;
2874		break;
2875
2876	case 0xD0:
2877		destReg = REGISTER_A;
2878		break;
2879
2880	case 0xE0:
2881		destReg = REGISTER_A;
2882		break;
2883
2884	case 0xF0:
2885		destReg = REGISTER_A;
2886		break;
2887
2888	case 0xA1:
2889		destReg = REGISTER_B;
2890		break;
2891
2892	case 0xB1:
2893		destReg = REGISTER_B;
2894		break;
2895
2896	case 0xC1:
2897		destReg = REGISTER_B;
2898		break;
2899
2900	case 0xD1:
2901		destReg = REGISTER_B;
2902		break;
2903
2904	case 0xE1:
2905		destReg = REGISTER_B;
2906		break;
2907
2908	case 0xF1:
2909		destReg = REGISTER_B;
2910		break;
2911
2912	case 0xA2:
2913		destReg = REGISTER_C;
2914		break;
2915
2916	case 0xB2:
2917		destReg = REGISTER_C;
2918		break;
2919
2920	case 0xC2:
2921		destReg = REGISTER_C;
2922		break;
2923
2924	case 0xD2:
2925		destReg = REGISTER_C;
2926		break;
2927
2928	case 0xE2:
2929		destReg = REGISTER_C;
2930		break;
2931
2932	case 0xF2:
2933		destReg = REGISTER_C;
2934		break;
2935
2936	case 0xA3:
2937		destReg = REGISTER_L;
2938		break;
2939
2940	case 0xB3:
2941		destReg = REGISTER_L;
2942		break;
2943
2944	case 0xC3:
2945		destReg = REGISTER_L;
2946		break;
2947
2948	case 0xD3:
2949		destReg = REGISTER_L;
2950		break;
2951
2952	case 0xE3:
2953		destReg = REGISTER_L;
2954		break;
2955
2956	case 0xF3:
2957		destReg = REGISTER_L;
2958		break;
2959
2960	case 0xA4:
2961		destReg = REGISTER_H;
2962		break;
2963
2964	case 0xB4:
2965		destReg = REGISTER_H;
2966		break;
2967
2968	case 0xC4:
2969		destReg = REGISTER_H;
2970		break;
2971
2972	case 0xD4:
2973		destReg = REGISTER_H;
2974		break;
2975
2976	case 0xE4:
2977		destReg = REGISTER_H;
2978		break;
2979
2980	case 0xF4:
2981		destReg = REGISTER_H;
2982		break;
2983
2984	case 0xA5:
2985		destReg = REGISTER_M;
2986		break;
2987
2988	case 0xB5:
2989		destReg = REGISTER_M;
2990		break;
2991
2992	case 0xC5:
2993		destReg = REGISTER_M;
2994		break;
2995
2996	case 0xD5:
2997		destReg = REGISTER_M;
2998		break;
2999
3000	case 0xE5:
3001		destReg = REGISTER_M;
3002		break;
3003	}
3004
3005	switch (source)
3006	{
3007	case 0xA0:
3008		sourceReg = REGISTER_A;
3009		break;
3010
3011	case 0xA1:
3012		sourceReg = REGISTER_A;
3013		break;
3014
3015	case 0xA2:
3016		sourceReg = REGISTER_A;
3017		break;
3018
3019	case 0xA3:
3020		sourceReg = REGISTER_A;
3021		break;
3022
3023	case 0xA4:
3024		sourceReg = REGISTER_A;
3025		break;
3026
3027	case 0xA5:
3028		sourceReg = REGISTER_A;
3029		break;
3030
3031	case 0xB0:
3032		sourceReg = REGISTER_B;
3033		break;
3034
3035	case 0xB1:
3036		sourceReg = REGISTER_B;
3037		break;
3038
3039	case 0xB2:
3040		sourceReg = REGISTER_B;
3041		break;
3042
3043	case 0xB3:
3044		sourceReg = REGISTER_B;
3045		break;
3046
3047	case 0xB4:
3048		sourceReg = REGISTER_B;
3049		break;
3050
3051	case 0xB5:
3052		sourceReg = REGISTER_B;
3053		break;
3054
3055	case 0xC0:
3056		sourceReg = REGISTER_C;
3057		break;
3058
3059	case 0xC1:
3060		sourceReg = REGISTER_C;
3061		break;
3062
3063	case 0xC2:
3064		sourceReg = REGISTER_C;
3065		break;
3066
3067	case 0xC3:
3068		sourceReg = REGISTER_C;
3069		break;
3070
3071	case 0xC4:
3072		sourceReg = REGISTER_C;
3073		break;
3074
3075	case 0xC5:
3076		sourceReg = REGISTER_C;
3077		break;
3078
3079	case 0xD0:
3080		sourceReg = REGISTER_L;
3081		break;
3082
3083	case 0xD1:
3084		sourceReg = REGISTER_L;
3085		break;
3086
3087	case 0xD2:
3088		sourceReg = REGISTER_L;
3089		break;
3090
3091	case 0xD3:
3092		sourceReg = REGISTER_L;
3093		break;
3094
3095	case 0xD4:
3096		sourceReg = REGISTER_L;
3097		break;
3098
3099	case 0xD5:
3100		sourceReg = REGISTER_L;
3101		break;
3102
3103	case 0xE0:
3104		sourceReg = REGISTER_H;
3105		break;
3106
3107	case 0xE1:
3108		sourceReg = REGISTER_H;
3109		break;
3110
3111	case 0xE2:
3112		sourceReg = REGISTER_H;
3113		break;
3114
3115	case 0xE3:
3116		sourceReg = REGISTER_H;
3117		break;
3118
3119	case 0xE4:
3120		sourceReg = REGISTER_H;
3121		break;
3122
3123	case 0xE5:
3124		sourceReg = REGISTER_H;
3125		break;
3126
3127	case 0xF0:
3128		sourceReg = REGISTER_M;
3129		break;
3130
3131	case 0xF1:
3132		sourceReg = REGISTER_M;
3133		break;
3134
3135	case 0xF2:
3136		sourceReg = REGISTER_M;
3137		break;
3138
3139	case 0xF3:
3140		sourceReg = REGISTER_M;
3141		break;
3142
3143	case 0xF4:
3144		sourceReg = REGISTER_M;
3145		break;
3146
3147	case 0x0A:
3148		sourceReg = REGISTER_A;
3149		break;
3150
3151	case 0x0B:
3152		sourceReg = REGISTER_B;
3153		break;
3154
3155	case 0x0C:
3156		sourceReg = REGISTER_C;
3157		break;
3158
3159	case 0x0D:
3160		sourceReg = REGISTER_L;
3161		break;
3162
3163	case 0x0E:
3164		sourceReg = REGISTER_H;
3165		break;
3166
3167	case 0x0F:
3168		sourceReg = REGISTER_M;
3169		break;
3170	}
3171
3172	if (sourceReg == REGISTER_M) {
3173
3174		address = Registers[REGISTER_L];
3175		address += (WORD)Registers[REGISTER_H] << 8;
3176
3177		if (address >= 0 && address <= MEMORY_SIZE) {
3178
3179			Registers[REGISTER_M] = Memory[address];
3180
3181		}
3182	}
3183
3184	if (destReg == REGISTER_M) {
3185
3186		address = Registers[REGISTER_L];
3187		address += (WORD)Registers[REGISTER_H] << 8;
3188
3189		if (address >= 0 && address <= MEMORY_SIZE) {
3190
3191			Memory[address] = Registers[sourceReg];
3192
3193		}
3194	}
3195	else {
3196		Registers[destReg] = Registers[sourceReg];
3197	}
3198}
3199
3200void execute(BYTE opcode)
3201{
3202
3203	BYTE source = opcode >> 4;
3204	BYTE destination = opcode & 0x0F;
3205
3206	if (((source >= 0x0A) && (source <= 0xF5)) && ((destination >= 0x00) && (destination <= 0x05))) {
3207		Group_2_Move(opcode);
3208	}
3209	else
3210	{
3211		Group_1(opcode);
3212	}
3213}
3214
3215void emulate()
3216{
3217	BYTE opcode;
3218	int sanity;
3219
3220	ProgramCounter = 0;
3221	halt = false;
3222	memory_in_range = true;
3223	sanity = 0;
3224
3225	printf("                    A  B  C  L  H  X  Y  SP\n");
3226
3227	while ((!halt) && (memory_in_range)) {
3228		printf("%04X ", ProgramCounter);           // Print current address
3229		opcode = fetch();
3230		execute(opcode);
3231
3232		printf("%s  ", opcode_mneumonics[opcode]);  // Print current opcode
3233
3234		printf("%02X ", Registers[REGISTER_A]);
3235		printf("%02X ", Registers[REGISTER_B]);
3236		printf("%02X ", Registers[REGISTER_C]);
3237		printf("%02X ", Registers[REGISTER_L]);
3238		printf("%02X ", Registers[REGISTER_H]);
3239		printf("%02X ", Index_Registers[REGISTER_X]);
3240		printf("%02X ", Index_Registers[REGISTER_Y]);
3241		printf("%04X ", StackPointer);              // Print Stack Pointer
3242
3243		if ((Flags & FLAG_Z) == FLAG_Z)
3244		{
3245			printf("Z=1 ");
3246		}
3247		else
3248		{
3249			printf("Z=0 ");
3250		}
3251		if ((Flags & FLAG_I) == FLAG_I)
3252		{
3253			printf("I=1 ");
3254		}
3255		else
3256		{
3257			printf("I=0 ");
3258		}
3259		if ((Flags & FLAG_N) == FLAG_N)
3260		{
3261			printf("N=1 ");
3262		}
3263		else
3264		{
3265			printf("N=0 ");
3266		}
3267		if ((Flags & FLAG_C) == FLAG_C)
3268		{
3269			printf("C=1 ");
3270		}
3271		else
3272		{
3273			printf("C=0 ");
3274		}
3275
3276		printf("\n");  // New line
3277		sanity++;
3278		if (sanity > 200) halt = true;
3279
3280	}
3281
3282	printf("\n");  // New line
3283}
3284
3285
3286////////////////////////////////////////////////////////////////////////////////
3287//                            Simulator/Emulator (End)                        //
3288////////////////////////////////////////////////////////////////////////////////
3289
3290
3291void initialise_filenames() {
3292	int i;
3293
3294	for (i = 0; i < MAX_FILENAME_SIZE; i++) {
3295		hex_file[i] = '\0';
3296		trc_file[i] = '\0';
3297	}
3298}
3299
3300
3301
3302
3303int find_dot_position(char *filename) {
3304	int  dot_position;
3305	int  i;
3306	char chr;
3307
3308	dot_position = 0;
3309	i = 0;
3310	chr = filename[i];
3311
3312	while (chr != '\0') {
3313		if (chr == '.') {
3314			dot_position = i;
3315		}
3316		i++;
3317		chr = filename[i];
3318	}
3319
3320	return (dot_position);
3321}
3322
3323
3324int find_end_position(char *filename) {
3325	int  end_position;
3326	int  i;
3327	char chr;
3328
3329	end_position = 0;
3330	i = 0;
3331	chr = filename[i];
3332
3333	while (chr != '\0') {
3334		end_position = i;
3335		i++;
3336		chr = filename[i];
3337	}
3338
3339	return (end_position);
3340}
3341
3342
3343bool file_exists(char *filename) {
3344	bool exists;
3345	FILE *ifp;
3346
3347	exists = false;
3348
3349	if ((ifp = fopen(filename, "r")) != NULL) {
3350		exists = true;
3351
3352		fclose(ifp);
3353	}
3354
3355	return (exists);
3356}
3357
3358
3359
3360void create_file(char *filename) {
3361	FILE *ofp;
3362
3363	if ((ofp = fopen(filename, "w")) != NULL) {
3364		fclose(ofp);
3365	}
3366}
3367
3368
3369
3370bool getline(FILE *fp, char *buffer) {
3371	bool rc;
3372	bool collect;
3373	char c;
3374	int  i;
3375
3376	rc = false;
3377	collect = true;
3378
3379	i = 0;
3380	while (collect) {
3381		c = getc(fp);
3382
3383		switch (c) {
3384		case EOF:
3385			if (i > 0) {
3386				rc = true;
3387			}
3388			collect = false;
3389			break;
3390
3391		case '\n':
3392			if (i > 0) {
3393				rc = true;
3394				collect = false;
3395				buffer[i] = '\0';
3396			}
3397			break;
3398
3399		default:
3400			buffer[i] = c;
3401			i++;
3402			break;
3403		}
3404	}
3405
3406	return (rc);
3407}
3408
3409
3410
3411
3412
3413
3414void load_and_run(int args, _TCHAR** argv) {
3415	char chr;
3416	int  ln;
3417	int  dot_position;
3418	int  end_position;
3419	long i;
3420	FILE *ifp;
3421	long address;
3422	long load_at;
3423	int  code;
3424
3425	// Prompt for the .hex file
3426
3427	printf("\n");
3428	printf("Enter the hex filename (.hex): ");
3429
3430	if (args == 2) {
3431		ln = 0;
3432		chr = argv[1][ln];
3433		while (chr != '\0')
3434		{
3435			if (ln < MAX_FILENAME_SIZE)
3436			{
3437				hex_file[ln] = chr;
3438				trc_file[ln] = chr;
3439				ln++;
3440			}
3441			chr = argv[1][ln];
3442		}
3443	}
3444	else {
3445		ln = 0;
3446		chr = '\0';
3447		while (chr != '\n') {
3448			chr = getchar();
3449
3450			switch (chr) {
3451			case '\n':
3452				break;
3453			default:
3454				if (ln < MAX_FILENAME_SIZE) {
3455					hex_file[ln] = chr;
3456					trc_file[ln] = chr;
3457					ln++;
3458				}
3459				break;
3460			}
3461		}
3462
3463	}
3464	// Tidy up the file names
3465
3466	dot_position = find_dot_position(hex_file);
3467	if (dot_position == 0) {
3468		end_position = find_end_position(hex_file);
3469
3470		hex_file[end_position + 1] = '.';
3471		hex_file[end_position + 2] = 'h';
3472		hex_file[end_position + 3] = 'e';
3473		hex_file[end_position + 4] = 'x';
3474		hex_file[end_position + 5] = '\0';
3475	}
3476	else {
3477		hex_file[dot_position + 0] = '.';
3478		hex_file[dot_position + 1] = 'h';
3479		hex_file[dot_position + 2] = 'e';
3480		hex_file[dot_position + 3] = 'x';
3481		hex_file[dot_position + 4] = '\0';
3482	}
3483
3484	dot_position = find_dot_position(trc_file);
3485	if (dot_position == 0) {
3486		end_position = find_end_position(trc_file);
3487
3488		trc_file[end_position + 1] = '.';
3489		trc_file[end_position + 2] = 't';
3490		trc_file[end_position + 3] = 'r';
3491		trc_file[end_position + 4] = 'c';
3492		trc_file[end_position + 5] = '\0';
3493	}
3494	else {
3495		trc_file[dot_position + 0] = '.';
3496		trc_file[dot_position + 1] = 't';
3497		trc_file[dot_position + 2] = 'r';
3498		trc_file[dot_position + 3] = 'c';
3499		trc_file[dot_position + 4] = '\0';
3500	}
3501
3502	if (file_exists(hex_file)) {
3503		// Clear Registers and Memory
3504
3505		Registers[REGISTER_A] = 0;
3506		Registers[REGISTER_B] = 0;
3507		Registers[REGISTER_C] = 0;
3508		Registers[REGISTER_L] = 0;
3509		Registers[REGISTER_H] = 0;
3510		Index_Registers[REGISTER_X] = 0;
3511		Index_Registers[REGISTER_Y] = 0;
3512		Flags = 0;
3513		ProgramCounter = 0;
3514		StackPointer = 0;
3515
3516		for (i = 0; i < MEMORY_SIZE; i++) {
3517			Memory[i] = 0x00;
3518		}
3519
3520		// Load hex file
3521
3522		if ((ifp = fopen(hex_file, "r")) != NULL) {
3523			printf("Loading file...\n\n");
3524
3525			load_at = 0;
3526
3527			while (getline(ifp, InputBuffer)) {
3528				if (sscanf(InputBuffer, "L=%x", &address) == 1) {
3529					load_at = address;
3530				}
3531				else if (sscanf(InputBuffer, "%x", &code) == 1) {
3532					if ((load_at >= 0) && (load_at <= MEMORY_SIZE)) {
3533						Memory[load_at] = (BYTE)code;
3534					}
3535					load_at++;
3536				}
3537				else {
3538					printf("ERROR> Failed to load instruction: %s \n", InputBuffer);
3539				}
3540			}
3541
3542			fclose(ifp);
3543		}
3544
3545		// Emulate
3546
3547		emulate();
3548	}
3549	else {
3550		printf("\n");
3551		printf("ERROR> Input file %s does not exist!\n", hex_file);
3552		printf("\n");
3553	}
3554}
3555
3556void building(int args, _TCHAR** argv) {
3557	char buffer[1024];
3558	load_and_run(args, argv);
3559	sprintf(buffer, "0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X",
3560		Memory[TEST_ADDRESS_1],
3561		Memory[TEST_ADDRESS_2],
3562		Memory[TEST_ADDRESS_3],
3563		Memory[TEST_ADDRESS_4],
3564		Memory[TEST_ADDRESS_5],
3565		Memory[TEST_ADDRESS_6],
3566		Memory[TEST_ADDRESS_7],
3567		Memory[TEST_ADDRESS_8],
3568		Memory[TEST_ADDRESS_9],
3569		Memory[TEST_ADDRESS_10],
3570		Memory[TEST_ADDRESS_11],
3571		Memory[TEST_ADDRESS_12]
3572	);
3573	sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
3574}
3575
3576
3577
3578void test_and_mark() {
3579	char buffer[1024];
3580	bool testing_complete;
3581	int  len = sizeof(SOCKADDR);
3582	char chr;
3583	int  i;
3584	int  j;
3585	bool end_of_program;
3586	long address;
3587	long load_at;
3588	int  code;
3589	int  mark;
3590	int  passed;
3591
3592	printf("\n");
3593	printf("Automatic Testing and Marking\n");
3594	printf("\n");
3595
3596	testing_complete = false;
3597
3598	sprintf(buffer, "Test Student %s", STUDENT_NUMBER);
3599	sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
3600
3601	while (!testing_complete) {
3602		memset(buffer, '\0', sizeof(buffer));
3603
3604		if (recvfrom(sock, buffer, sizeof(buffer) - 1, 0, (SOCKADDR *)&client_addr, &len) != SOCKET_ERROR) {
3605			printf("Incoming Data: %s \n", buffer);
3606
3607			//if (strcmp(buffer, "Testing complete") == 1)
3608			if (sscanf(buffer, "Testing complete %d", &mark) == 1) {
3609				testing_complete = true;
3610				printf("Current mark = %d\n", mark);
3611
3612			}
3613			else if (sscanf(buffer, "Tests passed %d", &passed) == 1) {
3614				//testing_complete = true;
3615				printf("Passed = %d\n", passed);
3616
3617			}
3618			else if (strcmp(buffer, "Error") == 0) {
3619				printf("ERROR> Testing abnormally terminated\n");
3620				testing_complete = true;
3621			}
3622			else {
3623				// Clear Registers and Memory
3624
3625				Registers[REGISTER_A] = 0;
3626				Registers[REGISTER_B] = 0;
3627				Registers[REGISTER_C] = 0;
3628				Registers[REGISTER_L] = 0;
3629				Registers[REGISTER_H] = 0;
3630				Index_Registers[REGISTER_X] = 0;
3631				Index_Registers[REGISTER_Y] = 0;
3632				Flags = 0;
3633				ProgramCounter = 0;
3634				StackPointer = 0;
3635				for (i = 0; i < MEMORY_SIZE; i++) {
3636					Memory[i] = 0;
3637				}
3638
3639				// Load hex file
3640
3641				i = 0;
3642				j = 0;
3643				load_at = 0;
3644				end_of_program = false;
3645				FILE *ofp;
3646				fopen_s(&ofp, "branch.txt", "a");
3647
3648				while (!end_of_program) {
3649					chr = buffer[i];
3650					switch (chr) {
3651					case '\0':
3652						end_of_program = true;
3653
3654					case ',':
3655						if (sscanf(InputBuffer, "L=%x", &address) == 1) {
3656							load_at = address;
3657						}
3658						else if (sscanf(InputBuffer, "%x", &code) == 1) {
3659							if ((load_at >= 0) && (load_at <= MEMORY_SIZE)) {
3660								Memory[load_at] = (BYTE)code;
3661								fprintf(ofp, "%02X\n", (BYTE)code);
3662							}
3663							load_at++;
3664						}
3665						else {
3666							printf("ERROR> Failed to load instruction: %s \n", InputBuffer);
3667						}
3668						j = 0;
3669						break;
3670
3671					default:
3672						InputBuffer[j] = chr;
3673						j++;
3674						break;
3675					}
3676					i++;
3677				}
3678				fclose(ofp);
3679				// Emulate
3680
3681				if (load_at > 1) {
3682					emulate();
3683					// Send and store results
3684					sprintf(buffer, "%02X%02X %02X%02X %02X%02X %02X%02X %02X%02X %02X%02X",
3685						Memory[TEST_ADDRESS_1],
3686						Memory[TEST_ADDRESS_2],
3687						Memory[TEST_ADDRESS_3],
3688						Memory[TEST_ADDRESS_4],
3689						Memory[TEST_ADDRESS_5],
3690						Memory[TEST_ADDRESS_6],
3691						Memory[TEST_ADDRESS_7],
3692						Memory[TEST_ADDRESS_8],
3693						Memory[TEST_ADDRESS_9],
3694						Memory[TEST_ADDRESS_10],
3695						Memory[TEST_ADDRESS_11],
3696						Memory[TEST_ADDRESS_12]
3697					);
3698					sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
3699				}
3700			}
3701		}
3702	}
3703}
3704
3705
3706
3707int _tmain(int argc, _TCHAR* argv[])
3708{
3709	char chr;
3710	char dummy;
3711
3712	printf("\n");
3713	printf("Microprocessor Emulator\n");
3714	printf("UWE Computer and Network Systems Assignment 1\n");
3715	printf("\n");
3716
3717	initialise_filenames();
3718
3719	if (WSAStartup(MAKEWORD(2, 2), &data) != 0) return(0);
3720
3721	sock = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP);  // Here we create our socket, which will be a UDP socket (SOCK_DGRAM).
3722	if (!sock) {
3723		// Creation failed!
3724	}
3725
3726	memset(&server_addr, 0, sizeof(SOCKADDR_IN));
3727	server_addr.sin_family = AF_INET;
3728	server_addr.sin_addr.s_addr = inet_addr(IP_ADDRESS_SERVER);
3729	server_addr.sin_port = htons(PORT_SERVER);
3730
3731	memset(&client_addr, 0, sizeof(SOCKADDR_IN));
3732	client_addr.sin_family = AF_INET;
3733	client_addr.sin_addr.s_addr = inet_addr("127.0.0.1");
3734	client_addr.sin_port = htons(PORT_CLIENT);
3735
3736	chr = '\0';
3737	while ((chr != 'e') && (chr != 'E'))
3738	{
3739		printf("\n");
3740		printf("Please select option\n");
3741		printf("L - Load and run a hex file\n");
3742		printf("T - Have the server test and mark your emulator\n");
3743		printf("E - Exit\n");
3744		if (argc == 2) { building(argc, argv); exit(0); }
3745		printf("Enter option: ");
3746		chr = getchar();
3747		if (chr != 0x0A)
3748		{
3749			dummy = getchar();  // read in the <CR>
3750		}
3751		printf("\n");
3752
3753		switch (chr)
3754		{
3755		case 'L':
3756		case 'l':
3757			load_and_run(argc, argv);
3758			break;
3759
3760		case 'T':
3761		case 't':
3762			test_and_mark();
3763			break;
3764
3765		default:
3766			break;
3767		}
3768	}
3769
3770	closesocket(sock);
3771	WSACleanup();
3772
3773
3774	return 0;
3775}