· 8 years ago · Apr 03, 2018, 06:06 PM
1/*
2 * (C) Copyright 2018 Chris Blake <chrisrblake93 at gmail.com>
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without
6 * any warranty of any kind, whether express or implied.
7 */
8
9#include <common.h>
10#include <watchdog.h>
11#include <asm/arch/timer.h>
12#include <asm/io.h>
13
14#define WDT_CTRL_RESTART (0x1 << 0)
15#define WDT_CTRL_KEY (0x0a57 << 1)
16#define WDT_MODE_EN (0x1 << 0)
17#define WDT_TIMEOUT_MASK (0xf)
18
19struct sunxi_wdt_reg {
20 u32 wdt_ctl;
21 u32 wdt_cfg;
22 u32 wdt_mode;
23 u32 wdt_reset_mask;
24 u32 wdt_reset_mode;
25};
26
27static const struct sunxi_wdt_reg sun4i_wdt_reg = {
28 .wdt_ctrl = 0x00,
29 .wdt_cfg = 0x04,
30 .wdt_mode = 0x04,
31 .wdt_timeout_shift = 3,
32 .wdt_reset_mask = 0x02,
33 .wdt_reset_val = 0x02,
34};
35
36static const struct sunxi_wdt_reg sun6i_dog_regs = {
37 .wdt_ctrl = 0x10,
38 .wdt_cfg = 0x14,
39 .wdt_mode = 0x18,
40 .wdt_timeout_shift = 4,
41 .wdt_reset_mask = 0x03,
42 .wdt_reset_val = 0x01,
43};
44
45static const int wdt_timeout_map[] = {
46 [1] = 0x1, /* 1s */
47 [2] = 0x2, /* 2s */
48 [3] = 0x3, /* 3s */
49 [4] = 0x4, /* 4s */
50 [5] = 0x5, /* 5s */
51 [6] = 0x6, /* 6s */
52 [8] = 0x7, /* 8s */
53 [10] = 0x8, /* 10s */
54 [12] = 0x9, /* 12s */
55 [14] = 0xA, /* 14s */
56 [16] = 0xB, /* 16s */
57};
58
59static const struct sunxi_wdt_reg *regs = &sun6i_dog_regs;
60
61static void *wdt_base = &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
62
63void hw_watchdog_reset(void)
64{
65 /* reload the watchdog */
66 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, wdt_base + regs->wdt_ctrl);
67}
68
69void hw_watchdog_disable(void)
70{
71 /* Reset WDT Config */
72 writel(0, wdt_base + regs->wdt_mode);
73}
74
75void hw_watchdog_init(void)
76{
77 const u32 timeout = CONFIG_SUNXI_WDT_TIMEOUT;
78 u32 reg;
79
80 reg = readl(wdt_base + regs->wdt_mode);
81 reg &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
82 reg |= wdt_timeout_map[timeout] << regs->wdt_timeout_shift;
83 writel(reg, wdt_base + regs->wdt_mode);
84
85 hw_watchdog_reset();
86
87 /* Set system reset function */
88 reg = readl(wdt_base + regs->wdt_cfg);
89 reg &= ~(regs->wdt_reset_mask);
90 reg |= regs->wdt_reset_val;
91 writel(reg, wdt_base + regs->wdt_cfg);
92
93 /* Enable watchdog */
94 reg = readl(wdt_base + regs->wdt_mode);
95 reg |= WDT_MODE_EN;
96 writel(reg, wdt_base + regs->wdt_mode);
97 }