L5mzS6MT

1CCRs Fixed in Release 19.1 ISR1
2================================================
3CCMPR02122206	Crash in read_def with 19.11
4CCMPR02122181	Unable to run floorplanning
5CCMPR02120749	User set timing derates are getting overwritten
6CCMPR02119829	scandef errors while restoring flattened ILM DB
7CCMPR02118446	Innovus 19.10 is locking up during ccopt_design CUI
8CCMPR02118241	selectInst crashes in 19.11_e088
9CCMPR02116891	Fatal crash during place_opt_design with Innovus 19.11-e081_1
10CCMPR02115286	place_opt crashing during scheduling file restore in ECF
11CCMPR02114856	Coloring is crashing at NR::sort_inst() on one of the designs
12CCMPR02114633	The add_fillers command causes Innovus 19.1 to hang for customer in tapeout. Works with 18.13-s088_1.
13CCMPR02113715	select_bump -net <netname> is not selecting the corresponding bumps
14CCMPR02112033	SEGV on a design
15CCMPR02111670	detachTerm SEGV due to user usage error
16CCMPR02111184	place_opt_design -opt crashes after SKP initialization
17CCMPR02110538	assignPtnPin SEGV
18CCMPR02110373	optDesign got crashed at spsInstMapLLG::getContextDemandInRange
19CCMPR02110294	Nanoroute creates patch wires on _SADP_FILLS_RESERVED in N5 node
20CCMPR02109985	Innovus crashed in optimization during DrvOpt
21CCMPR02109757	SEGV during "routeDesign -trackOpt"
22CCMPR02108858	Run eGR for better congestion prediction
23CCMPR02108852	Timing still jumps a lot if redo full eGR-steiner with incr-eGR-steiner on
24CCMPR02108281	Innovus does not connect supply pins from apply_power_model -supply_map
25CCMPR02107699	Crash at the AddStripe command
26CCMPR02107624	1911 place_opt_design crash
27CCMPR02107247	Early global router bad clock routing with NDR tracks defined
28CCMPR02106808	fterm location changed after write_db and then read_db
29CCMPR02106711	SEGV during iSpatial
30CCMPR02106530	Tool crash at dbsStripBoxGroupMgr::iterator globalDetailRoute due to missing power connection in netlist
31CCMPR02105917	18.13 CCOpt SEGV on "RefinePlaceCaller::ReportMovementHelper(const InstRec& instRec,"
32CCMPR02105502	saveDesign crashing with 19.1-p002_1
33CCMPR02105497	addEndCap crashing randomly in mixed placer flow with 19.11
34CCMPR02105432	**WARN: (IMPSC-1026): Instance pin %s connects to net %s with multiple (5) drivers
35CCMPR02104875	place_opt_design crash
36CCMPR02104801	19.11 postcts crash before hold fixing
37CCMPR02104799	19.11 report_power crash
38CCMPR02104685	Innovus crash in place_opt_design 18.13 CUI
39CCMPR02104677	Innovus crash with placeInstance of large delay cell
40CCMPR02104565	Innovus crashing right after checkFPlan with 19.11
41CCMPR02104540	Crash during routeDesign
42CCMPR02104528	Bus Planning - place_opt_design adds buffers outside busGuide
43CCMPR02104489	Design load crashing in 18.15
44CCMPR02103946	eco_oa_design gives error in 18.14
45CCMPR02103187	UPF file duplication lines on set_iso*
46CCMPR02102533	Need Secondary PG connection to extend top stripe to switch cell pin
47CCMPR02102523	Tool crashes during the optDesign -postCTS command
48CCMPR02102514	verify_drc reports a false EOL-Keepout violation
49CCMPR02102399	earlyGlobalRoute crashed due to user's incorrect -earlyGlobalMinRouteLayer setting
50CCMPR02102357	Innovus is unable to generate DRC clean multicut power vias
51CCMPR02102330	Power routing is not adding vias in 18.14-e070 and later
52CCMPR02101742	signoffTimeDesign command is checking out two Tempus licenses when only one is required
53CCMPR02101735	Tempus eco crash during drv optimziation
54CCMPR02101728	Filler node crashing while executing the verifyLitho command
55CCMPR02101712	Crash during global placement
56CCMPR02101422	Need help on Tempus TSO tool crash during invocation of eco_opt_design -hold
57CCMPR02101155	savePartition crash in 19.71-e003
58CCMPR02101131	Crash during routeDesign -highFrequency
59CCMPR02101005	Innovus crash with globalDetailRoute during the Route stage
60CCMPR02100922	SEGV when "place_opt_design -no_pre_place_opt" from iSpatial DB
61CCMPR02099805	M4 EOL keepout violations
62CCMPR02099791	M2 EOL keepout violations
63CCMPR02099754	Place stage in ccopt_design command crash
64CCMPR02099753	routeDesign reports ERROR: NR History Map is not available in dbs
65CCMPR02099708	optDesign postRoute timing difference between fullDC timing and optimization
66CCMPR02099683	**ERROR: (IMPTCM-4) happens in create_proto_model
67CCMPR02099655	Extraction crashes when running report_timing in 19.71-e003_1
68CCMPR02099500	place_opt_design hangs after issuing **WARN: (IMPSP-9089): Feature 'LEF ROWPATTERN' is obsolete
69CCMPR02099187	Utilization test - EGR correlation
70CCMPR02099049	TQuantus crash inside routeDesign
71CCMPR02099034	Editpowervia creates M2 Same metal aligned cut violations with cell geometries
72CCMPR02098961	FC route leaving a mess for some bumps when solution seems simple
73CCMPR02098657	Improve grid coarsening heuristic in line with suggestions for CCR 2089602
74CCMPR02098412	routeDesign crash
75CCMPR02098384	write_floorplan_script does not write out the same location for bump in tcl as create_bump -location issued
76CCMPR02098318	Crash during saveDesign
77CCMPR02097764	Crash during place_opt_design using 19.11
78CCMPR02097660	Negative shielding ratio is being reported during the clock stage
79CCMPR02097472	Innovus 171 routeDesign segmentation fault
80CCMPR02096845	Very high runtime of ~36hrs for first areaReclaim call in place_opt_design
81CCMPR02096512	19.11 postRoute DrvOpt NBF transform high CPU time due to forward depth 2 sub timing graph eval
82CCMPR02096495	19.11 postRoute DrvOpt Resize transform high CPU time due to large sub timing graph size
83CCMPR02096476	Update to latest UPF parser (d016)
84CCMPR02095873	SEGV Crash at refine place after DRV optimization
85CCMPR02095823	Incorrect consideration for top and bottom rects of standard via variant
86CCMPR02095681	optDesign utilizes incorrect MBFF cells from library binding in MSV design
87CCMPR02095557	optDesign -postCTS crashes with 18.14-e058_1
88CCMPR02095543	Fatal ERROR when trying to run ecoAddRepeater
89CCMPR02095542	ecoRoute not called after refine place within postroute opt
90CCMPR02095007	When using ORIENT syntax to TLEF, layer via is ignored in IMPLF-420
91CCMPR02094945	SEGV during place initial on a design
92CCMPR02094940	ecoRoute not fixing via0 violations
93CCMPR02094916	NanoRoute: further improvement on fixing false EOL and trim violations
94CCMPR02094830	Crash during routeDesign -trackOpt
95CCMPR02094692	Innovus crashing while running the ecoAddRepeater command
96CCMPR02094140	assignPtnPin SEGV
97CCMPR02094112	Restricted size-only constraint not honored for some cases during preCTS optimization
98CCMPR02094063	SEGV during place_opt_design -phys_syn
99CCMPR02094036	CUI equivalent of legacy command setNanoRouteMode -drouteCheckMarOnCellPin
100CCMPR02093958	Pins not aligning with align pin. Choosing closer edge rather than aligning
101CCMPR02093491	flip_chip_router causes SEGV using 19.11-e044_1
102CCMPR02093320	addStripe failed to create M4 PG stripes cross the whole core area correctly
103CCMPR02092585	SaveDesign Error out with **ERROR: (IMPSYC-1919)**
104CCMPR02092437	Routing runtime not competitive
105CCMPR02092108	MBF mapping file is incorrect after split
106CCMPR02092095	Crash during routeDesign in a design
107CCMPR02091794	Incorrect delay calculation in IO PG lib
108CCMPR02091657	SEGV during ecoRoute - Extracting RC
109CCMPR02091577	ccopt_design continues to leave transition violations
110CCMPR02091559	Nanoroute crashes when loading APA file
111CCMPR02091370	SEGV during extractRC in postroute top-level DB
112CCMPR02091063	Bug fix for pgFill -fixIsoVia support
113CCMPR02090673	SEGV during route
114CCMPR02090323	Innovus 19.1 Crash during place_opt
115CCMPR02090170	Crash during the placeopt stage when customer is trying custom buffering
116CCMPR02089616	Passive fill generates DRC violations
117CCMPR02089524	19.11: postRoute TNS opt NBF CPU time is high comparing to other transform due to too many legal loc check
118CCMPR02089507	read_parasitics failing to read its own written rcdb file under routeDesign -trackOpt
119CCMPR02089402	Crash in delay calculation in optDesign -postRoute
120CCMPR02089181	WidthTable Violation
121CCMPR02089048	Macro poly DRC violation in mixed mode
122CCMPR02088394	Innovus 19.11-e024_1 First ecoRoute in optDesign -postRoute has SEGV
123CCMPR02088301	19.11: Too many refinePlace were called even no non-legal commit during optimization in postroute opt
124CCMPR02088217	"Non-pin * cannot be skew_group sink" messages related to multibit flops during ccopt_design
125CCMPR02087923	postCTS hold fixing crashes with SEGV
126CCMPR02087717	Crash during eco Implementation
127CCMPR02087647	globalDetailRoute SEGV while restoring pin access data from .apa file
128CCMPR02087294	saveDesign crashes after postroute optimization with the ILM-based flow
129CCMPR02087027	Make passivation layer independent to other layers
130CCMPR02086273	Innovus 1801 output has -update {} and -supply {} which make the output unreadable
131CCMPR02086023	GUI hang after gui_highlight gui_show
132CCMPR02085574	GUI display speed status will auto change
133CCMPR02085341	Nanoroute does not appear to be using METALWIDTHVIAMAP for MUSTJOIN connections
134CCMPR02085302	chip_top "ecoRoute" stuck for 15hrs at a step of marking dirty area
135CCMPR02085254	Enhancement request to elaborate the path groups in the timeDesign summary
136CCMPR02085242	IMM crash in 19.11e036
137CCMPR02084614	Crash during ccopt_design -cts
138CCMPR02084601	NR leaving mustjoin pins disconnected
139CCMPR02084589	Off Trim Grid Vioation
140CCMPR02084571	19.11: Hold don't touch marking is taking long time
141CCMPR02084455	Crash observed during saveDesign
142CCMPR02084341	Crash during eco commands
143CCMPR02084324	SMAC violation after postRoute pg hook-up
144CCMPR02083810	19.11 SEGV at esiDcalc::createMultiDrvTask
145CCMPR02083788	AssignIOPin not assigning clock pin with ECF
146CCMPR02083751	pgFill -fix_iso_via crashes with multicpu
147CCMPR02083393	Post-route optimization tool crash
148CCMPR02083234	Innovus apply_port_map does not reconnect ports connected to constants
149CCMPR02083132	Support halo placement for "even height" block sizes
150CCMPR02082651	freeDesign does not clear via information by add_via_definition
151CCMPR02082510	Multi-Bit cells not being inferred by Innovus
152CCMPR02082402	addRing fails with IMPPP-4051 if the ring is generated to align with block boundary
153CCMPR02082146	18.14: place_opt_design with early clock flow SEGV
154CCMPR02082039	19.11 crash during ccopt_design -check_prerequisites
155CCMPR02081781	Tool crashes during oaIn
156CCMPR02081636	place_opt_design crash in optDesign phase
157CCMPR02081585	18.1/19.1 scanTrace after place_opt_design gives warn of IMPSC-1151
158CCMPR02081556	end_parallel_edit comes out with SEGV
159CCMPR02081382	HardenOpt is taking 40 minutes without any commit in postroute opt
160CCMPR02081292	 18.1/19.1 scanTrace gives warn 1138 if run twice
161CCMPR02081233	Crash reported during saveDesign in the floorplan stage
162CCMPR02080914	Tool crash running verifyPowerDomain
163CCMPR02080803	There was a short between M2 two pins of a cell placed next to the PG stripe
164CCMPR02080792	The field "pin group" is not updated automatically in pin Editor 
165CCMPR02080777	Trim to trim spacing violation
166CCMPR02080736	Missing inserted routing trim on top of pre-defined cell trim OBS
167CCMPR02080717	Crash during oaIn with different cell name with design cell
168CCMPR02080455	Need improvement for total fullDC runtime
169CCMPR02080369	NRHF crash while routing 6K nets
170CCMPR02079728	New off trim grid violations with NR
171CCMPR02079659	Enhance moderate PG via insertion to align vias instead of using checkboard pattern
172CCMPR02079374	NRHF crash ExportRipin
173CCMPR02079337	Tie cell addition fails for many pins after taking 15+ hours, keep on applying GNCs in loop
174CCMPR02078612	tQuantus is not honoring layer based RC scaling on SEC10
175CCMPR02078459	summaryReport -outDir does not output all files into the specified outdir
176CCMPR02078420	addStripe with stapling style will not generate full expected for M4 in channel
177CCMPR02078095	Innovus not able to support CPF input/ouput_domain options in create_level_shifter_rule
178CCMPR02078075	place_opt_design uses wrong clock_latency value
179CCMPR02077863	Unacceptable CTS memory/runtime tracing a macro with complex internal structure
180CCMPR02077830	Manual ICG sizing leads to better postCTS QoR compared to default skewClock sizing
181CCMPR02077823	ccopt_design error out with "MT ERROR" messages
182CCMPR02077284	apply_power_model -port_map not making connections
183CCMPR02077263	setTopCell command is crashing when invoked from GUI
184CCMPR02077202	Incorrect mbit naming by Innovus causing NEQs in LEC
185CCMPR02077100	Need Max Layer control for Shield tapping
186CCMPR02077099	place_opt_design crash with 19.11
187CCMPR02076922	Sspecial-via search box too small when considering altered pre-existing metal-shapes. Leads to drc errors
188CCMPR02076860	Need GUI enhancement for adding zoomTo -radius option
189CCMPR02076566	CCOpt Halos not being applied to clock roots
190CCMPR02076515	M2 EOL violation not flagged by verify_drc
191CCMPR02076308	19.1 qor degradation when compared to 18.12
192CCMPR02076247	VIA2 spacing violations within Invs18.14
193CCMPR02076112	Innovus does not connect supply nets properly when apply_power_model is used
194CCMPR02076099	saveDesign cannot override the starting DBS when setOaxMode -locking true
195CCMPR02075993	M1 shorts seen during Nano route
196CCMPR02075786	verifyConnectivity detects open error at net accessing pins as feedthrough
197CCMPR02075746	Large increatse in routing DRCs when enabling passive fill
198CCMPR02075577	trimDesign getting stuck in Innovus 19.10-b706_1
199CCMPR02075445	Power bump routing using fcroute
200CCMPR02075429	Massive detour for a net on critical path
201CCMPR02075313	One pass run with preCTS useful skew run progress is very slow
202CCMPR02075239	ecoRoute in distributed mode flags false adjacent cut violations not seen in non-distributed mode
203CCMPR02075160	Dangling wires left after ecoRoute in 18.14_e043_1
204CCMPR02075154	Crash while NR starts routing of the clock nets during ccopt_design
205CCMPR02074980	fcroute shorts and opens
206CCMPR02074966	fcroute taps wrong VSSO pin
207CCMPR02074539	18.11-s100_1 crash when running "get_lib_clock_tree_path_delay"
208CCMPR02074460	M1 routing under X1 trim layer
209CCMPR02074300	ccopt_design hang during clustering
210CCMPR02074069	addStripe causing segmentation fault when "-power_domains" is specified
211CCMPR02073996	19.10 routeDesign 30% peak memory degradation compared to 18.12
212CCMPR02073717	Pin access analysis takes 7 hours in one cell
213CCMPR02073681	NRHF crash, CheckPinAccess
214CCMPR02073600	Innovus gets confused about colors when importing from display.drf
215CCMPR02073498	Huge DRC jump at the end of optDesign -postRoute
216CCMPR02073423	CTD SEGV selecting Constraints - dont touch on clock mesh design
217CCMPR02073380	delete_dangling_port introduce error IMPSYC-1919
218CCMPR02073245	SEGV during route_secondary_pg_pins in timing_driven
219CCMPR02073054	_SADP_FILLS_RESERVED is written to Netlist
220CCMPR02072973	checkPlace/place_opt_design reporting false pin access violations
221CCMPR02072971	DIAG in 18.13-s088_1 
222CCMPR02072915	place_opt_design not honoring selective sizeonly for all the specified instances
223CCMPR02072913	Incorrect error message for 'addStripe -power_domains' and inconsistent behavior between multi/single PD
224CCMPR02072886	trackOpt seeing very optimistic timing compared to postRouteOpt - 90nm
225CCMPR02072858	addStripe creates euclidean spacing violations to 45-degree edges of bumps
226CCMPR02072754	Missing VIA definition in DEF
227CCMPR02072685	ERROR: (internal Tcl error) 'invalid command name "cbGet"
228CCMPR02072464	This switch "-usePostCTSHighFanoutNetFixing" is still leaving some HFN unfixed during postcts
229CCMPR02072308	Slack changes after reset_path_group
230CCMPR02072224	User gets repeatable stack trace when selecting an IO pad
231CCMPR02072197	editAddRoute does not honor assign multi pattern color
232CCMPR02072146	place_opt_design crash
233CCMPR02071689	Innovus 1801 3.0: invalid command name "::MSV_UPF::define_power_model"
234CCMPR02071682	addTieHiLo creates a new net with empty props
235CCMPR02071594	FlexILM for blocks does not show partition pins in Hierarchical DB when block pins have PLACED status.
236CCMPR02071430	ICG pin alignment not having pins aligned
237CCMPR02071161	SEGV during saveDesign in 19.10-b706_1
238CCMPR02071129	Wire spreading causes lots of DRC in "LEF58_EOLEXTENSIONSPACING"
239CCMPR02070901	19.1 code bash: routeDesign left more than 1000 DRCs on M3/M4 in 19.1 compared to 18.1
240CCMPR02070851	PSW enable In/Out pin are not in ALWAYS ON power domain
241CCMPR02070822	Miss out PA violation Hybrid row flow
242CCMPR02070754	Seeing NRDB-671 warning that PG nets are not routed in 19.10-b706
243CCMPR02070725	Router hang on a testcase
244CCMPR02070681	SEGV during timing optimization under power reclaim
245CCMPR02069894	Star router using 19.11-e010 results in 44 opens where it can be resolved manually
246CCMPR02069870	fixCellEMViolation can NOT fix all violation due to NoViewFound ERROR reason
247CCMPR02069867	deleteFiller -inst print out messages for each deleted filler cells
248CCMPR02069497	Crash during optDesign -postRoute on chip level
249CCMPR02069357	addRepeaterByRule is not buffering some nets
250CCMPR02069314	report_metric should use the id itself as a tag name while comparing multiple metrics instead of "G" "T1"
251CCMPR02069267	ECF not able to identify all ICGs with multi driver net
252CCMPR02069237	Large TAT and memory jump during postCtsHold due to high fanout net from place_opt
253CCMPR02069186	UseMultiCutViaEffort hard - Huge runtime and DRC viols because NR does not use appropriate VIA12 vias
254CCMPR02069052	Problem of memory in deleteRouteBlk
255CCMPR02069016	skewClock should support ICG sizing having ICG clock pins connected to multi driven net
256CCMPR02068981	place_opt_design -place takes longer runtime during global placement
257CCMPR02068863	ccopt_design should accept ILM model type "SI" and just use the data it needs
258CCMPR02068721	CCOPT crash in cell filtering
259CCMPR02068527	delete_assign issues false warning since no new instance/net are created
260CCMPR02068257	Crash during ecoRoute for FE Block
261CCMPR02068186	optDesign is coming out with illegal placement
262CCMPR02068129	Stack trace a flattenPartition
263CCMPR02068105	via pillars create short with M2 cell blockage
264CCMPR02068057	refinePlace hanging again, not finding legal locations for cells due to "Other"
265CCMPR02068045	'colorizePowerMesh' crashed with 18.14-e033_1
266CCMPR02067999	Stack trace during DRV optimization at Postroute
267CCMPR02067997	Innovus route stage end up with many un-routed (open net)
268CCMPR02067401	Very long runtime of global route during ecoRoute
269CCMPR02067384	displayScanChain does not work in an interactive session
270CCMPR02067381	Unnecessary jogs during FlexH routing
271CCMPR02066879	reportVtInstCount is giving stack trace
272CCMPR02066708	High Runtime during detail route
273CCMPR02066646	Sizing in "skewClock -postRoute" is not honoring "set_ccopt_property buffer_cells { ..} -clock_tree"
274CCMPR02066621	NanoRoute leaves fixable Cut Short violations
275CCMPR02066461	Runtime consumed by checking antenna on constant nets
276CCMPR02066079	Routing DRC caused by via pillars during postRoute Opt
277CCMPR02066026	Stack trace at the start of Postroute while restoring markers from Route Db 
278CCMPR02065956	Checkplace reports false TPO violations after filler insertion
279CCMPR02065949	Secondary PG for merged nwell ignores some un-connected pins (with log message)
280CCMPR02065944	SEGV on IMPSP-2031 error message during place_connected
281CCMPR02065885	Tool hangs at the gen_net of droute during via pillar insertion
282CCMPR02065879	18.13e070 exits with synthesize_flexible_htrees command without completing htree routes, errors with 18.13e050
283CCMPR02065638	Innovus false forbidden spacing My.S.27 violation
284CCMPR02065573	Crash in top-level postcts_hold (ilm design)
285CCMPR02065317	Route hangs
286CCMPR02065062	Fail to route net in region. Set net to open
287CCMPR02065046	Target-based Opt file has parsing error with bit slice name
288CCMPR02064996	ccopt_design -cts stage crashes during the clustering stage
289CCMPR02064583	ccopt_design hangs
290CCMPR02064372	Detail routing initial DRC count is very high without the option '-routeEcoOnlyInLayers'
291CCMPR02064336	Issues when importing Virtuoso colors into Innovus
292CCMPR02064293	place_connected not placing ICG close to macro
293CCMPR02064292	Antenna diodes placed in incorrect power domain during routeDesign
294CCMPR02064190	verify_drc segfaults with 18.1x
295CCMPR02064153	pdzgSetNbInfoMC() SEGV.
296CCMPR02063566	signoff extraction is not working in 18.13 & 17.16 - same scripts worked OK in 17.15
297CCMPR02063550	route_details is resulting in false trim OBS short violations
298CCMPR02063543	SEGV during editPowerVia
299CCMPR02063528	NR is reporting off trim grid violations that are not real
300CCMPR02063420	Error while restoring the design
301CCMPR02063403	Crash in Global Placement
302CCMPR02063022	OPT uses much less via pillars when cut class for STACKVIARULE is not defined in rule LEF
303CCMPR02062972	1801 produces error IMPDB-1207 when supply set is not fully defined before apply_power_model
304CCMPR02062862	Long runtime of "editDelete -net" command
305CCMPR02062538	NanoRoute SEGV
306CCMPR02062475	17.1 & 18.1: Crash in post-route opt (CCOpt) from coePostCommitDelayUpdater / CompressedWave, ground voltage is not 0
307CCMPR02062301	Buffering issue due to Iso cells missing in Innovus Stylus
308CCMPR02062186	ecoRoute stops with #ERROR (NRDB-158) Missing via
309CCMPR02061999	SEGV while doing GUI edits
310CCMPR02061944	addFiller not able to insert double height cell
311CCMPR02061900	SEC10 preRoute extraction miscorrelation
312CCMPR02061887	addStripe breaks stripe at selected even when -break_at set to none when power domains exist in design
313CCMPR02061828	Secondary PG pin routing setup does not get saved when Tie cells are not part of Prects Db
314CCMPR02061821	Still difference between timing seen by optimization and timing command
315CCMPR02061152	mesh_vias are not added on the top/bottom 2 rows
316CCMPR02061150	Sstack trace generated during check_design
317CCMPR02061038	Core dumped at ediPowerVia
318CCMPR02060787	Attribute editor should have the editChangeNet -to <net_name> GUI enhancement
319CCMPR02060716	Stack trace while saving OA design after Routing (Stylus)
320CCMPR02060711	Enhancement to enforce row numbers in block and between macros to be multiples of 4
321CCMPR02060651	N/A reported in Expanded views if "ignorePathGroupsForHold {in2reg reg2out in2out default}" specified w/o creating the path group
322CCMPR02060537	Add new option "-specify_cut_class" for user to specify cut class by cut layer
323CCMPR02060307	ccopt_design crashes
324CCMPR02060288	CTS HTree crash
325CCMPR02060249	4 chip_top "optDesign -postRoute -drv" long runtime
326CCMPR02060219	Huge runtime during macro checker
327CCMPR02060201	Innovus is crashing during ecoRoute
328CCMPR02060195	Global skew and band occupancy sometimes broken by late stage CTS
329CCMPR02060125	update_power_vias does not respect via11 blockage over m10 block pins but does over m10 stripes
330CCMPR02060072	Inverting ICG scoring function too restrictive (follow on from CCR 1969990)
331CCMPR02060054	Attribute editor window or any GUI box should be closed with one bind key preferably "esc"
332CCMPR02059995	Wrong design name saved in *.enc.dat/gui_pref.tcl
333CCMPR02059816	set_visible_nets does not work in hierarchy db
334CCMPR02059756	Inconsistent report between budget and justify on port with case
335CCMPR02059644	ecoChangeCell in batch mode SEGV
336CCMPR02059633	addTieHiLo breaks logical equivalency, module based
337CCMPR02059562	Wire gets dropped when writing OA db and reloading
338CCMPR02059548	create_snapshot on restored placeopt DB creates massive timing in GPU block
339CCMPR02059547	checkPlace taking 4-7hrs on a routed design
340CCMPR02059434	Floorplan prediction in Genus calling Innovus 'planDesign' results in SEGV
341CCMPR02059411	sroute SEGV during stripegen target
342CCMPR02059223	congRepair QoR issue when restart new Innovus section
343CCMPR02059140	Innovus fails to optimize critical io group timing with high effort and weight
344CCMPR02059053	addRepeaterByRule SEGV
345CCMPR02058952	sroute moving ports in COVER status to outside the die
346CCMPR02058873	Need to issue a warning message related to tech file error
347CCMPR02058738	Innovus crashing during CTS when using nested fences and the dont_touch_hports attributes after issuing IMPCCOPT-4283
348CCMPR02058346	Need to improve initial timing QoR after NR
349CCMPR02058291	Stack trace during addWellTap in 18.12 and 18.13
350CCMPR02058200	[CPU][NY] Crash after deleting a net
351CCMPR02057772	DIAG [dbWireIO.c:1562:dbiNetNotNeedToSave] during saveDesign
352CCMPR02057589	NR/Swapping vias does not respect hard NDR spacing besides verify_drc cannot detect the errors
353CCMPR02057557	Clock route jogging on preferred routing layers using 18.14
354CCMPR02057549	create_clock_tree_spec output file has typo
355CCMPR02057514	Crash during global routing part of routeDesign
356CCMPR02057474	Manual swapping of ICG improves REG2ICG paths in postcts
357CCMPR02056789	dbget changes deleteFiller behavior
358CCMPR02056738	appending empty lef file list to init_lef_file causes saveDesign link every file in the current run dir
359CCMPR02056633	Innovus crashing on SARC design during QRC extraction
360CCMPR02056023	Does setEcoMode -LEQCheck true affect ecoAddRepeater honoring location parameter
361CCMPR02056011	savePartition with upf should handle inverted control signal
362CCMPR02055978	Crash during save design after refreshing upf, need freeTimingGraph
363CCMPR02055314	Clean up of DIAG messages during preroute extraction due to missing vias in LEF
364CCMPR02055297	Early global route crossing partition boundary at two locations
365CCMPR02055226	PostRoute optDesign crashed during ecoRoute detailRoute
366CCMPR02055209	routeDesign -highFrequency SEGV
367CCMPR02055104	add_gui_shape or addCustomBox no longer allows user to manually resize using GUI due to failed of setObjFPlanBox
368CCMPR02055067	18.13-e070_1 and 18.14 set is_memory to true even for all std cells when voltage scaling lib set is loaded
369CCMPR02054834	Huge amount of Clock ID degradation is observed during egrpc
370CCMPR02054599	SpecifyCellEdgeSpacing -underPG does not work as suggested
371CCMPR02054412	assignTSV takes huge runtime with large number of front bumps
372CCMPR02054352	Order of columns not matching rows
373CCMPR02054161	Innovus shows random behaviour in optDesign -postRoute -setup -hold, in one run crashes during hold optimization
374CCMPR02054105	Crash during placeDesign command
375CCMPR02053999	Fix memory leakage for trimMetalFillNearNet
376CCMPR02053765	OA DB Checker cannot consider standardViaVariant correctly
377CCMPR02053080	CTS crashing at clustering with 17.15 version
378CCMPR02052825	SEGV when do place_opt_design
379CCMPR02052490	HUGE run time is seen while implementing the PG MESH
380CCMPR02051947	SEGV in post-cts opt in ccopt_design after area reclaim
381CCMPR02051261	Back-and-forth buffering observed due to partitioning by UPF logical power domains
382CCMPR02050741	Flip chip router with star algorithm v19.1 results in corrupted routing path data message in a multi pad to bump design
383CCMPR02050703	Flexible htree image colormap change makes the data difficult to use
384CCMPR02050480	Timing miscorrelation moving from tQuantus to iQuantus
385CCMPR02050031	Htree net routed with min cut DRCs
386CCMPR02049947	NR is not updating the default power domain dimension after switching partition
387CCMPR02049946	add_stripe misses via on one of the macro power pins
388CCMPR02049627	fixVia -minstep DIAG issue caused by FGC false report drc
389CCMPR02049322	Mfill cap not being extracted correctly for tQuantus
390CCMPR02049229	Provide an option to allow floating pins to be placed at abutted edge BUT NOT abutting to other floating
391CCMPR02049164	Request to remove escape character in instance name for "create_inst -inst"
392CCMPR02048374	setDesignMode -node S5 causes huge jump in eGR congestion
393CCMPR02048344	Strange routeDesign -wireOpt behavior 
394CCMPR02047828	egr misscorrelation with NanoRoute
395CCMPR02047608	Long clock runtime for the block
396CCMPR02047048	streamOut: wrong min/max voltage text labels for 45-degree shapes
397CCMPR02046629	remove_assigns -net is removing assign statements on all the nets in the design
398CCMPR02046466	NanoRoute: further improvement on fixing trim grid violations is needed for certification
399CCMPR02046325	Tran violations reported with report_constraint and reportTranViolation have mismatch in postRoute
400CCMPR02046088	DIAG during create_timing_budget
401CCMPR02045997	saveNetlist creates wrong assign statement for the input port
402CCMPR02045919	When stretching or changing origin of partition, pins get moved outside of partition and off-track
403CCMPR02045849	Not able to build clock tree with in-bound cells
404CCMPR02045829	add_stripes hung for longtime
405CCMPR02045621	Horizontal max length violations are not being fixed by tool
406CCMPR02045449	editPowerVia - same mask metal aligned cuts
407CCMPR02045272	Floorplan file saved with saveDesign is missing area-IO instances
408CCMPR02044918	Innovus should skip any IO cell when collecting domain tech site
409CCMPR02044551	16nm power via array generated with insufficient space between cuts
410CCMPR02044541	'-optimizeFF true' for Hold is degrading DRV on both data and clock
411CCMPR02043881	Crash and DIAG Assert "peIsDesignExtracted() && peiExtStatus" after tQuantus RC extraction
412CCMPR02043363	Map -noapplycpfrule option in CUI and make it public to add_power_switch both in CUI and Legacy
413CCMPR02043269	ecoAddRepeater missing detail warning message if using -net versus -term
414CCMPR02043233	Why top critical net is not layer assigned at place_opt compared to clock?
415CCMPR02043217	ccopt_design removing pre-routed routing
416CCMPR02042583	ecoRoute crashing after restoreDesign -noTiming
417CCMPR02042544	ecoAddRepeater -hinstGuide executed with setEcoMode -batchMode false
418CCMPR02042506	40nm add/check_metal_fill SEGV
419CCMPR02041798	write_power_intent -1801 is taking longer than expected to dump out upf
420CCMPR02041690	Need a message when tool replaces max input delay by min value
421CCMPR02041649	Placer needs to align placement of insts with M3 via pillars wrt M3 PG
422CCMPR02041585	Timing Debugger generates hold data instead of setup data when timing_analysis_check_type is set to hold
423CCMPR02040999	Module function not preserved after place_opt_design -opt
424CCMPR02040993	**ERROR: (IMPESI-3201): Delay calculation failed for net and causing SEGV
425CCMPR02040333	Power grid insertion to support RIGHTWAYONGRIDONLY EXCEPTWIDTH
426CCMPR02040038	IQRC does not see physical connectivity between terminal wire segment (IMPEXT-1392)
427CCMPR02039519	CCOPT SEGV during refine Place
428CCMPR02039062	NR leaves many open nets when access macro pin in a region
429CCMPR02038277	checkPlace issues pin access warnings and violations while router is able to route
430CCMPR02038152	Router is crashing during hotspot fixing in Pattern matching flow
431CCMPR02038098	Pin legality issue causing PG shorts
432CCMPR02037494	Power hookup not happening for always on buffer while using add_port_driver
433CCMPR02037177	AddTieHiLo adding a cell per pin instead of a cell for multiple pins
434CCMPR02036952	Re-generate .apa file automatically if moved or deleted in the previous DB
435CCMPR02036922	globalDetailRoute -selected SEGV
436CCMPR02036415	MIX_PLACER - the PG modeling for stdcell placement is too pessimistic
437CCMPR02036375	 [invs] write_floorplan_script command dumps out reg's [string] index without curly braces
438CCMPR02036227	Layer preference not honored for special clock routing with the route_ccopt_clock_tree_nets command
439CCMPR02035281	Request to enhance S20 std cell pin access routing
440CCMPR02035102	addFiller creates edge spacing violations
441CCMPR02034883	Stacked vias not added when THICK_CU_D with is between 2.0 and 2.1
442CCMPR02034653	Filler insertion on placed db leaves gaps and checkPlace DRCs after filler cell insertion
443CCMPR02034353	Powerplan via gen needs to support new CUTCLASS orientation syntax
444CCMPR02033663	Vague errors on reading the same CPF after free_power_intent
445CCMPR02033400	verify_drc does not report violations between stripes and 45-degree bump shapes
446CCMPR02033327	place_opt_design hang with Invs 18.12 and 18.13
447CCMPR02033107	Non-determinism in FDS
448CCMPR02032826	Need routing halo to behave as a hard constraint and apply to stdcells as well
449CCMPR02032364	tQuantus vs signoff_Quantus is not good
450CCMPR02031913	postRoute optDesign makes lots of fixable color violations
451CCMPR02031404	Utilization not competitive 
452CCMPR02031150	Partitioning not saving NDR track name to partition's floorplan file
453CCMPR02029175	Improve PRO TAT on large designs (Adaptive EcoRoute Flow)
454CCMPR02028415	Enhance write_lef_abstract to create minimum spacing cut out for non-rectangular pin
455CCMPR02027822	report_path_group_options fails to report -early options
456CCMPR02026581	For Design having ILM create_clock_tree_spec generates 56ns early-tapping on 1 ilm reg clk pin
457CCMPR02026253	Filler cell vertical stack issue
458CCMPR02026031	Observing new zigzag routes with ccoptDesign -cts
459CCMPR02025887	The reportCapViolation -all -min command is not detecting min cap violation on port
460CCMPR02025657	Bug against NR_DRC to not treat trim bridging 2 disjoint wires(pins in this case)
461CCMPR02025200	Automatic via tuning at addStripe could avoid missing vias
462CCMPR02025054	Via blockage and checker function enhancement
463CCMPR02024232	Forbidden spacing issues seen after detail routing
464CCMPR02024132	Clock routing creates stubs on few nets causing EM violations
465CCMPR02023492	NDR violations on M5(6) for via_pillar
466CCMPR02023456	Crash in msvConnectAlwaysOnPowerGround during place_opt_design
467CCMPR02023431	Fill1 gap between MBFF and tap cells
468CCMPR02022973	SAI create_module -gateCount to specify the entire stdcell area not just the flexfiller area
469CCMPR02022953	2x2 TVDD pin via pillar insertion
470CCMPR02022504	Insertion delay due to suboptimal tap assignment
471CCMPR02022480	Shorts during tapering for wide wires
472CCMPR02022275	Lingering 7nm stacked via/MAXCELLEXTENSION issues
473CCMPR02021752	Netlist check failure due to scan chain reorder on chain with macros
474CCMPR02021331	optDesign -postRoute overlooks max_tran violation net
475CCMPR02020831	NRHF routing outside boundary in case no DRC clean path is available
476CCMPR02019093	routeDesign does not honor hard busGuide
477CCMPR02018941	CCopt flexible h-tree drivers placed too close to each other (not honoring cell padding)
478CCMPR02018281	Enhancement to allow addWellTap and other physical placement tools to allow EEQ capability
479CCMPR02017697	CCOpt stuck at the netlist update
480CCMPR02016957	SEGV during clock implementation routing
481CCMPR02016716	ecoRoute fails because of nonexistent segment in PASS layer
482CCMPR02016517	Lack of DRV fixing on N7 top level with INVS 18.11 (unexpected behavior of spGetBoxDemandAndSupply)
483CCMPR02015149	Gigaopt post-eco mode is not running after final area recovery in 18.12-e079_1
484CCMPR02013494	ARR does not add buffers in balanced mode
485CCMPR02012390	Customer wants Innovus to achieve ~179mW of total power Vs current ~200mW for a 1M std-cell only design
486CCMPR02012103	ERROR: (IMPVL-325) in ILM flow when an abstract (LEF) of a submodule is available
487CCMPR02011414	Improve eGR runtime on large designs
488CCMPR02007468	Too many hold fixing buffers getting added
489CCMPR02006782	verify_drc needs to ignore NUT check on M1 layer
490CCMPR02006567	N12, false litho halo violations seen by NanoRoute, 18.11
491CCMPR02005032	Need Innovus to natively fix isolated via violations
492CCMPR02004569	Flightline for rectilinear fences should point to the center of it rather than center of rectangle box
493CCMPR02004466	Command eco_design to support -lef_files option
494CCMPR02003347	route_eco/route_eco -fix_drc leaving 20-30 M1 trim2trim spacing violation in 18.12 builds
495CCMPR01999519	H-tree bottom up pass did not converge
496CCMPR01994813	Inconsistency in postRoute Opt (2nd PRO removal)
497CCMPR01988788	Innovus fixes 300K max_trans in 25 hrs, and it hangs for 18 hours for 1st round fix, without increment info
498CCMPR01982274	New feature to remove tied inputs not working as expected during optimization
499CCMPR01975052	40x improvement in TNS after "place_opt -incr". Improved placement and use of faster buffers
500CCMPR01972186	MAR on fixed VIA when route_eco
501CCMPR01969151	Huge timing difference reported after running extractRc followed with report_timing in innovus
502CCMPR01968874	nrtdGetNetRoutingLayers at huge timing QoR difference between full flow and split flow
503CCMPR01966289	CNOD Optimization in placement
504CCMPR01965080	report_ccopt_cell_halo_violations should output violation report for Violation Browser
505CCMPR01962428	Virtuoso registry file out-of-sync with other Cadence tools
506CCMPR01955769	reportShield changes shield ratio values without actual change to shielding
507CCMPR01948207	Partitioning is wrongly removing rows at the top-level/inside partitions
508CCMPR01943689	Innovus adding shield nets between PG and clock routes
509CCMPR01932175	CCOpt run time degradation due to timing graph updates
510CCMPR01928397	addRoutingHalo fail for PAD
511CCMPR01925270	18.1 place_opt_design resulting in 80% more runtime compared to 17.14
512CCMPR01922769	Current being incorrectly distributed between primary ground pin and bulk ground pin
513CCMPR01889342	verifyPowerVia command is flagging missing vias where cell blockage located
514CCMPR01867794	Placement grid violations are seen in case of nested partitions of mix track libs
515CCMPR01859285	Stacktrace during writing timing model
516CCMPR01835601	verify_drc detects false NSMetal violations on the RDL
517CCMPR01758160	dbiSnapCoordToTrackCmd ptnSnapCoordToTrack API is not snapping to next Mask1 rather than nearest track