· 8 years ago · Jul 31, 2018, 02:58 PM
1#-----------------------------------------------------------
2# Vivado v2018.1 (64-bit)
3# SW Build 2188600 on Wed Apr 4 18:40:38 MDT 2018
4# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
5# Start of session at: Tue Jul 31 10:37:27 2018
6# Process ID: 17156
7# Current directory: C:/Users/roliveira31/Downloads/user/project
8# Command line: vivado.exe -mode batch -source create_project.tcl -tclargs xcku060-ffva1156-2-i
9# Log file: C:/Users/roliveira31/Downloads/user/project/vivado.log
10# Journal file: C:/Users/roliveira31/Downloads/user/project\vivado.jou
11#-----------------------------------------------------------
12source create_project.tcl
13# if { $argc == 1 } {
14# set part [lindex $argv 0]
15# } else {
16# puts "You did not enter the correct number of paramters:"
17# puts "1 - FPGA part (for example : xcku060-ffva1156-1L-i)"
18# exit 1
19# }
20# set suffix ""
21# set tclDir "../scripts/xilinx"
22# source $tclDir/design_utils.tcl
23## set modules [list ]
24## set implementations [list ]
25## set opt_directives [list Explore \
26## ExploreArea \
27## AddRemap \
28## ExploreSequentialArea \
29## RuntimeOptimized \
30## NoBramPowerOpt \
31## Default \
32## ]
33## set place_directives [list Explore \
34## WLDrivenBlockPlacement \
35## AltWLDrivenPlacement \
36## LateBlockPlacement \
37## ExtraNetDelay_high \
38## ExtraNetDelay_medium \
39## ExtraNetDelay_low \
40## SpreadLogic_high \
41## SpreadLogic_medium \
42## SpreadLogic_low \
43## ExtraPostPlacementOpt \
44## SSI_ExtraTimingOpt \
45## SSI_SpreadSLLs \
46## SSI_BalanceSLLs \
47## SSI_BalanceSLRs \
48## SSI_HighUtilSLRs \
49## RuntimeOptimized \
50## Quick \
51## Default \
52## ]
53## set phys_directives [list Explore \
54## ExploreWithHoldFix \
55## AggressiveExplore \
56## AlternateReplication \
57## AggressiveFanoutOpt \
58## AlternateDelayModeling \
59## AddRetime \
60## AlternateFlowWithRetiming \
61## Default \
62## ]
63## set route_directives [list Explore \
64## NoTimingRelaxation \
65## MoreGlobalIterations \
66## HigherDelayCost \
67## AdvancedSkewModeling \
68## RuntimeOptimized \
69## Quick \
70## Default \
71## ]
72## array set module_attributes [list "moduleName" [list string null] \
73## "top_level" [list boolean {0 1}] \
74## "prj" [list string null] \
75## "includes" [list string null] \
76## "generics" [list string null] \
77## "vlog_headers" [list string null] \
78## "vlog_defines" [list string null] \
79## "sysvlog" [list string null] \
80## "vlog" [list string null] \
81## "vhdl" [list string null] \
82## "ip" [list string null] \
83## "ipRepo" [list string null] \
84## "bd" [list string null] \
85## "cores" [list string null] \
86## "xdc" [list string null] \
87## "synthXDC" [list string null] \
88## "implXDC" [list string null] \
89## "synth" [list boolean {0 1}] \
90## "synth_options" [list string null] \
91## "synthCheckpoint" [list string null] \
92## ]
93## array set impl_attributes [list "top" [list string null] \
94## "name" [list string null] \
95## "implXDC" [list string null] \
96## "linkXDC" [list string null] \
97## "cores" [list string null] \
98## "ip" [list string null] \
99## "ipRepo" [list string null] \
100## "impl" [list boolean {0 1}] \
101## "hd.impl" [list boolean {0 1}] \
102## "td.impl" [list boolean {0 1}] \
103## "pr.impl" [list boolean {0 1}] \
104## "ic.impl" [list boolean {0 1}] \
105## "incr.impl" [list boolean {0 1}] \
106## "ooc.impl" [list boolean {0 1}] \
107## "iso.impl" [list boolean {0 1}] \
108## "pr.budget" [list boolean {0 1}] \
109## "pr.budget_exclude" [list string null] \
110## "partitions" [list string null \
111## string null \
112## enum {implement import greybox} \
113## string null \
114## enum {default ooc iso} \
115## enum {logical placement routing} \
116## string null \
117## ] \
118## "link" [list boolean {0 1}] \
119## "opt" [list boolean {0 1}] \
120## "opt.pre" [list string null] \
121## "opt_options" [list string null] \
122## "opt_directive" [list enum $opt_directives] \
123## "place" [list boolean {0 1}] \
124## "place.pre" [list string null] \
125## "place_options" [list string null] \
126## "place_directive" [list enum $place_directives] \
127## "phys" [list boolean {0 1}] \
128## "phys.pre" [list string null] \
129## "phys_options" [list string null] \
130## "phys_directive" [list enum $phys_directives] \
131## "route" [list boolean {0 1}] \
132## "route.pre" [list string null] \
133## "route_options" [list string null] \
134## "route_directive" [list enum $route_directives] \
135## "post_phys" [list boolean {0 1}] \
136## "post_phys.pre" [list string null] \
137## "post_phys_options" [list string null] \
138## "post_phys_directive" [list enum $phys_directives] \
139## "verify" [list boolean {0 1}] \
140## "bitstream" [list boolean {0 1}] \
141## "bitstream.pre" [list string null] \
142## "bitstream_options" [list string null] \
143## "bitstream_settings" [list string null] \
144## "cfgmem.icap" [list boolean {0 1}] \
145## "cfgmem.pcap" [list boolean {0 1}] \
146## "cfgmem.offset" [list string null] \
147## "cfgmem.size" [list enum {1 2 4 8 16 32 64 128 256 512}] \
148## "cfgmem.interface" [list enum {SMAPx8 SMAPx16 SMAPx32}] \
149## "drc.quiet" [list boolean {0 1}] \
150## ]
151## proc add_implementation { name } {
152## global implementations
153## set procname [lindex [info level 0] 0]
154##
155## if {[lsearch -exact $implementations $name] >= 0} {
156## set errMsg "\nERROR: Implementation $name is already defined"
157## error $errMsg
158## }
159##
160## lappend implementations $name
161## set_attribute impl $name "top" ""
162## set_attribute impl $name "name" $name
163## set_attribute impl $name "implXDC" ""
164## set_attribute impl $name "linkXDC" ""
165## set_attribute impl $name "cores" ""
166## set_attribute impl $name "ip" ""
167## set_attribute impl $name "ipRepo" ""
168## set_attribute impl $name "impl" 0
169## set_attribute impl $name "hd.impl" 0
170## set_attribute impl $name "td.impl" 0
171## set_attribute impl $name "pr.impl" 0
172## set_attribute impl $name "ic.impl" 0
173## set_attribute impl $name "incr.impl" 0
174## set_attribute impl $name "ooc.impl" 0
175## set_attribute impl $name "iso.impl" 0
176## set_attribute impl $name "pr.budget" 0
177## set_attribute impl $name "pr.budget_exclude" ""
178## set_attribute impl $name "link" 1
179## set_attribute impl $name "partitions" ""
180## set_attribute impl $name "opt" 1
181## set_attribute impl $name "opt.pre" ""
182## set_attribute impl $name "opt_options" ""
183## set_attribute impl $name "opt_directive" ""
184## set_attribute impl $name "place" 1
185## set_attribute impl $name "place.pre" ""
186## set_attribute impl $name "place_options" ""
187## set_attribute impl $name "place_directive" ""
188## set_attribute impl $name "phys" 1
189## set_attribute impl $name "phys.pre" ""
190## set_attribute impl $name "phys_options" ""
191## set_attribute impl $name "phys_directive" ""
192## set_attribute impl $name "route" 1
193## set_attribute impl $name "route.pre" ""
194## set_attribute impl $name "route_options" ""
195## set_attribute impl $name "route_directive" ""
196## set_attribute impl $name "post_phys" 0
197## set_attribute impl $name "post_phys.pre" ""
198## set_attribute impl $name "post_phys_options" ""
199## set_attribute impl $name "post_phys_directive" ""
200## set_attribute impl $name "verify" 0
201## set_attribute impl $name "bitstream" 0
202## set_attribute impl $name "bitstream.pre" ""
203## set_attribute impl $name "bitstream_options" ""
204## set_attribute impl $name "bitstream_settings" ""
205## set_attribute impl $name "cfgmem.icap" 0
206## set_attribute impl $name "cfgmem.pcap" 0
207## set_attribute impl $name "cfgmem.offset" "up 0x0"
208## set_attribute impl $name "cfgmem.size" "1"
209## set_attribute impl $name "cfgmem.interface" "SMAPx32"
210## set_attribute impl $name "drc.quiet" 0
211## }
212## proc add_module { name } {
213## global modules synthDir
214##
215## if {[lsearch -exact $modules $name] >= 0} {
216## set errMsg "\nERROR: Module $name is already defined"
217## error $errMsg
218## }
219##
220## lappend modules $name
221## set_attribute module $name "moduleName" $name
222## set_attribute module $name "top_level" 0
223## set_attribute module $name "prj" ""
224## set_attribute module $name "includes" ""
225## set_attribute module $name "generics" ""
226## set_attribute module $name "vlog_headers" [list ]
227## set_attribute module $name "vlog_defines" ""
228## set_attribute module $name "sysvlog" [list ]
229## set_attribute module $name "vlog" [list ]
230## set_attribute module $name "vhdl" [list ]
231## set_attribute module $name "ip" [list ]
232## set_attribute module $name "ipRepo" [list ]
233## set_attribute module $name "bd" [list ]
234## set_attribute module $name "cores" [list ]
235## set_attribute module $name "xdc" [list ]
236## set_attribute module $name "synthXDC" [list ]
237## set_attribute module $name "implXDC" [list ]
238## set_attribute module $name "synth" 0
239## set_attribute module $name "synth_options" "-flatten_hierarchy rebuilt"
240## set_attribute module $name "synthCheckpoint" ""
241## }
242## proc set_attribute { type name attribute {values null} } {
243## global ${type}Attribute
244## set procname [lindex [info level 0] 0]
245##
246## switch -exact -- $type {
247## module {set list_type "modules"}
248## impl {set list_type "implementations"}
249## default {error "\nERROR: Invalid type \'$type\' specified"}
250## }
251##
252## check_list $list_type $name $procname
253## check_attribute $type $attribute $procname
254## if {![string match $values "null"]} {
255## foreach value $values {
256## check_attribute_value $type $attribute $value
257## }
258## set ${type}Attribute(${name}.$attribute) $values
259## } else {
260## puts "Critical Warning: Attribute $attribute for $type $name is set to $values. The value will not be modified."
261## }
262## return $values
263## }
264## proc get_attribute { type name attribute } {
265## global ${type}Attribute
266## set procname [lindex [info level 0] 0]
267##
268## switch -exact -- $type {
269## module {set list_type "modules"}
270## impl {set list_type "implementations"}
271## default {error "\nERROR: Invalid type \'$type\' specified"}
272## }
273##
274## check_list $list_type $name $procname
275## check_attribute $type $attribute $procname
276## return [subst -nobackslash \$${type}Attribute(${name}.$attribute)]
277## }
278## proc check_attribute { type attribute procname } {
279## global ${type}_attributes
280## set attributes [array names ${type}_attributes]
281## if {[lsearch -exact $attributes $attribute] < 0} {
282## set errMsg "\nERROR: Invalid $type attribute \'$attribute\' specified in $procname"
283## error $errMsg
284## }
285## }
286## proc check_attribute_value { type attribute values } {
287## global ${type}_attributes
288## if {[info exists ${type}_attributes($attribute)]} {
289## set attribute_checks [subst -nobackslashes \$${type}_attributes($attribute)]
290## set index 0
291## foreach {attr_type attr_values} $attribute_checks {
292## set value [lindex $values $index]
293## if {![string match $attr_values "null"] && [llength $value]} {
294## set pass 0
295## foreach attr_value $attr_values {
296## if {$attr_value==$value} {
297## set pass 1
298## }
299## }
300## if {$pass==0} {
301## set errMsg "\nERROR: Value \'$value\' of $type attribute $attribute of type $attr_type is not valid.\n"
302## append errMsg "Supported values are: $attr_values"
303## error $errMsg
304## }
305## }
306## incr index
307## }
308## } else {
309## set errMsg "\nERROR: Could not find attribute $attribute in array ${type}_attributes."
310## error $errMsg
311## }
312## }
313## proc check_list { list_type name procname } {
314## global [subst $list_type]
315## if {[lsearch -exact [subst -nobackslash \$$list_type] $name] < 0} {
316## set errMsg "\nERROR: Invalid $list_type \'$name\' specified in $procname"
317## error $errMsg
318## }
319## }
320## proc set_directives {$type $name} {
321## global Directives
322##
323## set_attribute $type $name opt_directive $Directives(opt)
324## set_attribute $type $name place_directive $Directives(place)
325## set_attribute $type $name phys_directive $Directives(phys)
326## set_attribute $type $name route_directive $Directives(route)
327## }
328## proc list_runs { } {
329## #### Print list of Modules
330## if {[llength [get_modules synth]]} {
331## set table "-title {#HD: List of modules to be synthesized}"
332## append table " -row {Module \"Module Name\" \"Top Level\" Options}"
333## foreach module [get_modules synth] {
334## set moduleName [get_attribute module $module moduleName]
335## set top [get_attribute module $module top_level]
336## set synth_options [get_attribute module $module synth_options]
337## append table " -row {$module $moduleName $top \"$synth_options\"}"
338## }
339## print_table $table
340## } else {
341## puts "#HD: No modules set to be synthesized"
342## }
343## if {[llength [get_modules !synth]]} {
344## puts "#HD: Defined modules not being synthesized:"
345## set count 1
346## foreach module [get_modules !synth] {
347## puts "\t$count. $module ([get_attribute module $module moduleName])"
348## incr count
349## }
350## }
351##
352## #### Print list of Configurations
353## if {[llength [get_implementations "pr.impl impl" &&]]} {
354## set configs [sort_configurations [get_implementations "pr.impl impl" &&]]
355## set table "-title {#HD: List of Configurations to be implemented}"
356## append table " -row {Configuration \"Reconfig Modules\" \"Static State\" pr_verify write_bistream}"
357## #Sort list of configurations. Insert "initial" config at beginning of list.
358## foreach configuration $configs {
359## set partitions [get_attribute impl $configuration partitions]
360## set top [get_attribute impl $configuration top]
361## set verify [get_attribute impl $configuration verify]
362## set bitstream [get_attribute impl $configuration bitstream]
363## set RMs ""
364## set staticState ""
365## foreach partition $partitions {
366## lassign $partition module cell state name type level dcp
367## if {![string match $cell $top]} {
368## if {[string match $state "greybox"]} {
369## lappend RMs "$state"
370## } else {
371## lappend RMs "$module\($state\)"
372## }
373## } else {
374## set staticState $state
375## }
376## }
377## set rmCount [llength $RMs]
378## for {set i 0} {$i < $rmCount} {incr i} {
379## if {$i==0} {
380## append table " -row {$configuration [lindex $RMs $i] $staticState $verify $bitstream}"
381## } else {
382## append table " -row {\"\" [lindex $RMs $i] \"\" \"\" \"\"}"
383## }
384## }
385## }
386## print_table $table
387## } else {
388## puts "#HD: No Configurations set to be implemented"
389## }
390## if {[llength [get_implementations "pr.impl !impl" &&]]} {
391## puts "#HD: Defined Configurations not being implemented:"
392## set count 1
393## foreach config [get_implementations "pr.impl !impl" &&] {
394## puts "\t$count. $config"
395## incr count
396## }
397## }
398##
399## #### Print list of Implementations
400## if {[llength [get_implementations "!pr.impl impl" &&]]} {
401## set table "-title {#HD: List of Implementations to be implemented}"
402## append table " -row {Implementation Top Partitions \"Flow Type\" write_bistream}"
403## foreach impl [get_implementations "!pr.impl impl" &&] {
404## set partitions [get_attribute impl $impl partitions]
405## set top [get_attribute impl $impl top]
406## set hd [get_attribute impl $impl hd.impl]
407## set td [get_attribute impl $impl td.impl]
408## set ic [get_attribute impl $impl ic.impl]
409## set incr [get_attribute impl $impl incr.impl]
410## set ooc [get_attribute impl $impl ooc.impl]
411## set iso [get_attribute impl $impl iso.impl]
412## set bitstream [get_attribute impl $impl bitstream]
413##
414## if {$hd} {
415## set runType "Assembly"
416## } elseif {$td} {
417## set runType "Top-Down"
418## } elseif {$ic} {
419## set runType "In-Context"
420## } elseif {$incr} {
421## set runType "Incremental"
422## } elseif {$ooc} {
423## set runType "Out-of-Context"
424## } elseif {$iso} {
425## set runType "Isolation"
426## } else {
427## set runType "Flat"
428## }
429##
430## set hdCells ""
431## set state ""
432## set topState "implement"
433## foreach partition $partitions {
434## lassign $partition module cell state name type level dcp
435## if {![string match $cell $top]} {
436## if {![llength $name]} {
437## set name [lindex [split $cell "/"] end]
438## }
439## lappend hdCells "$name\($state\)"
440## } else {
441## set topState $state
442## }
443## }
444##
445## if {[llength $hdCells]} {
446## for {set i 0} {$i < [llength $hdCells]} {incr i} {
447## if {$i==0} {
448## append table " -row {$impl $top\($topState\) [lindex $hdCells $i] $runType $bitstream}"
449## } else {
450## append table " -row {\"\" \"\" [lindex $hdCells $i] \"\" \"\"}"
451## }
452## }
453## } else {
454## append table " -row {$impl $top\($topState\) \"\" $runType $bitstream}"
455## }
456## }
457## print_table $table
458## }
459## if {[llength [get_implementations "!pr.impl !impl" &&]]} {
460## puts "#HD: Defined Implementations not being implemented:"
461## set count 1
462## foreach impl [get_implementations "!pr.impl !impl" &&] {
463## puts "\t$count. $impl"
464## incr count
465## }
466## }
467## puts "\n"
468## }
469## proc sort_configurations { configurations } {
470## set configs ""
471## #Sort list of configurations. Insert "initial" config at beginning of list.
472## foreach configuration $configurations {
473## set partitions [get_attribute impl $configuration partitions]
474## set top [get_attribute impl $configuration top]
475## foreach partition $partitions {
476## lassign $partition module cell state name type level dcp
477## if {[string match $cell $top]} {
478## if {[string match -nocase $state "implement"]} {
479## set configs [linsert $configs 0 $configuration]
480## } else {
481## lappend configs $configuration
482## }
483## }
484## }
485## }
486##
487## #Make sure no configurations get lost in the sort
488## if {[llength $configs] == [llength $configurations]} {
489## return $configs
490## } else {
491## set errMsg "\nERROR: Number of configurations changed during sorting process."
492## error $errMsg
493## }
494## }
495## proc set_parameters {params} {
496## command "puts \"\t#HD: Setting Tcl Params:\""
497## foreach {name value} $params {
498## puts "\t$name == $value"
499## command "set_param $name $value"
500## }
501## puts "\n"
502## }
503## proc report_attributes { type name } {
504## global ${type}Attribute
505## global ${type}_attributes
506## set procname [lindex [info level 0] 0]
507## set widthCol1 18
508## set widthCol2 90
509##
510## switch -exact -- $type {
511## module {set list_type "modules"}
512## impl {set list_type "implementations"}
513## default {error "\nERROR: Invalid type \'$type\' specified"}
514## }
515##
516## check_list $list_type $name $procname
517## puts "Report $type properties for $name:"
518## puts "| [string repeat - $widthCol1] | [string repeat - $widthCol2] |"
519## puts [format "| %-*s | %-*s |" $widthCol1 "Attribute" $widthCol2 "Value"]
520## puts "| [string repeat - $widthCol1] | [string repeat - $widthCol2] |"
521## foreach {attribute } [lsort [array names ${type}_attributes]] {
522## set value [subst -nobackslash \$${type}Attribute(${name}.$attribute)]
523## puts [format "| %-*s | %-*s |" $widthCol1 $attribute $widthCol2 $value]
524## }
525## puts "| [string repeat - $widthCol1] | [string repeat - $widthCol2] |"
526## }
527## proc get_configurations { } {
528## set configurations [get_implementations pr.impl]
529## return $configurations
530## }
531## proc get_ooc_implementations { } {
532## set implementations [get_implementations "ooc.impl iso.impl" ||]
533## return $implementations
534## }
535## proc get_modules { {filters ""} {function &&} } {
536## upvar #0 modules modules
537##
538## if {[llength $filters]} {
539## set filtered_modules ""
540## foreach module $modules {
541## foreach filter $filters {
542## #Check if value is "not", and remove ! from name
543## if {[regexp {!(.*)} $filter old filter]} {
544## set value 0
545## } else {
546## set value 1
547## }
548## if {[get_attribute module $module $filter] == $value} {
549## set match 1
550## if {[string match $function "||"]} {
551## #Add matching filter results if not already added
552## if {[lsearch -exact $filtered_modules $module] < 0} {
553## lappend filtered_modules $module
554## break
555## }
556## }
557## } else {
558## set match 0
559## if {[string match $function "&&"]} {
560## break
561## }
562## }
563## }
564## if {$match && [string match $function "&&"]} {
565## #Add matching filter results if not already added
566## if {[lsearch -exact $filtered_modules $module] < 0} {
567## lappend filtered_modules $module
568## }
569## }
570## }
571## return $filtered_modules
572## } else {
573## return $modules
574## }
575## }
576## proc get_implementations { {filters ""} {function &&} } {
577## upvar #0 implementations implementations
578##
579## if {[llength $filters]} {
580## set filtered_implementations ""
581## foreach implementation $implementations {
582## foreach filter $filters {
583## #Check if value is "not", and remove ! from name
584## if {[regexp {!(.*)} $filter old filter]} {
585## set value 0
586## } else {
587## set value 1
588## }
589## if {[get_attribute impl $implementation $filter] == $value} {
590## set match 1
591## if {[string match $function "||"]} {
592## #Add matching filter results if not already added
593## if {[lsearch -exact $filtered_implementations $implementation] < 0} {
594## lappend filtered_implementations $implementation
595## break
596## }
597## }
598## } else {
599## set match 0
600## if {[string match $function "&&"]} {
601## break
602## }
603## }
604## }
605## if {$match && [string match $function "&&"]} {
606## #Add matching filter results if not already added
607## if {[lsearch -exact $filtered_implementations $implementation] < 0} {
608## lappend filtered_implementations $implementation
609## }
610## }
611## }
612## return $filtered_implementations
613## } else {
614## return $implementations
615## }
616## }
617## proc check_part {part} {
618## set device [lindex [split $part -] 0]
619## if {![llength [get_parts $part]]} {
620## puts "ERROR: No valid part found matching specifiec part:\n\t$part"
621## if {[llength [get_parts ${device}*]]} {
622## puts "Valid part combinations for $device:"
623## puts "\t[join [get_parts ${device}*] \n\t]"
624## }
625## error "ERROR: Check value of specified part."
626## } else {
627## puts "INFO: Found part matching $part"
628## }
629## }
630# source $tclDir/log_utils.tcl
631## if {[info exists tclDir]} {
632## set runLog "run"
633## set commandLog "command"
634## set criticalLog "critical"
635##
636## set logs [list $runLog $commandLog $criticalLog]
637## foreach log $logs {
638## if {[file exists ${log}.log]} {
639## file copy -force $log.log ${log}_prev.log
640## }
641## }
642##
643## set RFH [open "$runLog.log" w]
644## set CFH [open "$commandLog.log" w]
645## set WFH [open "$criticalLog.log" w]
646## }
647## proc log_time {phase start_time end_time {header 0} {notes ""}} {
648## global RFH
649## upvar #1 rfh rfh
650##
651## if {![info exists rfh]} {
652## set rfh "stdout"
653## }
654##
655## #Define widths of each column
656## set widthCol1 19
657## set widthCol2 13
658## set widthCol3 25
659## set widthCol4 65
660##
661## #Calculate times based of passed in times
662## set total_seconds [expr $end_time - $start_time]
663## set total_minutes [expr $total_seconds / 60]
664## set total_hours [expr $total_minutes / 60]
665##
666## if {$header} {
667## puts $rfh "\n| [string repeat - $widthCol1] | [string repeat - $widthCol2] | [string repeat - $widthCol3] | [string repeat - $widthCol4] |"
668## puts $rfh [format "| %-*s | %-*s | %-*s | %-*s |" $widthCol1 "Phase" $widthCol2 "Time in Phase" $widthCol3 "Time\/Date" $widthCol4 "Description"]
669## puts $rfh "| [string repeat - $widthCol1] | [string repeat - $widthCol2] | [string repeat - $widthCol3] | [string repeat - $widthCol4] |"
670## if {[info exists RFH]} {
671## puts $RFH "\n| [string repeat - $widthCol1] | [string repeat - $widthCol2] | [string repeat - $widthCol3] | [string repeat - $widthCol4] |"
672## puts $RFH [format "| %-*s | %-*s | %-*s | %-*s |" $widthCol1 "Phase" $widthCol2 "Time in Phase" $widthCol3 "Time\/Date" $widthCol4 "Description"]
673## puts $RFH "| [string repeat - $widthCol1] | [string repeat - $widthCol2] | [string repeat - $widthCol3] | [string repeat - $widthCol4] |"
674## }
675## }
676##
677## if {[string match $phase final]} {
678## set time "[format %02d [expr $total_hours]]h:[format %02d [expr $total_minutes-($total_hours*60)]]m:[format %02d [expr $total_seconds-($total_minutes*60)]]s"
679## puts $rfh "Total time:\t\t$time\n\n"
680## if {[info exists RFH]} {
681## puts $RFH "Total time:\t\t$time"
682## }
683## } else {
684## set time "[format %02d [expr $total_hours]]h:[format %02d [expr $total_minutes-($total_hours*60)]]m:[format %02d [expr $total_seconds-($total_minutes*60)]]s"
685## set date "[clock format $start_time -format {%H:%M:%S %a %b %d %Y}]"
686## puts $rfh [format "| %-*s | %-*s | %-*s | %-*s |" $widthCol1 "$phase" $widthCol2 "$time" $widthCol3 "$date" $widthCol4 "$notes"]
687## puts $rfh "| [string repeat - $widthCol1] | [string repeat - $widthCol2] | [string repeat - $widthCol3] | [string repeat - $widthCol4] |"
688## if {[info exists RFH]} {
689## puts $RFH [format "| %-*s | %-*s | %-*s | %-*s |" $widthCol1 "$phase" $widthCol2 "$time" $widthCol3 "$date" $widthCol4 "$notes"]
690## puts $RFH "| [string repeat - $widthCol1] | [string repeat - $widthCol2] | [string repeat - $widthCol3] | [string repeat - $widthCol4] |"
691## }
692## }
693## if {[info exists RFH]} {
694## flush $RFH
695## }
696## if {![string match $rfh "stdout"]} {
697## flush $rfh
698## }
699## }
700## proc command { command {log ""} {quiet 0} } {
701## global verbose CFH
702## upvar #1 cfh cfh
703##
704## if {![info exists cfh]} {
705## set cfh "stdout"
706## }
707##
708## if {![info exists CFH]} {
709## set CFH "stdout"
710## }
711##
712## #Write all commands to command.log if file hanlde exists
713## if {![string match $cfh "stdout"]} {
714## if {[llength $log]} {
715## puts $cfh "$command \> $log"
716## } else {
717## puts $cfh $command
718## }
719## flush $cfh
720## }
721## if {![string match $CFH "stdout"]} {
722## if {[llength $log]} {
723## puts $CFH "$command \> $log"
724## } else {
725## puts $CFH $command
726## }
727## flush $CFH
728## }
729##
730## #ignore new-line, comments, or if verbose=0 (to generate scripts only)
731## if {[string match "\n" $command] || [string match "#*" $command] || !$verbose} {
732## return 0
733## }
734##
735## if {$verbose > 1} {
736## puts "\tCOMMAND: $command"
737## }
738##
739## set commandName [lindex [split $command] 0]
740## if {[llength $log] > 0} {
741## if { [catch "$command > $log" errMsg] && !$quiet } {
742## parse_log $log
743## regexp {(\.*.*)(\..*)} $log matched logName logType
744## #If design is open write out a debug DCP
745## if { ![catch {current_instance}] } {
746## puts "#HD: Writing checkpoint ${logName}_error.dcp for debug."
747## command "write_checkpoint -force ${logName}_error.dcp"
748## }
749## #upvar start_time start_time
750## upvar #1 start_time start_time
751## set end_time [clock seconds]
752## log_time $commandName $start_time $end_time 0 $errMsg
753## append errMsg "\nERROR: $commandName command \"$command\" failed.\nSee log file $log for more details."
754## error $errMsg
755## }
756## #Prevent messages from being dumped to terminal if quiet mode
757## if {!$quiet} {
758## parse_log $log
759## }
760## } else {
761## if { [catch $command errMsg] && !$quiet} {
762## append errMsg "\nERROR: $commandName command failed.\n\t$command\n"
763## error $errMsg
764## }
765## }
766## }
767## proc parse_log { log } {
768## global RFH WFH
769## upvar #1 wfh wfh
770## upvar #1 rfh rfh
771##
772## if {![info exists WFH]} {
773## set WFH "stdout"
774## }
775## if {![info exists rfh]} {
776## set rfh "stdout"
777## }
778## if {![info exists wfh]} {
779## set wfh "stdout"
780## }
781## if {[file exists $log]} {
782## set lfh [open $log r]
783## set log_data [read $lfh]
784## close $lfh
785## set log_lines [split $log_data "\n" ]
786## puts $wfh "\t#HD: Parsing log file \"$log\":"
787## puts $WFH "\t#HD: Parsing log file \"$log\":"
788## foreach line $log_lines {
789## if {[string match "CRITICAL WARNING*" $line]} {
790## puts $wfh "\t$line"
791## puts $WFH "\t$line"
792## }
793## if {[string match "ERROR:*" $line]} {
794## puts $rfh $line
795## puts $RFH $line
796## puts $line
797## }
798## }
799## } else {
800## puts $wfh "ERROR: Could not find specified log file \"$log\"."
801## puts $WFH "ERROR: Could not find specified log file \"$log\"."
802## }
803## puts $wfh "\n"
804## puts $WFH "\n"
805## flush $wfh
806## flush $WFH
807## }
808## proc getTimingInfo { {report {}} } {
809## global RFH
810## upvar #1 rfh rfh
811##
812## if {![info exists RFH]} {
813## set RFH "stdout"
814## }
815##
816## if {$report == {}} {
817## set report [split [report_timing_summary -no_detailed_paths -no_check_timing -no_header -return_string] \n]
818## } else {
819## set report [split $report \n]
820## }
821##
822## foreach {wns tns tnsFailingEp tnsTotalEp whs ths thsFailingEp thsTotalEp wpws tpws tpwsFailingEp tpwsTotalEp} [list {N/A} {N/A} {N/A} {N/A} {N/A} {N/A} {N/A} {N/A} {N/A} {N/A} {N/A} {N/A}] {
823## break
824## }
825## if {[set i [lsearch -regexp $report {Design Timing Summary}]] != -1} {
826## foreach {wns tns tnsFailingEp tnsTotalEp whs ths thsFailingEp thsTotalEp wpws tpws tpwsFailingEp tpwsTotalEp} [regexp -inline -all -- {\S+} [lindex $report [expr $i + 6]]] {
827## break
828## }
829## }
830## puts "Setup:\n\t| WNS=$wns | TNS=$tns | Failing Endpoints=$tnsFailingEp | Total Endpoints=$tnsTotalEp |"
831## puts "Hold:\n\t| WHS=$whs | THS=$ths | Failing Endpoints=$thsFailingEp | Total Endpoints=$thsTotalEp |"
832## puts "Pulse Width:\n\t | WPWS=$wpws | TPWS=$tpws | Failing Endpoints=$tpwsFailingEp | Total Endpoints=$tpwsTotalEp |\n\n"
833## puts $RFH "Setup:\n\t| WNS=$wns | TNS=$tns | Failing Endpoints=$tnsFailingEp | Total Endpoints=$tnsTotalEp |"
834## puts $RFH "Hold:\n\t| WHS=$whs | THS=$ths | Failing Endpoints=$thsFailingEp | Total Endpoints=$thsTotalEp |"
835## puts $RFH "Pulse Width:\n\t | WPWS=$wpws | TPWS=$tpws | Failing Endpoints=$tpwsFailingEp | Total Endpoints=$tpwsTotalEp |\n\n"
836## puts $rfh "Setup:\n\t| WNS=$wns | TNS=$tns | Failing Endpoints=$tnsFailingEp | Total Endpoints=$tnsTotalEp |"
837## puts $rfh "Hold:\n\t| WHS=$whs | THS=$ths | Failing Endpoints=$thsFailingEp | Total Endpoints=$thsTotalEp |"
838## puts $rfh "Pulse Width:\n\t | WPWS=$wpws | TPWS=$tpws | Failing Endpoints=$tpwsFailingEp | Total Endpoints=$tpwsTotalEp |\n\n"
839## }
840## proc read_file_lines {file} {
841## if {![file exists $file]} {
842## puts "Error: Specified file $file does not exist. Please check path."
843## return
844## }
845## set fh [open $file r]
846## set fileData [read $fh]
847## close $fh
848## set fileLines [split $fileData "\n" ]
849## return $fileLines
850## }
851## proc print_table { args } {
852## set args [join $args]
853## set title "Table"
854## set FH "stdout"
855##
856## #Override defaults with command options
857## set argLength [llength $args]
858## set index 0
859## set rowCount 0
860## while {$index < $argLength} {
861## set arg [lindex $args $index]
862## set value [lindex $args [expr $index+1]]
863## switch -exact -- $arg {
864## {-title} {set title $value}
865## {-row} {dict set rows row${rowCount} $value
866## incr rowCount
867## }
868## {-file} {set FH [open $value w]}
869## {-handle} {upvar $value FH}
870## {-help} {set helpMsg "Description:"
871## lappend helpMsg "Prints out a table in order the Rows are specified.\n"
872## lappend helpMsg "Syntax:"
873## lappend helpMsg "print_table\t\[-row <row1>] ... \[-row <rowN] \[-file <arg>]\n"
874## lappend helpMsg "Usage:"
875## lappend helpMsg " Name Description"
876## lappend helpMsg " -------------------------------------------------------------------------------"
877## lappend helpMsg " \[-title] Optional. Defines the title of the table."
878## lappend helpMsg " A default table name is used if no title is defined"
879## lappend helpMsg " \[-row] Required. Defines a Row of the table to be printed."
880## lappend helpMsg " The order the rows are defined is the print order."
881## lappend helpMsg " \[-file] Optional. Specifies the output file name."
882## lappend helpMsg " If not specified the output will be written to STDOUT"
883## lappend helpMsg " \[-help] Displays this message\n\n"
884## foreach line $helpMsg {
885## puts $FH $line
886## }
887## return
888## }
889## default {set errMsg "ERROR: Specified argument $arg is not supported.\n"
890## append errMsg "Supported arguments are -help, -title, -row, and -file.\n"
891## append errMsg "Use the -help option for more details"
892## error $errMsg
893## }
894## }
895## set index [expr $index + 2]
896## }
897##
898##
899## #Create an array for column widths for each header entry
900## set headers [dict get $rows row0]
901## set colCount 0
902## set colTotal [llength $headers]
903## foreach header $headers {
904## set colWidth($colCount) [expr [string length $header] + 1]
905## incr colCount
906## }
907##
908##
909## #Get max length of entry, and update colWidth if necessary
910## dict for {row entries} $rows {
911## set colCount 0
912## set rowTotal [llength $entries]
913## if {$rowTotal != $colTotal} {
914## set errMsg "Error: The number of entries for $row does match the number of entries for row0.\n"
915## append errMsg "row0: [dict get $rows row0]\n"
916## append errMsg "$row: [dict get $rows $row]\n"
917## error $errMsg
918## }
919## foreach cell $entries {
920## set length [expr [string length $cell] + 1]
921## #puts "$colCount: $cell: $length"
922## if {$length > $colWidth($colCount) } {
923## set colWidth($colCount) $length
924## }
925## incr colCount
926## }
927## }
928##
929## #Create a string to seperate each row/column of data
930## set separator "|"
931## set colCount 0
932## foreach {key value} [array get colWidth] {
933## set width $colWidth($colCount)
934## append separator " [string repeat - $width] |"
935## incr colCount
936## }
937##
938## #Create the necessary string for each row to be used with "format" command
939## #[format "| %-*s | %-*s | %-*s | %-*s | %-*s | %-*s |" $width1 $value1 $width2 $value2 ... $widthN $valueN]
940## set rowCount 0
941## dict for {row entries} $rows {
942## dict set table row${rowCount} "\"|"
943## foreach cell $entries {
944## dict append table row${rowCount} " %-*s |"
945## }
946## dict append table row${rowCount} "\""
947## #puts "[dict get $table row${rowCount}]"
948## incr rowCount
949## }
950##
951## #Add additional information to each row to complete information needed for "format" command
952## #[format "| %-*s | %-*s | %-*s | %-*s | %-*s | %-*s |" $width1 $value1 $width2 $value2 ... $widthN $valueN]
953## set rowCount 0
954## dict for {row entries} $rows {
955## set col 0
956## foreach cell $entries {
957## dict append table row${rowCount} " $colWidth($col) \"$cell\""
958## incr col
959## }
960## #puts "[dict get $table row${rowCount}]"
961## incr rowCount
962## }
963##
964## #Print the Table
965## puts $FH "\n$title:"
966## dict for {row value} $table {
967## puts $FH $separator
968## puts $FH [eval format $value]
969## }
970## puts $FH "$separator\n"
971##
972## #Close the file handle if -file was specified
973## if {![string match $FH "stdout"]} {
974## close $FH
975## }
976## }
977# source $tclDir/synth_utils.tcl
978## source $tclDir/synthesize.tcl
979### proc synthesize { module } {
980### global tclParams
981### global part
982### global board
983### global synthDir
984### global srcDir
985### global verbose
986###
987### set moduleName [get_attribute module $module moduleName]
988### set topLevel [get_attribute module $module top_level]
989### set prj [get_attribute module $module prj]
990### set includes [get_attribute module $module includes]
991### set generics [get_attribute module $module generics]
992### set vlogHeaders [get_attribute module $module vlog_headers]
993### set vlogDefines [get_attribute module $module vlog_defines]
994### set sysvlog [get_attribute module $module sysvlog]
995### set vlog [get_attribute module $module vlog]
996### set vhdl [get_attribute module $module vhdl]
997### set ip [get_attribute module $module ip]
998### set ipRepo [get_attribute module $module ipRepo]
999### set bd [get_attribute module $module bd]
1000### set cores [get_attribute module $module cores]
1001### set xdc [get_attribute module $module xdc]
1002### set synthXDC [get_attribute module $module synthXDC]
1003### set options [get_attribute module $module synth_options]
1004###
1005### set resultDir "$synthDir/$module"
1006###
1007### # Make the synthesis directory if needed
1008### if {![file exists $synthDir]} {
1009### file mkdir $synthDir
1010### }
1011### # Clean-out and re-make the synthesis directory for this module
1012### file delete -force $resultDir
1013### file mkdir $resultDir
1014###
1015### #Open local log files
1016### set rfh [open "$resultDir/run.log" w]
1017### set cfh [open "$resultDir/command.log" w]
1018### set wfh [open "$resultDir/critical.log" w]
1019###
1020### command "puts \"#HD: Running synthesis for block $module\""
1021### puts "\tWriting results to: $resultDir"
1022### set synth_start [clock seconds]
1023###
1024### #### Set Tcl Params
1025### if {[info exists tclParams] && [llength $tclParams] > 0} {
1026### set_parameters $tclParams
1027### }
1028###
1029### #Create in-memory project
1030### command "create_project -in_memory -part $part" "$resultDir/create_project.log"
1031###
1032### if {[info exists board] && [llength $board]} {
1033### command "set_property board_part $board \[current_project\]"
1034### }
1035###
1036### #### Setup any IP Repositories
1037### if {$ipRepo != ""} {
1038### puts "\tLoading IP Repositories:\n\t+ [join $ipRepo "\n\t+ "]"
1039### command "set_property IP_REPO_PATHS \{$ipRepo\} \[current_fileset\]" "$resultDir/temp.log"
1040### command "update_ip_catalog" "$resultDir/temp.log"
1041### }
1042###
1043### set start_time [clock seconds]
1044### if {[llength $prj] > 0} {
1045### add_prj $prj
1046### set end_time [clock seconds]
1047### log_time add_prj $start_time $end_time 1 "Process PRJ file"
1048### } else {
1049### #### Read in System Verilog
1050### if {[llength $sysvlog] > 0} {
1051### add_sysvlog $sysvlog
1052### }
1053###
1054### #### Read in Verilog
1055### if {[llength $vlog] > 0} {
1056### add_vlog $vlog
1057### }
1058###
1059### #### Read in VHDL
1060### if {[llength $vhdl] > 0} {
1061### add_vhdl $vhdl
1062### }
1063### set end_time [clock seconds]
1064### log_time add_files $start_time $end_time 1 "Add source files"
1065### }
1066###
1067### #### Read IP from Catalog
1068### if {[llength $ip] > 0} {
1069### set start_time [clock seconds]
1070### add_ip $ip
1071### set end_time [clock seconds]
1072### log_time add_ip $start_time $end_time 0 "Add XCI files and generate/synthesize IP"
1073### }
1074###
1075### #### Read IPI systems
1076### if {[llength $bd] > 0} {
1077### set start_time [clock seconds]
1078### add_bd $bd
1079### set end_time [clock seconds]
1080### log_time add_bd $start_time $end_time 0 "Add/generate IPI block design"
1081### }
1082###
1083### #### Read in IP Netlists
1084### if {[llength $cores] > 0} {
1085### set start_time [clock seconds]
1086### add_cores $cores
1087### set end_time [clock seconds]
1088### log_time add_cores $start_time $end_time 0 "Add synthesized IP (DCP, NGC, EDIF)"
1089### }
1090###
1091### #### Read in synthXDC files
1092### if {[llength $synthXDC] > 0} {
1093### set start_time [clock seconds]
1094### add_xdc $synthXDC 2
1095### set end_time [clock seconds]
1096### log_time add_xdc $start_time $end_time 0 "Add synthesis only XDC files"
1097### }
1098###
1099### #### Read in XDC file
1100### if {[llength $xdc] > 0} {
1101### set start_time [clock seconds]
1102### add_xdc $xdc 1
1103### set end_time [clock seconds]
1104### log_time add_xdc $start_time $end_time 0 "Add XDC files"
1105### }
1106###
1107### if {[llength $xdc] == 0 && [llength $synthXDC] == 0} {
1108### puts "\tInfo: No XDC file specified for $module"
1109### }
1110###
1111### #### Set Verilog Headers
1112### if {[llength $vlogHeaders] > 0} {
1113### foreach file $vlogHeaders {
1114### command "set_property file_type {Verilog Header} \[get_files $file\]"
1115### }
1116### }
1117###
1118### #### Set Verilog Defines
1119### if {$vlogDefines != ""} {
1120### command "set_property verilog_define \{$vlogDefines\} \[current_fileset\]"
1121### }
1122###
1123### #### Set Include Directories
1124### if {$includes != ""} {
1125### command "set_property include_dirs \{$includes\} \[current_fileset\]"
1126### }
1127###
1128### #### Set Generics
1129### if {$generics != ""} {
1130### command "set_property generic $generics \[current_fileset\]"
1131### }
1132###
1133### #### synthesis
1134### puts "\tRunning synth_design"
1135### set start_time [clock seconds]
1136### if {$topLevel} {
1137### command "synth_design -mode default $options -top $moduleName -part $part" "$resultDir/${moduleName}_synth_design.rds"
1138### } else {
1139### command "synth_design -mode out_of_context $options -top $moduleName -part $part" "$resultDir/${moduleName}_synth_design.rds"
1140### }
1141### set end_time [clock seconds]
1142### log_time synth_design $start_time $end_time 0 "$moduleName $options"
1143###
1144### set start_time [clock seconds]
1145### command "write_checkpoint -force $resultDir/${moduleName}_synth.dcp" "$resultDir/write_checkpoint.log"
1146### set end_time [clock seconds]
1147### log_time write_checkpiont $start_time $end_time 0 "Write out synthesis DCP"
1148###
1149### if {$verbose >= 1} {
1150### set start_time [clock seconds]
1151### command "report_utilization -file $resultDir/${moduleName}_utilization_synth.rpt" "$resultDir/temp.log"
1152### set end_time [clock seconds]
1153### log_time report_utilization $start_time $end_time 0 "Report Synthesis Utilization of $module"
1154### }
1155### set synth_end [clock seconds]
1156### log_time final $synth_start $synth_end
1157### command "close_project"
1158### command "puts \"#HD: Synthesis of module $module complete\\n\""
1159### close $rfh
1160### close $cfh
1161### close $wfh
1162### }
1163## proc add_prj { prj } {
1164## global srcDir
1165##
1166## if {[file exists $prj]} {
1167## puts "\tParsing PRJ file: $prj"
1168## set source [open $prj r]
1169## set source_data [read $source]
1170## close $source
1171## #Remove quotes from PRJ file
1172## regsub -all {\"} $source_data {} source_data
1173## set prj_lines [split $source_data "\n" ]
1174## set line_count 0
1175## foreach line $prj_lines {
1176## incr line_count
1177## #Ignore empty and commented lines
1178## if {[llength $line] > 0 && ![string match -nocase "#*" $line]} {
1179## if {[llength $line]!=3} {
1180## set errMsg "\nERROR: Line $line_count is invalid format. Should be:\n\t<file_type> <library> <file>"
1181## error $errMsg
1182## }
1183## lassign $line type lib file
1184## if {![string match -nocase $type "dcp"] && \
1185## ![string match -nocase $type "xci"] && \
1186## ![string match -nocase $type "header"] && \
1187## ![string match -nocase $type "system"] && \
1188## ![string match -nocase $type "verilog"] && \
1189## ![string match -nocase $type "vhdl"]} {
1190## set errMsg "\nERROR: File type $type is not a supported value.\n"
1191## append errMsg "Supported types are:\n\tdcp\n\txci\n\theader\n\tsystem\n\tverilog\n\tvhdl\n\t"
1192## error $errMsg
1193## }
1194## if {[file exists ${srcDir}/$file]} {
1195## set file ${srcDir}/$file
1196## command "add_files $file" "add_files.log"
1197## if {[string match -nocase $type "vhdl"]} {
1198## command "set_property LIBRARY $lib \[get_files $file\]"
1199## }
1200## if {[string match -nocase $type "system"]} {
1201## command "set_property FILE_TYPE SystemVerilog \[get_files $file\]"
1202## }
1203## if {[string match -nocase $type "header"]} {
1204## command "set_property FILE_TYPE {Verilog Header} \[get_files $file\]"
1205## }
1206## } elseif {[file exists $file]} {
1207## command "add_files $file"
1208## if {[string match -nocase $type "vhdl"]} {
1209## command "set_property LIBRARY $lib \[get_files $file\]"
1210## }
1211## if {[string match -nocase $type "system"]} {
1212## command "set_property FILE_TYPE SystemVerilog \[get_files $file\]"
1213## }
1214## if {[string match -nocase $type "header"]} {
1215## command "set_property FILE_TYPE {Verilog Header} \[get_files $file\]"
1216## }
1217## } else {
1218## puts "ERROR: Could not find file \"$file\" on line $line_count."
1219## set error 1
1220## }
1221## }
1222## }
1223## if {[info exists error]} {
1224## set errMsg "\nERROR: Files not found. Check messages for more details.\n"
1225## error $errMsg
1226## }
1227## } else {
1228## set errMsg "\nERROR: Could not find PRJ file $prj"
1229## error $errMsg
1230## }
1231## }
1232## proc add_bd { files } {
1233## upvar resultDir resultDir
1234##
1235## foreach file $files {
1236## if {[string length file] > 0} {
1237## if {[file exists $file]} {
1238## set bd_split [split $file "/"]
1239## set bd [lindex $bd_split end]
1240## set bdName [lindex [split $bd "."] 0]
1241## if {[regexp {.*\.tcl} $file]} {
1242## command "source $file"
1243## command "generate_target all \[get_files .srcs/sources_1/bd/${bdName}/${bdName}.bd\]"
1244## } else {
1245## command "add_files $file" "$resultDir/add_bd.log"
1246## command "generate_target all \[get_files $file]" "$resultDir/${bdName}_generate.log"
1247## }
1248## } else {
1249## set errMsg "\nERROR: Could not find specified BD file: $file"
1250## error $errMsg
1251## }
1252## }
1253## }
1254## }
1255## proc add_sysvlog { sysvlog } {
1256## set files [join $sysvlog]
1257## foreach file $files {
1258## if {[file exists $file]} {
1259## command "add_files $file"
1260## command "set_property FILE_TYPE SystemVerilog \[get_files $file\]"
1261## } else {
1262## puts "ERROR: Could not find file \"$file\"."
1263## set error 1;
1264## }
1265## }
1266## if {[info exists error]} {
1267## set errMsg "\nERROR: Files not found. Check messages for more details.\n"
1268## error $errMsg
1269## }
1270## }
1271## proc add_vlog { vlog } {
1272## set files [join $vlog]
1273## foreach file $files {
1274## if {[file exists $file]} {
1275## command "add_files $file"
1276## } else {
1277## puts "ERROR: Could not find file \"$file\"."
1278## set error 1;
1279## }
1280## }
1281## if {[info exists error]} {
1282## set errMsg "\nERROR: Files not found. Check messages for more details.\n"
1283## error $errMsg
1284## }
1285## }
1286## proc add_vhdl { vhdl } {
1287## set index 0
1288## while {$index < [llength $vhdl]} {
1289## set lib [lindex $vhdl [expr $index+1]]
1290## foreach file [lindex $vhdl $index] {
1291## if {[file exists $file]} {
1292## command "add_files $file"
1293## command "set_property LIBRARY $lib \[get_files $file\]"
1294## } else {
1295## puts "ERROR: Could not find file \"$file\"."
1296## set error 1;
1297## }
1298## }
1299## set index [expr $index+2]
1300## }
1301## if {[info exists error]} {
1302## set errMsg "\nERROR: Files not found. Check messages for more details.\n"
1303## error $errMsg
1304## }
1305## }
1306# source $tclDir/impl_utils.tcl
1307## if {[info exists tclDir]} {
1308## source $tclDir/implement.tcl
1309## source $tclDir/step.tcl
1310## }
1311### proc implement {impl} {
1312### global tclParams
1313### global part
1314### global dcpLevel
1315### global verbose
1316### global implDir
1317### global xdcDir
1318### global dcpDir
1319### global RFH
1320###
1321### set top [get_attribute impl $impl top]
1322### set name [get_attribute impl $impl name]
1323### set implXDC [get_attribute impl $impl implXDC]
1324### set linkXDC [get_attribute impl $impl linkXDC]
1325### set cores [get_attribute impl $impl cores]
1326### set ip [get_attribute impl $impl ip]
1327### set ipRepo [get_attribute impl $impl ipRepo]
1328### set hd [get_attribute impl $impl hd.impl]
1329### set td [get_attribute impl $impl td.impl]
1330### set pr [get_attribute impl $impl pr.impl]
1331### set ic [get_attribute impl $impl ic.impl]
1332### set incr [get_attribute impl $impl incr.impl]
1333### set iso [get_attribute impl $impl iso.impl]
1334### set ooc [get_attribute impl $impl ooc.impl]
1335### set pr.budget [get_attribute impl $impl pr.budget]
1336### set budgetExclude [get_attribute impl $impl pr.budget_exclude]
1337### set partitions [get_attribute impl $impl partitions]
1338### set link [get_attribute impl $impl link]
1339### set opt [get_attribute impl $impl opt]
1340### set opt.pre [get_attribute impl $impl opt.pre]
1341### set opt_options [get_attribute impl $impl opt_options]
1342### set opt_directive [get_attribute impl $impl opt_directive]
1343### set place [get_attribute impl $impl place]
1344### set place.pre [get_attribute impl $impl place.pre]
1345### set place_options [get_attribute impl $impl place_options]
1346### set place_directive [get_attribute impl $impl place_directive]
1347### set phys [get_attribute impl $impl phys]
1348### set phys.pre [get_attribute impl $impl phys.pre]
1349### set phys_options [get_attribute impl $impl phys_options]
1350### set phys_directive [get_attribute impl $impl phys_directive]
1351### set route [get_attribute impl $impl route]
1352### set route.pre [get_attribute impl $impl route.pre]
1353### set route_options [get_attribute impl $impl route_options]
1354### set route_directive [get_attribute impl $impl route_directive]
1355### set post_phys [get_attribute impl $impl post_phys]
1356### set post_phys.pre [get_attribute impl $impl post_phys.pre]
1357### set post_phys_options [get_attribute impl $impl post_phys_options]
1358### set post_phys_directive [get_attribute impl $impl post_phys_directive]
1359### set bitstream [get_attribute impl $impl bitstream]
1360### set bitstream.pre [get_attribute impl $impl bitstream.pre]
1361### set bitstream_options [get_attribute impl $impl bitstream_options]
1362### set bitstream_settings [get_attribute impl $impl bitstream_settings]
1363### set drc.quiet [get_attribute impl $impl drc.quiet]
1364###
1365### if {($hd && ($td || $ic || $pr || $ooc)) || \
1366### ($td && ($hd || $ic || $pr || $ooc)) || \
1367### ($ic && ($td || $hd || $pr || $ooc)) || \
1368### ($pr && ($td || $hd || $ic || $ooc)) || \
1369### ($ooc && ($td || $hd || $ic || $pr)) } {
1370### set errMsg "\nERROR: Implementation $impl has more than one of the following flow variables set to 1"
1371### append errMsg "\n\thd.impl($hd)\n\ttd.impl($td)\n\tic.impl($ic)\n\tpr.impl($pr)\n\t$ooc.impl($ooc)\n"
1372### append errMsg "Only one of these variables can be set true at one time. To run multiple flows, create separate implementation runs."
1373### #Temporary - comment out until PR is no longer needed for HD Platform flow (ie. PR + IC)
1374### # error $errMsg
1375### }
1376###
1377### set resultDir "$implDir/$impl"
1378### set reportDir "$resultDir/reports"
1379###
1380### #### Make the implementation directory, Clean-out and re-make the results directory
1381### command "file mkdir $implDir"
1382### command "file delete -force $resultDir"
1383### command "file mkdir $resultDir"
1384### command "file mkdir $reportDir"
1385###
1386### #### Open local log files
1387### set rfh [open "$resultDir/run.log" w]
1388### set cfh [open "$resultDir/command.log" w]
1389### set wfh [open "$resultDir/critical.log" w]
1390###
1391### set vivadoVer [version]
1392### puts $rfh "Info: Running Vivado version $vivadoVer"
1393### puts $RFH "Info: Running Vivado version $vivadoVer"
1394###
1395### command "puts \"#HD: Running implementation $impl\""
1396### puts "\tWriting results to: $resultDir"
1397### puts "\tWriting reports to: $reportDir"
1398### puts $rfh "#HD: Running implementation $impl"
1399### puts $rfh "Writing results to: $resultDir"
1400### puts $rfh "Writing reports to: $reportDir"
1401### puts $RFH "#HD: Running implementation $impl"
1402### puts $RFH "Writing results to: $resultDir"
1403### puts $RFH "Writing reports to: $reportDir"
1404### set impl_start [clock seconds]
1405###
1406### #### Set Tcl Params
1407### if {[info exists tclParams] && [llength $tclParams] > 0} {
1408### set_parameters $tclParams
1409### }
1410###
1411### #### Create in-memory project
1412### command "create_project -in_memory -part $part" "$resultDir/create_project.log"
1413###
1414### #### Setup any IP Repositories
1415### if {$ipRepo != ""} {
1416### puts "\tLoading IP Repositories:\n\t+ [join $ipRepo "\n\t+ "]"
1417### command "set_property IP_REPO_PATHS \{$ipRepo\} \[current_fileset\]" "$resultDir/temp.log"
1418### command "update_ip_catalog" "$resultDir/temp.log"
1419### }
1420###
1421### ###########################################
1422### # Linking
1423### ###########################################
1424### if {$link} {
1425### #Determine state of Top (import or implement).
1426### set topState "implement"
1427### foreach partition $partitions {
1428### lassign $partition module cell state name type level dcp
1429### if {[string match $cell $top]} {
1430### set topState $state
1431### if {[llength $dcp]} {
1432### set topFile $dcp
1433### }
1434### }
1435### }
1436###
1437### #If DCP for top is not defined in Partition settings, try and find it.
1438### if {![info exist topFile] || ![llength $topFile]} {
1439### foreach module [get_modules] {
1440### set moduleName [get_attribute module $module moduleName]
1441### if {[string match $top $moduleName]} {
1442### break
1443### }
1444### }
1445### if {[string match $topState "implement"]} {
1446### set topFile [get_module_file $module]
1447### } elseif {[string match $topState "import"]} {
1448### if {$pr} {
1449### set topFile "$dcpDir/${top}_static.dcp"
1450### } else {
1451### set topFile "$dcpDir/${top}_routed.dcp"
1452### }
1453### } else {
1454### set errMsg "\nERROR: State of Top module $top is set to illegal state $topState."
1455### error $errMsg
1456### }
1457### }
1458###
1459### if {[file exists $topFile]} {
1460### puts "\t#HD: Adding file $topFile for $top"
1461### command "add_files $topFile"
1462### } else {
1463### set errMsg "\nERROR: Specified file $topFile cannot be found on disk. Verify path is correct, and that all dependices have been run."
1464### error $errMsg
1465### }
1466###
1467### ####Read in top-level cores, ip, and XDC on if Top is being implemented
1468### if {[string match $topState "implement"]} {
1469### # Read in IP Netlists
1470### if {[llength $cores] > 0} {
1471### add_cores $cores
1472### }
1473### # Read IP XCI files
1474### if {[llength $ip] > 0} {
1475### set start_time [clock seconds]
1476### add_ip $ip
1477### set end_time [clock seconds]
1478### log_time add_ip $start_time $end_time 0 "Add XCI files and generate/synthesize IP"
1479### }
1480### # Read in XDC files
1481### if {[llength $implXDC] > 0 && [string match $topState "implement"]} {
1482### add_xdc $implXDC
1483### } else {
1484### if {[string match $topState "import"]} {
1485### puts "\tInfo: Skipping top-level XDC files because $top is set to $topState"
1486### } else {
1487### puts "\tInfo: No pre-link_design XDC file specified for $impl"
1488### }
1489### }
1490### }
1491###
1492### ###########################################################
1493### # Link the top-level design with black boxes for Partitions
1494### ###########################################################
1495### set start_time [clock seconds]
1496### if {!$ooc} {
1497### puts "\t#HD: Running link_design for $top \[[clock format $start_time -format {%a %b %d %H:%M:%S %Y}]\]"
1498### command "link_design -mode default -part $part -top $top" "$resultDir/${top}_link_design.log"
1499### } else {
1500### puts "\t#HD: Running link_design for $top \[[clock format $start_time -format {%a %b %d %H:%M:%S %Y}]\]"
1501### command "link_design -mode out_of_context -part $part -top $top" "$resultDir/${top}_link_design.log"
1502### #Set appropriate attribute on "current_design" for ISO and OOC flows.
1503### if {$iso} {
1504### command "set_property HD.ISOLATED 1 \[current_design]"
1505### } else {
1506### command "set_property HD.PARTITION 1 \[current_design]"
1507### }
1508### }
1509### set end_time [clock seconds]
1510### log_time link_design $start_time $end_time 1 "link_design -part $part -top $top"
1511###
1512### ##############################################
1513### # Resolve Partitions
1514### ##############################################
1515### #Special processing for TopDown implementation
1516### if {$td && $verbose > 0} {
1517### #Turn off phys_opt_design and route_design for TD run
1518### set phys [set_attribute impl $impl phys 0]
1519### set route [set_attribute impl $impl route 0]
1520### #Turn on param to generate PP_RANGE. UPDATE: Default is now 1, so no need.
1521### #set_parameters {hd.partPinRangesForPblock 1}
1522### }
1523### if {$incr} {
1524### #Turn off Partpin generation for in-conext flows with HD.PARTITION
1525### set_parameters {hd.partPinRangesForPblock 0}
1526### }
1527###
1528### foreach partition $partitions {
1529### lassign $partition module cell state name type level dcp
1530### if {![llength $name]} {
1531### set name [lindex [split $cell "/"] end]
1532### }
1533###
1534### #Process each partition that is not Top
1535### #Don't try to get moduleName for greybox Partitions as the name can be random
1536### if {![string match "greybox" $state]} {
1537### set moduleName [get_attribute module $module moduleName]
1538### } else {
1539### set moduleName $module
1540### }
1541### if {![string match $moduleName $top]} {
1542### #Set appropriate HD.* property if Top/Static is being implemented
1543### if {[string match $topState "implement"]} {
1544### #Mark all partitions as HD.RECONFIG in a PR run unless partition 'type' is set to OOC
1545### if {$pr && ![string match $type "ooc"] && ![string match $type "iso"]} {
1546### command "set_property HD.RECONFIGURABLE 1 \[get_cells $cell]"
1547### } elseif [string match $type "iso"] {
1548### command "set_property HD.ISOLATED 1 \[get_cells $cell]"
1549### } else {
1550### command "set_property HD.PARTITION 1 \[get_cells $cell]"
1551### }
1552### }
1553###
1554### #Find correct file to be used for Partition
1555### if {[llength $dcp] && ![string match $state "greybox"]} {
1556### set partitionFile $dcp
1557### } else {
1558### #Greybox overrides any other settings regardless of flow
1559### if {[string match $state "greybox"]} {
1560### puts "\tInfo: Cell $cell will be implemented as a grey box."
1561### set partitionFile "NA"
1562### #if flow is incremental, load synth netlist regardless of $state equal to import Vs implement
1563### } elseif {[string match $state "implement"] || $incr} {
1564### set partitionFile [get_module_file $module]
1565### } elseif {[string match $state "import"]} {
1566### if {$iso || $ooc} {
1567### set partitionFile "$dcpDir/${pblock}_${module}_route_design.dcp"
1568### } else {
1569### set pblock [get_pblocks -of [get_cell $cell]]
1570### #Since names rely on Pblock to uniquify, error if no Pblock exists.
1571### if {![llength $pblock]} {
1572### set errMsg "Error: No pblock found on partition cell $cell."
1573### error $errMsg
1574### }
1575### set partitionFile "$dcpDir/${pblock}_${module}_route_design.dcp"
1576### }
1577### } else {
1578### set errMsg "\nERROR: Invalid state \"$state\" in settings for $name\($impl)."
1579### append errMsg"Valid states are \"implement\", \"import\", or \"greybox\".\n"
1580### error $errMsg
1581### }
1582### }
1583### if {![file exists $partitionFile] && ![string match $state "greybox"]} {
1584### set errMsg "ERROR: Partition \'$cell\' with state \'$state\' is set to use the file:\n$partitionFile\n\nThis file does not exist."
1585### if {$ooc} {
1586### append errMsg "Check that the Name of the parition matches the Name field of the corresponding OOC run."
1587### }
1588### error $errMsg
1589### }
1590###
1591### #Resolve blackbox for partition
1592### if {![get_property IS_BLACKBOX [get_cells $cell]]} {
1593### set start_time [clock seconds]
1594### puts "\tCritical Warning: Partition cell \'$cell\' is not a blackbox. This likely occurred because OOC synthesis was not used. This can cause illegal optimization. Please verify it is intentional that this cell is not a blackbox at this stage in the flow.\nResolution: Caving out cell to make required blackbox. \[[clock format $start_time -format {%a %b %d %H:%M:%S %Y}]\]"
1595### command "update_design -cells $cell -black_box" "$resultDir/update_design_blackbox_$name.log"
1596### set end_time [clock seconds]
1597### log_time update_design $start_time $end_time 0 "Create blackbox for $name"
1598### }
1599### if {[string match $state "greybox"]} {
1600### command "set_msg_config -id \"Constraints 18-514\" -suppress"
1601### command "set_msg_config -id \"Constraints 18-515\" -suppress"
1602### command "set_msg_config -id \"Constraints 18-402\" -suppress"
1603### set start_time [clock seconds]
1604### puts "\t#HD: Inserting LUT1 buffers on interface of $name \[[clock format $start_time -format {%a %b %d %H:%M:%S %Y}]\]"
1605### command "update_design -cells $cell -buffer_ports" "$resultDir/update_design_bufferport_$name.log"
1606### set end_time [clock seconds]
1607### log_time update_design $start_time $end_time 0 "Buffer blackbox RM $name"
1608### #If verbose it turned up, write out intermediate link_design DCP files
1609### if {$dcpLevel > 1} {
1610### set start_time [clock seconds]
1611### command "write_checkpoint -force $resultDir/${top}_link_design_intermediate.dcp" "$resultDir/write_checkpoint.log"
1612### set end_time [clock seconds]
1613### log_time write_checkpoint $start_time $end_time 0 "Intermediate link_design checkpoint for debug"
1614### }
1615### set budgetXDC $xdcDir/${module}_budget.xdc
1616### if {![file exists $budgetXDC] || ${pr.budget}} {
1617### set start_time [clock seconds]
1618### puts "\t#HD: Creating budget constraints for greybox $name \[[clock format $start_time -format {%a %b %d %H:%M:%S %Y}]\]"
1619### create_pr_budget -cell $cell -file $budgetXDC -exclude $budgetExclude
1620### set end_time [clock seconds]
1621### log_time create_budget $start_time $end_time 0 "Create budget constraints for $name"
1622### }
1623### set start_time [clock seconds]
1624### #DW - Add DT on port nets to fix issues seen on RP with embedded MIG where port connections got optimized in greybox flow.
1625### #command "set_property DONT_TOUCH 1 \[get_nets -of \[get_ports -of \[get_nets -of \[get_pins $cell/*\]\]\]\]"
1626### readXDC $budgetXDC
1627### set end_time [clock seconds]
1628### log_time read_xdc $start_time $end_time 0 "Read in budget constraints for $name"
1629### } else {
1630### set fileSplit [split $partitionFile "."]
1631### set fileType [lindex $fileSplit end]
1632### if {[string match $fileType "dcp"]} {
1633### set start_time [clock seconds]
1634### puts "\tReading in checkpoint $partitionFile for $cell ($module) \[[clock format $start_time -format {%a %b %d %H:%M:%S %Y}]\]"
1635### command "read_checkpoint -cell $cell $partitionFile -strict" "$resultDir/read_checkpoint_${module}_${name}.log"
1636### set end_time [clock seconds]
1637### log_time read_checkpoint $start_time $end_time 0 "Resolve blackbox for $name"
1638### } elseif {[string match $fileType "edf"] || [string match $fileType "edn"]} {
1639### set start_time [clock seconds]
1640### puts "\tUpdating design with $partitionFile for $cell ($module) \[[clock format $start_time -format {%a %b %d %H:%M:%S %Y}]\]"
1641### command "update_design -cells $cell -from_file $partitionFile" "$resultDir/update_design_$name.log"
1642### set end_time [clock seconds]
1643### log_time update_design $start_time $end_time 0 "Resolve blackbox for $name"
1644### } else {
1645### set errMsg "\nERROR: Invalid file type \"$fileType\" for $partitionFile.\n"
1646### error $errMsg
1647### }
1648### }
1649###
1650### #Read in Module XDC if module is not imported or greybox
1651### if {[string match $state "implement"]} {
1652### ## Read in module Impl XDC files
1653### set implXDC [get_attribute module $module implXDC]
1654### if {[llength $implXDC] > 0} {
1655### set start_time [clock seconds]
1656### readXDC $implXDC
1657### set end_time [clock seconds]
1658### log_time read_xdc $start_time $end_time 0 "Cell level XDCs for $name"
1659### } else {
1660### puts "\tInfo: No cell XDC file specified for $cell"
1661### }
1662### }
1663###
1664### #Lock imported Partitions
1665### if {[string match $state "import"] && !$incr} {
1666### if {![llength $level]} {
1667### set level "routing"
1668### }
1669### set start_time [clock seconds]
1670### puts "\tLocking $cell \[[clock format $start_time -format {%a %b %d %H:%M:%S %Y}]\]"
1671### command "lock_design -level $level $cell" "$resultDir/lock_design_$name.log"
1672### set end_time [clock seconds]
1673### log_time lock_design $start_time $end_time 0 "Locking cell $cell at level routing"
1674### }
1675###
1676### #Do up front check for PR for Pblocks on Partitions
1677### if {$verbose && $pr} {
1678### set rpPblock [get_pblocks -quiet -of [get_cells $cell]]
1679### if {![llength $rpPblock]} {
1680### set errMsg "ERROR: No pblock found for PR cell $cell."
1681### #error $errMsg
1682### }
1683### }
1684###
1685### #Create constraints for OOC partitions if TopDown run.
1686### if {$td && [string match $type "ooc"]} {
1687### puts "\t#HD: Creating OOC constraints for $cell"
1688### set start_time [clock seconds]
1689### create_set_logic $name $cell $xdcDir
1690### create_ooc_clocks $name $cell $xdcDir
1691### set end_time [clock seconds]
1692### log_time "create_constraints" $start_time $end_time 0 "Create necessary OOC constraints"
1693### }
1694###
1695### #If verbose it turned up, write out intermediate link_design DCP files
1696### if {$dcpLevel > 1} {
1697### set start_time [clock seconds]
1698### command "write_checkpoint -force $resultDir/${top}_link_design_intermediate.dcp" "$resultDir/write_checkpoint.log"
1699### set end_time [clock seconds]
1700### log_time write_checkpoint $start_time $end_time 0 "Intermediate link_design checkpoint for debug"
1701### }
1702### }; #End: Process each partition that is not Top
1703### }
1704###
1705### ##############################################
1706### # Read in any linkXDC files
1707### ##############################################
1708### #if {[llength $linkXDC] > 0 && [string match $topState "implement"]} {}
1709### if {[llength $linkXDC] > 0 } {
1710### set start_time [clock seconds]
1711### readXDC $linkXDC
1712### set end_time [clock seconds]
1713### log_time read_xdc $start_time $end_time 0 "Post link_design XDC files"
1714### } else {
1715### puts "\tInfo: No post-link_design XDC file specified for $impl"
1716### }
1717###
1718### if {$dcpLevel > 0} {
1719### set start_time [clock seconds]
1720### puts "\tWriting post-link_design checkpoint: $resultDir/${top}_link_design.dcp \[[clock format $start_time -format {%a %b %d %H:%M:%S %Y}]\]\n"
1721### command "write_checkpoint -force $resultDir/${top}_link_design.dcp" "$resultDir/write_checkpoint.log"
1722### set end_time [clock seconds]
1723### log_time write_checkpoint $start_time $end_time 0 "Post link_design checkpoint"
1724### }
1725###
1726### ##############################################
1727### # Write out final link_design DCP
1728### ##############################################
1729### if {$verbose > 1} {
1730### set start_time [clock seconds]
1731### command "report_utilization -file $reportDir/${top}_utilization_link_design.rpt" "$resultDir/temp.log"
1732### set end_time [clock seconds]
1733### log_time report_utilization $start_time $end_time
1734### }
1735### puts "\t#HD: Completed link_design"
1736### puts "\t##########################\n"
1737###
1738### ##############################################
1739### # Run Methodology DRCs checks
1740### ##############################################
1741### #Run methodology DRCs and catch any Critical Warnings or Error (module ruledeck quiet)
1742### if {$verbose > 1} {
1743### set start_time [clock seconds]
1744### check_drc $top methodology_checks 1
1745### set end_time [clock seconds]
1746### log_time report_drc $start_time $end_time 0 "methodology checks"
1747### #Run timing DRCs and catch any Critical Warnings or Error (module ruledeck quiet)
1748### set start_time [clock seconds]
1749### check_drc $top timing_checks 1
1750### set end_time [clock seconds]
1751### log_time report_drc $start_time $end_time 0 "timing_checks"
1752### }
1753### }
1754###
1755### ############################################################################################
1756### # Implementation steps: opt_design, place_design, phys_opt_design, route_design
1757### ############################################################################################
1758### if {$opt} {
1759### impl_step opt_design $top $opt_options $opt_directive ${opt.pre}
1760### if {$incr} {
1761### set imports {}
1762### foreach partition $partitions {
1763### lassign $partition module cell state name type level dcp
1764### #Process each partition that is not Top
1765### set moduleName [get_attribute module $module moduleName]
1766### if {![string match $moduleName $top]} {
1767### if {[string match $state "import"]} {
1768### lappend imports $cell
1769### }
1770### }
1771### }
1772### if {[llength $imports]} {
1773### set start_time [clock seconds]
1774### command "read_checkpoint -incremental -only_reuse \{[join $imports]\} $dcpDir/${top}_incremental.dcp -fix_reuse" "$resultDir/read_incremental.log"
1775### set end_time [clock seconds]
1776### log_time read_checkpoint $start_time $end_time 0 "Read incremental Checkpoint for $imports"
1777### if {$dcpLevel > 0} {
1778### set start_time [clock seconds]
1779### puts "\tWriting post-opt_design checkpoint with incremental data: $resultDir/${top}_opt_design_incremental.dcp \[[clock format $start_time -format {%a %b %d %H:%M:%S %Y}]\]\n"
1780### command "write_checkpoint -force $resultDir/${top}_opt_design_incremental.dcp" "$resultDir/write_checkpoint.log"
1781### set end_time [clock seconds]
1782### log_time write_checkpoint $start_time $end_time 0 "Post opt_design checkpoint with incremental data"
1783### }
1784### }
1785### }
1786### }
1787###
1788### if {$place} {
1789### #Report out all RM clocks for PR runs
1790### #COMMENT out because not working with designs that have clocks with [] in the name (ie. clk[myclk])
1791### #TODO: Debug this issue. Figure out a way to send clock names with [] escaped.
1792### # if {$pr} {
1793### # foreach partition $partitions {
1794### # lassign $partition module cell state name type level dcp
1795### # if {![string match $cell $top]} {
1796### # if {![llength $name]} {
1797### # set name [lindex [split $cell "/"] end]
1798### # }
1799### # get_rp_clocks $cell $reportDir/${name}_clocks.rpt
1800### # }
1801### # }
1802### # }
1803###
1804### impl_step place_design $top $place_options $place_directive ${place.pre}
1805###
1806### #### If Top-Down, write out XDCs
1807### if {$td && $verbose > 0} {
1808### puts "\n\tWriting instance level XDC files."
1809### foreach partition $partitions {
1810### lassign $partition module cell state name type level dcp
1811### if {![string match $cell $top]} {
1812### if {![llength $name]} {
1813### set name [lindex [split $cell "/"] end]
1814### }
1815### write_hd_xdc $name $cell $xdcDir
1816###
1817### #Check for CLOCK_ROOT values and write them out as USER_CLOCK_ROOT if found.
1818### set clockNets [get_nets -quiet -hier -filter "CLOCK_ROOT!=\"\" && NAME=~$cell/*"]
1819### if {[llength $clockNets]} {
1820### set fh [open "$xdcDir/${name}_phys.xdc" a]
1821### puts $fh "\n#### Clock root values from Top-Down run ####"
1822### foreach net $clockNets {
1823### puts $fh "set_property USER_CLOCK_ROOT [get_property CLOCK_ROOT $net] \[get_nets [lindex [split $net /] end]\]"
1824### }
1825### close $fh
1826### }
1827### }
1828### }
1829### }
1830### }
1831###
1832### if {$phys} {
1833### impl_step phys_opt_design $top $phys_options $phys_directive ${phys.pre}
1834### }
1835###
1836### if {$route} {
1837### impl_step route_design $top $route_options $route_directive ${route.pre}
1838###
1839### if {$post_phys} {
1840### impl_step post_phys_opt $top $post_phys_options $post_phys_directive ${post_phys.pre}
1841### }
1842###
1843### # Added by YotamP-Mellanox: Reroute antennas (workaround)
1844### #puts "\n#### YotamP: Re-route antennas ####"
1845### #route_design -unroute –nets [get_nets –top –hier –filter ROUTE_STATUS==ANTENNAS]
1846### #lock_design -level routing ; # To lock down all other routes
1847### #route_design
1848###
1849### # Added by YotamP-Mellanox: Reroute imported nets with collisions (workaround)
1850### #if {$ic} {
1851### # if {[string match "import" $topState]} {
1852### # puts "\n#### YotamP: Re-route imported nets with collisions ####"
1853### # set conflicts [get_nets -quiet -top -hier -filter ROUTE_STATUS==CONFLICTS]
1854### # if {[llength $conflicts]} {
1855### # set_property IS_ROUTE_FIXED 0 [get_nets $conflicts]
1856### # route_design
1857### # }
1858### # }
1859### #}
1860###
1861### #Run report_timing_summary on final design
1862### set start_time [clock seconds]
1863### command "report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -file $reportDir/${top}_timing_summary.rpt" "$resultDir/temp.log"
1864### set end_time [clock seconds]
1865### log_time report_timing $start_time $end_time 0 "Timing Summary"
1866###
1867### #Run a final DRC that catches any Critical Warnings (module ruledeck quiet)
1868### set start_time [clock seconds]
1869### if {$ooc} {
1870### check_drc $top default ${drc.quiet}
1871### } else {
1872### check_drc $top bitstream_checks ${drc.quiet}
1873### }
1874###
1875### set end_time [clock seconds]
1876### log_time report_drc $start_time $end_time 0 "bistream_checks"
1877###
1878### #Report PR specific statitics for debug and analysis
1879### if {$pr} {
1880### command "debug::report_design_status" "$reportDir/${top}_design_status.rpt"
1881### }
1882###
1883### getTimingInfo
1884### set impl_end [clock seconds]
1885### log_time final $impl_start $impl_end
1886### }
1887###
1888###
1889### set extras_start [clock seconds]
1890### if {![file exists $dcpDir]} {
1891### command "file mkdir $dcpDir"
1892### }
1893###
1894### #Write out checkpoints for OOC implementations
1895### if {$iso || $ooc} {
1896### set pblock [get_pblocks -filter PARENT==ROOT]
1897### set dcp "$resultDir/${top}_route_design.dcp"
1898### command "file copy -force $dcp $dcpDir/${pblock}_${top}_route_design.dcp"
1899### }
1900###
1901### if {$ic || $pr} {
1902### #Write out cell checkpoints for all Partitions and create black_box
1903### #Add log_time with header to make sure table always has a header (grebybox case, etc)
1904### log_time Post-Process $start_time $start_time 1 "Post-process HD and PR designs"
1905### foreach partition $partitions {
1906### lassign $partition module cell state name type level dcp
1907### #Don't try to get moduleName for greybox Partitions as the name can be random
1908### if {![string match "greybox" $state]} {
1909### set moduleName [get_attribute module $module moduleName]
1910### } else {
1911### set moduleName $module
1912### }
1913###
1914### #Only write out cell DCPs for implemented cells, or imported cells if Top/Static was implemented
1915### # if {![string match $moduleName $top] && ([string match $state "implement"] || [string match $topState "implement"])} { }
1916### #DW This didnt' quite work. Scripts export greybox DCPs when #topState=implement. Why was this needed? Simplify for now to the following
1917### if {![string match $moduleName $top] && ([string match $state "implement"])} {
1918### if {![llength $name]} {
1919### set name [lindex [split $cell "/"] end]
1920### }
1921### set start_time [clock seconds]
1922### set pblock [get_pblocks -of [get_cells $cell]]
1923### #Pblock required to generate unique name. Do not write out cell DCP if no Pblock exists.
1924### if {[llength $pblock]} {
1925### set dcp "$resultDir/${pblock}_${module}_route_design.dcp"
1926### command "write_checkpoint -force -cell $cell $dcp" "$resultDir/write_checkpoint.log"
1927### set end_time [clock seconds]
1928### log_time write_checkpoint $start_time $end_time 0 "Write cell checkpoint for $cell"
1929### command "file copy -force $dcp $dcpDir"
1930### } else {
1931### puts "Critical Warning: No pblock found for $cell. No cell-level DCP will be written out."
1932### }
1933### }
1934###
1935### #Carve out all partitions if Top/Static was implemented
1936### if {![string match $moduleName $top] && [string match $topState "implement"]} {
1937### set start_time [clock seconds]
1938### puts "\tCarving out $cell to be a black box \[[clock format $start_time -format {%a %b %d %H:%M:%S %Y}]\]"
1939### command "update_design -cell $cell -black_box" "$resultDir/carve_$name.log"
1940### #Temporary - Remove once HD.RECONFIG is not needed for HD platform support
1941### if {$ic} {
1942### command "set_property HD.RECONFIGURABLE 0 \[get_cells $cell\]"
1943### command "route_design -unroute -nets \[get_nets -of \[get_pins $cell/*\]\]" "$resultDir/unroute.log"
1944### }
1945### set end_time [clock seconds]
1946### log_time update_design $start_time $end_time 0 "Carve out (blackbox) $cell"
1947### }
1948### }
1949### }
1950###
1951### #Write out implemented version of Top for import in subsequent runs
1952### if {$pr || $ic} {
1953### foreach partition $partitions {
1954### lassign $partition module cell state name type level dcp
1955### #Skip this step for greybox partitions to avoid errors in getting moduleName property
1956### if {[string match "greybox" $state]} {
1957### continue
1958### }
1959### set moduleName [get_attribute module $module moduleName]
1960### if {[string match $moduleName $top] && [string match $state "implement"]} {
1961### set start_time [clock seconds]
1962### puts "\t#HD: Locking $top and exporting results \[[clock format $start_time -format {%a %b %d %H:%M:%S %Y}]\]"
1963### #Temporary - Remove once lock_design restriction is fixed for in-context flows
1964### if {$ic} {
1965### command "set_property CONTAIN_ROUTING 1 \[get_pblocks\]"
1966### }
1967### command "lock_design -level routing" "$resultDir/lock_design_$top.log"
1968### #Temporary - Remove once lock_design restriction is fixed for in-context flows
1969### if {$ic} {
1970### command "set_property CONTAIN_ROUTING 0 \[get_pblocks\]"
1971### }
1972### set end_time [clock seconds]
1973### log_time lock_design $start_time $end_time 0 "Lock placement and routing of $top"
1974### if {$pr} {
1975### set topDCP "$resultDir/${top}_static.dcp"
1976### }
1977### if {$ic} {
1978### set topDCP "$resultDir/${top}_routed.dcp"
1979### }
1980### set start_time [clock seconds]
1981### command "write_checkpoint -force $topDCP" "$resultDir/write_checkpoint.log"
1982### command "file copy -force $topDCP $dcpDir"
1983### set end_time [clock seconds]
1984### log_time write_checkpoint $start_time $end_time 0 "Write out locked Static checkpoint"
1985### }
1986### }
1987### }
1988###
1989###
1990### if {$incr} {
1991### set start_time [clock seconds]
1992### command "write_checkpoint -force $resultDir/${top}_incremental.dcp" "$resultDir/write_checkpoint.log"
1993### command "file copy -force $resultDir/${top}_incremental.dcp $dcpDir"
1994### set end_time [clock seconds]
1995### log_time write_checkpoint $start_time $end_time 1 "Write out locked incremental checkpoint"
1996### }
1997###
1998### #For PR, don't write out bitstreams until after PR_VERIFY has run. See run.tcl
1999### #For OOC, don't write out bitstreams
2000### if {$bitstream && !$pr && !$ooc} {
2001### impl_step write_bitstream $top $bitstream_options none ${bitstream.pre} $bitstream_settings
2002### }
2003###
2004### #For ISO flow, disable DRCs so that OOC bitstream can be written
2005### if {$iso && $bitstream} {
2006### command "set_property IS_ENABLED {false} \[get_drc_checks\]"
2007### impl_step write_bitstream $ooc_inst $bitstream_options none ${bitstream.pre}
2008### command "reset_drc_check \[get_drc_checks]"
2009### }
2010###
2011### set extras_end [clock seconds]
2012### log_time final $extras_start $extras_end
2013### command "puts \"#HD: Implementation $impl complete\\n\""
2014### command "close_project"
2015### close $rfh
2016### close $cfh
2017### close $wfh
2018### }
2019### proc impl_step {phase instance {options none} {directive none} {pre none} {settings none} } {
2020### global dcpLevel
2021### global verbose
2022### upvar impl impl
2023### upvar resultDir resultDir
2024### upvar reportDir reportDir
2025###
2026### #Make sure $phase is valid and set checkpoint in case no design is open
2027### if {[string match $phase "opt_design"]} {
2028### set checkpoint1 "$resultDir/${instance}_link_design.dcp"
2029### } elseif {[string match $phase "place_design"]} {
2030### set checkpoint1 "$resultDir/${instance}_opt_design.dcp"
2031### } elseif {[string match $phase "phys_opt_design"]} {
2032### set checkpoint1 "$resultDir/${instance}_place_design.dcp"
2033### } elseif {[string match $phase "route_design"]} {
2034### set checkpoint1 "$resultDir/${instance}_phys_opt_design.dcp"
2035### set checkpoint2 "$resultDir/${instance}_place_design.dcp"
2036### } elseif {[string match $phase "post_phys_opt"]} {
2037### set checkpoint1 "$resultDir/${instance}_route_design.dcp"
2038### } elseif {[string match $phase "write_bitstream"]} {
2039### set checkpoint1 "$resultDir/${instance}_post_phys_opt.dcp"
2040### set checkpoint2 "$resultDir/${instance}_route_design.dcp"
2041### } else {
2042### set errMsg "\nERROR: Value $phase is not a recognized step of implementation. Valid values are \"opt_design\", \"place_design\", \"phys_opt_design\", or \"route_design\"."
2043### error $errMsg
2044### }
2045### #If no design is open
2046### if { [catch {current_instance > $resultDir/temp.log} errMsg] && $verbose > 0 } {
2047### puts "\tNo open design"
2048### if {[info exists checkpoint1] || [info exists checkpoint2]} {
2049### if {[file exists $checkpoint1]} {
2050### puts "\tOpening checkpoint $checkpoint1 for $instance"
2051### command "open_checkpoint $checkpoint1" "$resultDir/open_checkpoint_${instance}_$phase.log"
2052### if { [catch {current_instance > $resultDir/temp.log} errMsg] } {
2053### command "link_design"
2054### }
2055### } elseif {[file exists $checkpoint2]} {
2056### puts "\tOpening checkpoint $checkpoint2 for $instance"
2057### command "open_checkpoint $checkpoint2" "$resultDir/open_checkpoint_${instance}_$phase.log"
2058### if { [catch {current_instance > $resultDir/temp.log} errMsg] } {
2059### command "link_design"
2060### }
2061### } else {
2062### set errMsg "\nERROR: Checkpoint file not found. Please rerun necessary steps."
2063### error $errMsg
2064### }
2065### } else {
2066### set errMsg "\nERROR: No checkpoint defined."
2067### error $errMsg
2068### }
2069### }
2070###
2071### #Run any specified pre-phase scripts
2072### if {![string match $pre "none"] && ![string match $pre ""] } {
2073### foreach script $pre {
2074### if {[file exists $script]} {
2075### puts "\t#HD: Running pre-$phase script $script"
2076### command "source $script" "$resultDir/pre_${phase}_script.log"
2077### } else {
2078### set errMsg "\nERROR: Script $script specified for pre-${phase} does not exist"
2079### error $errMsg
2080### }
2081### }
2082### }
2083###
2084### #Append options or directives to command
2085### if {[string match $phase "write_bitstream"]} {
2086### set impl_step "$phase -force -file $resultDir/$instance"
2087### } elseif {[string match $phase "post_phys_opt"]} {
2088### set impl_step "phys_opt_design"
2089### } else {
2090### set impl_step $phase
2091### }
2092###
2093### if {[string match $options "none"]==0 && [string match $options ""]==0} {
2094### append impl_step " $options"
2095### }
2096### if {[string match $directive "none"]==0 && [string match $directive ""]==0} {
2097### append impl_step " -directive $directive"
2098### }
2099### if {[string match $settings "none"]==0 && [string match $settings ""]==0} {
2100### foreach setting $settings {
2101### puts "\tSetting property $setting"
2102### command "set_property $setting \[current_design]"
2103### }
2104### }
2105###
2106### #Run the specified Implementation phase
2107### puts "\n\t#HD: Running $impl_step for $impl"
2108###
2109### set log "$resultDir/${instance}_$phase.log"
2110### puts "\tWriting Results to $log"
2111###
2112### set start_time [clock seconds]
2113### puts "\t$phase start time: \[[clock format $start_time -format {%a %b %d %H:%M:%S %Y}]\]"
2114### command "$impl_step" "$log"
2115### set end_time [clock seconds]
2116### log_time $phase $start_time $end_time 0 "$impl_step"
2117### command "puts \"\t#HD: Completed: $phase\""
2118### puts "\t################################"
2119###
2120### #Write out checkpoint for successfully completed phase
2121### if {($dcpLevel > 0 || [string match $phase "route_design"]) && ![string match $phase "write_bitstream"]} {
2122### set start_time [clock seconds]
2123### puts "\tWriting post-$phase checkpoint: $resultDir/${instance}_$phase.dcp \[[clock format $start_time -format {%a %b %d %H:%M:%S %Y}]\]\n"
2124### command "write_checkpoint -force $resultDir/${instance}_$phase.dcp" "$resultDir/write_checkpoint.log"
2125### set end_time [clock seconds]
2126### log_time write_checkpoint $start_time $end_time 0 "Post-$phase checkpoint"
2127### }
2128###
2129### #Write out additional reports controled by verbose level
2130### if {$verbose > 1 || [string match $phase "route_design"]} {
2131### set start_time [clock seconds]
2132### command "report_utilization -file $reportDir/${instance}_utilization_${phase}.rpt" "$resultDir/temp.log"
2133### set end_time [clock seconds]
2134### log_time report_utilization $start_time $end_time
2135### }
2136### if {[string match $phase "opt_design"]} {
2137### set start_time [clock seconds]
2138### command "close_project"
2139### command "open_checkpoint $resultDir/${instance}_$phase.dcp" "$resultDir/open_checkpoint.log"
2140### set end_time [clock seconds]
2141### log_time open_checkpoint $start_time $end_time
2142### }
2143### if {[string match $phase "route_design"]} {
2144### set start_time [clock seconds]
2145### command "report_route_status -file $reportDir/${instance}_route_status.rpt" "$resultDir/temp.log"
2146### set end_time [clock seconds]
2147### log_time report_route_status $start_time $end_time
2148### }
2149### }
2150## proc get_module_file { module } {
2151## global synthDir
2152## global netlistDir
2153##
2154## if {![info exists synthDir]} {
2155## set synthDir "."
2156## }
2157## if {![info exists netlistDir]} {
2158## set netlistDir "."
2159## }
2160##
2161## set moduleName [get_attribute module $module moduleName]
2162## set synthDCP [get_attribute module $module synthCheckpoint]
2163## set searchFiles [list $synthDCP \
2164## $synthDir/$module/${moduleName}_synth.dcp \
2165## $netlistDir/$module/${moduleName}.edf \
2166## $netlistDir/$module/${moduleName}.edn \
2167## $netlistDir/$module/${moduleName}.ngc \
2168## ]
2169## set moduleFile ""
2170## foreach file $searchFiles {
2171## if {[file exists $file]} {
2172## set moduleFile $file
2173## break
2174## }
2175## }
2176## if {![llength $moduleFile]} {
2177## set errMsg "\nERROR: No synthesis netlist or checkpoint file found for $module."
2178## append errMsg "\nSearched directories:"
2179## foreach file $searchFiles {
2180## append errMsg "\t$file\n"
2181## }
2182## error $errMsg
2183## }
2184## return $moduleFile
2185## }
2186## proc get_ooc_results { implementations } {
2187## global dcpLevel
2188## upvar resultDir resultDir
2189##
2190## foreach ooc $implementations {
2191## set instName [get_attribute ooc $ooc inst]
2192## set hierInst [get_attribute ooc $ooc hierInst]
2193## set readCheckpoint [get_attribute ooc $ooc implCheckpoint]
2194## set preservation [get_attribute ooc $ooc preservation]
2195## set hd.isolated [get_attribute ooc $ooc hd.isolated]
2196##
2197## if {![file exists $readCheckpoint]} {
2198## set errMsg "\nERROR: Specified OOC Checkpoint $readCheckpoint does not exist."
2199## error $errMsg
2200## }
2201##
2202## if {[get_property IS_BLACKBOX [get_cells $hierInst]]} {
2203## set start_time [clock seconds]
2204## puts "\tReading in checkpoint $readCheckpoint for $instName \[[clock format $start_time -format {%a %b %d %H:%M:%S %Y}]\]"
2205## if {${hd.isolated}} {
2206## command "set_property HD.ISOLATED 1 \[get_cells $hierInst]"
2207## } else {
2208## command "set_property HD.PARTITION 1 \[get_cells $hierInst]"
2209## }
2210## command "read_checkpoint -cell $hierInst $readCheckpoint -strict" "$resultDir/read_checkpoint_${instName}.log"
2211## set end_time [clock seconds]
2212## log_time read_checkpoint $start_time $end_time 0 "Resolve blacbox for $instName"
2213## if {[string match $preservation "logical" ] || \
2214## [string match $preservation "placement"] || \
2215## [string match $preservation "routing" ]} {
2216## set start_time [clock seconds]
2217## puts "\tLocking $hierInst \[[clock format $start_time -format {%a %b %d %H:%M:%S %Y}]\]"
2218## command "lock_design -level $preservation $hierInst" "$resultDir/lock_design_$instName.log"
2219## set end_time [clock seconds]
2220## log_time lock_design $start_time $end_time 0 "Locking cell $hierInst at level $preservation"
2221## } elseif {[string match $preservation "none"] || [string match $preservation ""] } {
2222## puts "\tSkipping lock_design for $hierInst"
2223## } else {
2224## set errMsg "\nERROR: Unknown value \"$preservation\" specified for lock_design for cell $hierInst."
2225## error $errMsg
2226## }
2227## } else {
2228## puts "Cell $hierInst, implemented as OOC, is not a blackbox. OOC implementation results will not be used."
2229## }
2230##
2231## if {$dcpLevel > 1} {
2232## set start_time [clock seconds]
2233## command "write_checkpoint -force $resultDir/${instName}_link_design_intermediate.dcp" "$resultDir/write_checkpoint.log"
2234## set end_time [clock seconds]
2235## log_time write_checkpoint $start_time $end_time 0 "Intermediate link_design checkpoint"
2236## }
2237## }
2238## }
2239## proc generate_pr_binfiles { config } {
2240## upvar bitDir bitDir
2241##
2242## set top [get_attribute impl $config top]
2243## set partitions [get_attribute impl $config partitions]
2244## set icap [get_attribute impl $config cfgmem.icap]
2245## set pcap [get_attribute impl $config cfgmem.pcap]
2246## set offset [get_attribute impl $config cfgmem.offset]
2247## set size [get_attribute impl $config cfgmem.size]
2248## set interface [get_attribute impl $config cfgmem.interface]
2249## if {$icap || $pcap} {
2250## foreach partition $partitions {
2251## lassign $partition module cell state name type level dcp
2252## if {![string match $cell $top]} {
2253## set pblock [get_pblock -quiet -of [get_cells $cell]]
2254## set bitFile "$bitDir/${config}_${pblock}_partial.bit"
2255## if {![file exists $bitFile]} {
2256## puts "\tCritical Warning: No bit file found for $name in configuration $config. Skipping BIN file generation. Expected file \n\t$bitFile.\n\tRun write_bitstream first to generate the expected file."
2257## return
2258## }
2259## if {$icap} {
2260## set logFile "$bitDir/write_cfgmem_${config}_${name}_icap.log"
2261## set msg "\t#HD: Generating ICAP formatted BIN file for $name of Configuration $config"
2262## command "puts \"$msg\""
2263## set start_time [clock seconds]
2264## set binFile "$bitDir/${config}_${pblock}_partial_icap.bin"
2265## #command "write_cfgmem -force -format BIN -interface $interface -loadbit \"$offset $bitFile\" -size $size $binFile" $logFile
2266## command "write_cfgmem -force -format BIN -interface $interface -loadbit \"$offset $bitFile\" $binFile" $logFile
2267## set end_time [clock seconds]
2268## log_time write_cfgmem $start_time $end_time 1 "Generate ICAP format bin file for ${config}(${name})"
2269## }
2270## if {$pcap} {
2271## set logFile "$bitDir/write_cfgmem_${config}_${name}_pcap.log"
2272## set msg "\t#HD: Generating PCAP formatted BIN file for $name of Configuration $config"
2273## command "puts \"$msg\""
2274## set start_time [clock seconds]
2275## set binFile "$bitDir/${config}_${pblock}_partial_pcap.bin"
2276## #command "write_cfgmem -force -format BIN -interface $interface -disablebitswap -loadbit \"$offset $bitFile\" -size $size $binFile" $logFile
2277## command "write_cfgmem -force -format BIN -interface $interface -disablebitswap -loadbit \"$offset $bitFile\" $binFile" $logFile
2278## set end_time [clock seconds]
2279## log_time write_cfgmem $start_time $end_time 1 "Generate PCAP format bin file for ${config}(${name})"
2280## }
2281## }
2282## }
2283## } else {
2284## puts "\tINFO: Skipping partial BIN file generation for Configuration $config."
2285## }
2286## }
2287## proc generate_pr_bitstreams { configs } {
2288## global dcpDir bitDir implDir
2289##
2290## #Set a default directory to write bitstreams if not already defined
2291## if {![info exists bitDir]} {
2292## set bitDir "./Bitstreams"
2293## }
2294##
2295## #command "file delete -force $bitDir"
2296## if {![file exists $bitDir]} {
2297## command "file mkdir $bitDir"
2298## }
2299##
2300## foreach config $configs {
2301## set top [get_attribute impl $config top]
2302## set partitions [get_attribute impl $config partitions]
2303## set post_phys [get_attribute impl $config post_phys]
2304## set bitstream [get_attribute impl $config bitstream]
2305## set bitstream.pre [get_attribute impl $config bitstream.pre]
2306## set bitOptions [get_attribute impl $config bitstream_options]
2307## set bitSettings [get_attribute impl $config bitstream_settings]
2308## if {$bitstream} {
2309## set start_time [clock seconds]
2310## set msg "\t#HD: Running write_bitstream on $config"
2311## command "puts \"$msg\""
2312## set logFile "$bitDir/write_bitstream_${config}.log"
2313## if {$post_phys} {
2314## set configFile "$implDir/$config/${top}_post_phys_opt.dcp"
2315## } else {
2316## set configFile "$implDir/$config/${top}_route_design.dcp"
2317## }
2318## if {[file exists $configFile]} {
2319## command "open_checkpoint $configFile" "$bitDir/open_checkpoint_$config.log"
2320## #Check for dbg_hub and write out probes
2321## if {[llength [get_cells -quiet -hier -filter REF_NAME==dbg_hub_CV]]} {
2322## command "write_debug_probes -force $bitDir/$config" "$bitDir/write_debug_probes_$config.log"
2323## }
2324##
2325## #Run any pre.hook scripts for write_bitstream
2326## foreach script ${bitstream.pre} {
2327## if {[file exists $script]} {
2328## puts "\t#HD: Running pre-bitstream script $script"
2329## command "source $script" "$bitDir/pre_bitstream_script.log"
2330## } else {
2331## set errMsg "\nERROR: Script $script specified for pre-bitstream does not exist"
2332## error $errMsg
2333## }
2334## }
2335## #Set any design level bistream properties
2336## foreach setting $bitSettings {
2337## puts "\tSetting property $setting"
2338## command "set_property $setting \[current_design]"
2339## }
2340## foreach partition $partitions {
2341## lassign $partition module cell state name type level dcp
2342## if {[string match $cell $top]} {
2343## #Generate full bitstream only
2344## command "write_bitstream -force $bitOptions $bitDir/${config}_full -no_partial_bitfile" "$bitDir/${config}.log"
2345## } else {
2346## #Generate partials using -cell for better naming
2347## command "write_bitstream -force $bitOptions -cell $cell $bitDir/${config}_${module}_partial.bit" "$bitDir/${config}_${module}.log"
2348## }
2349## }
2350## } else {
2351## puts "\tERROR: The route_design DCP $configFile was not found for $config"
2352## continue
2353## }
2354##
2355## set end_time [clock seconds]
2356## log_time write_bitstream $start_time $end_time 1 $config
2357## generate_pr_binfiles $config
2358## command "close_project" "$bitDir/temp.log"
2359## } else {
2360## puts "\tSkipping write_bitstream for Configuration $config with attribute \"bitstream\" set to \'$bitstream\'"
2361## }
2362## }
2363## }
2364## proc verify_configs { configs } {
2365## global implDir
2366##
2367## #Compare Initial Configuration to all others
2368## set initialConfig [lindex $configs 0]
2369## set post_phys [get_attribute impl $initialConfig post_phys]
2370## set initialConfigTop [get_attribute impl $initialConfig top]
2371## if {$post_phys} {
2372## set initialConfigFile $implDir/$initialConfig/${initialConfigTop}_post_phys_opt.dcp
2373## } else {
2374## set initialConfigFile $implDir/$initialConfig/${initialConfigTop}_route_design.dcp
2375## }
2376##
2377## set numConfigs [llength $configs]
2378## set additionalConfigs ""
2379## set additionalConfigFiles ""
2380## for {set i 1} {$i < $numConfigs} {incr i} {
2381## set config [lindex $configs $i]
2382## set verify [get_attribute impl $config verify]
2383## set post_phys [get_attribute impl $config post_phys]
2384## if {$verify} {
2385## lappend additionalConfigs $config
2386## set configTop [get_attribute impl $config top]
2387## if {$post_phys} {
2388## set configFile $implDir/$config/${configTop}_post_phys_opt.dcp
2389## } else {
2390## set configFile $implDir/$config/${configTop}_route_design.dcp
2391## }
2392## lappend additionalConfigFiles $configFile
2393## } else {
2394## puts "\tSkipping pr_verify for Configuration $config with attribute \"verify\" set to \'$verify\'"
2395## }
2396## }
2397##
2398## if {[llength $additionalConfigFiles]} {
2399## set start_time [clock seconds]
2400## set msg "#HD: Running pr_verify between initial config $initialConfig and subsequent configurations $additionalConfigs"
2401## command "puts \"$msg\""
2402## set logFile "pr_verify_results.log"
2403## command "pr_verify -full_check -initial $initialConfigFile -additional \"$additionalConfigFiles\"" $logFile
2404## #Parse log file for errors or successful results
2405## if {[file exists $logFile]} {
2406## set lfh [open $logFile r]
2407## set log_data [read $lfh]
2408## close $lfh
2409## set log_lines [split $log_data "\n" ]
2410## foreach line $log_lines {
2411## if {[string match "*Vivado 12-3253*" $line] || [string match "*ERROR:*" $line]} {
2412## puts "$line"
2413## }
2414## }
2415## }
2416## set end_time [clock seconds]
2417## log_time pr_verify $start_time $end_time 1 "[llength $configs] Configurations"
2418## }
2419## }
2420## proc add_xdc { xdc { synth 0} } {
2421## puts "\tAdding XDC files"
2422## #Flatten list if nested lists exist
2423## set files [join [join $xdc]]
2424## foreach file $files {
2425## if {[file exists $file]} {
2426## command "add_files $file"
2427## set file_split [split $file "/"]
2428## set fileName [lindex $file_split end]
2429## if { $synth ==2 || [string match "*synth*" $fileName] } {
2430## if {[string match "*ooc*" $fileName]} {
2431## command "set_property USED_IN {synthesis out_of_context} \[get_files $file\]"
2432## } else {
2433## command "set_property USED_IN {synthesis} \[get_files $file\]"
2434## }
2435## } elseif { $synth==1 } {
2436## if {[string match "*ooc*" $fileName]} {
2437## command "set_property USED_IN {synthesis implementation out_of_context} \[get_files $file\]"
2438## } else {
2439## command "set_property USED_IN {synthesis implementation} \[get_files $file\]"
2440## }
2441## } else {
2442## if {[string match "*ooc*" $fileName]} {
2443## command "set_property USED_IN {implementation out_of_context} \[get_files $file\]"
2444## } else {
2445## command "set_property USED_IN {implementation} \[get_files $file\]"
2446## }
2447## }
2448##
2449## if {[string match "*late*" $fileName]} {
2450## command "set_property PROCESSING_ORDER late \[get_files $file\]"
2451## } elseif {[string match "*early*" $fileName]} {
2452## command "set_property PROCESSING_ORDER early \[get_files $file\]"
2453## }
2454## } else {
2455## set errMsg "\nERROR: Could not find specified XDC: $file"
2456## error $errMsg
2457## }
2458## }
2459## }
2460## proc readXDC { xdc {cell ""} } {
2461## upvar resultDir resultDir
2462##
2463## puts "\tReading XDC files"
2464## #Flatten list if nested lists exist
2465## set files [join [join $xdc]]
2466## foreach file $files {
2467## if {[file exists $file]} {
2468## if {![llength $cell]} {
2469## command "read_xdc $file" "$resultDir/read_xdc.log"
2470## } else {
2471## command "read_xdc -cell $cell $file" "$resultDir/read_xdc_cell.log"
2472## }
2473## } else {
2474## set errMsg "\nERROR: Could not find specified XDC: $file"
2475## error $errMsg
2476## }
2477## }
2478## }
2479## proc add_ip_UNUSED { ips } {
2480## upvar resultDir resultDir
2481##
2482## foreach ip $ips {
2483## if {[string length ip] > 0} {
2484## if {[file exists $ip]} {
2485## set ip_split [split $ip "/"]
2486## set xci [lindex $ip_split end]
2487## set ipPathList [lrange $ip_split 0 end-1]
2488## set ipPath [join $ipPathList "/"]
2489## set ipName [lindex [split $xci "."] 0]
2490## set ipType [lindex [split $xci "."] end]
2491## puts "\t#HD: Adding \'$ipType\' file $xci"
2492## command "add_files $ipPath/$xci" "$resultDir/${ipName}_add.log"
2493## if {[string match $ipType "bd"]} {
2494## return
2495## }
2496## if {[get_property GENERATE_SYNTH_CHECKPOINT [get_files $ipPath/$xci]]} {
2497## if {![file exists $ipPath/${ipName}.dcp]} {
2498## puts "\tSynthesizing IP $ipName"
2499## command "synth_ip \[get_files $ipPath/$xci]" "$resultDir/${ipName}_synth.log"
2500## }
2501## } else {
2502## puts "\tGenerating output for IP $ipName"
2503## command "generate_target all \[get_ips $ipName]" "$resultDir/${ipName}_generate.log"
2504## }
2505## } else {
2506## set errMsg "\nERROR: Could not find specified IP file: $ip"
2507## error $errMsg
2508## }
2509## }
2510## }
2511## }
2512## proc add_cores { cores } {
2513## puts "\tAdding core files"
2514## #Flatten list if nested lists exist
2515## set files [join [join $cores]]
2516## foreach file $files {
2517## if {[string length $file] > 0} {
2518## if {![file exists $file]} {
2519## #Comment this out to prevent adding files 1 at a time. Add all at once instead.
2520## #command "add_files $file"
2521## set errMsg "\nERROR: Could not find specified IP netlist: $file"
2522## error $errMsg
2523## }
2524## }
2525## }
2526## #Check to make sure file list is not empty
2527## if {[string length $files] > 0} {
2528## command "add_files $files"
2529## }
2530## }
2531## proc check_drc { module {ruleDeck default} {quiet 0} } {
2532## upvar reportDir reportDir
2533##
2534## if {[info exists reportDir]==0} {
2535## set reportDir "."
2536## }
2537## puts "\t#HD: Running report_drc with ruledeck $ruleDeck.\n\tResults saved to $reportDir/${module}_drc_$ruleDeck.rpt"
2538## command "report_drc -ruledeck $ruleDeck -name $module -file $reportDir/${module}_drc_$ruleDeck.rpt" "$reportDir/temp.log"
2539## set Advisories [get_drc_violations -quiet -name $module -filter {SEVERITY=~"Advisory"}]
2540## set Warnings [get_drc_violations -quiet -name $module -filter {SEVERITY=~"Warning"}]
2541## set CritWarnings [get_drc_violations -quiet -name $module -filter {SEVERITY=~"Critical Warning"}]
2542## set Errors [get_drc_violations -quiet -name $module -filter {SEVERITY=~"Error"}]
2543## puts "\tAdvisories: [llength $Advisories]; Warnings: [llength $Warnings]; Critical Warnings: [llength $CritWarnings]; Errors: [llength $Errors];"
2544##
2545## if {[llength $Errors]} {
2546## if {!$quiet} {
2547## set errMsg "\nERROR: DRC found [llength $Errors] errors ($Errors)."
2548## } else {
2549## puts "\tCritical Warning: DRC found [llength $Errors] errors ($Errors)."
2550## }
2551## foreach error $Errors {
2552## puts "\n\t${error}: [get_property DESCRIPTION [get_drc_violations -name $module $error]]"
2553## }
2554## #Stop the script for Errors, unless user specifies quiet as true
2555## if {!$quiet} {
2556## error $errMsg
2557## }
2558## }
2559##
2560## if {[llength $CritWarnings]} {
2561## if {!$quiet} {
2562## set errMsg "\nERROR: DRC found [llength $CritWarnings] Critical Warnings ($CritWarnings)."
2563## } else {
2564## puts "\tCritical Warning: DRC found [llength $CritWarnings] Critical Warnings ($CritWarnings)."
2565## }
2566## foreach cw $CritWarnings {
2567## puts "\n\t${cw}: [get_property DESCRIPTION [get_drc_violations -name $module $cw]]"
2568## }
2569## #Stop the script for Critcal Warnings, unless user specifies quiet as true
2570## if {!$quiet} {
2571## error $errMsg
2572## }
2573## }
2574## }
2575## proc printRuleDecks { {decks ""} } {
2576## if {[llength $decks]} {
2577## set rules [get_drc_checks -of [get_drc_ruledecks $decks]]
2578## foreach rule $rules {
2579## set name [get_property NAME [get_drc_checks $rule]]
2580## set description [get_property DESCRIPTION [get_drc_checks $rule]]
2581## set severity [get_property SEVERITY [get_drc_checks $rule]]
2582## puts "\t${name}(${severity}): ${description}"
2583## }
2584## } else {
2585## puts "Rule Decks:\n\t[join [get_drc_ruledecks] "\n\t"]"
2586## }
2587## }
2588## proc printRules { rules } {
2589## foreach rule $rules {
2590## set name [get_property NAME [get_drc_checks $rule]]
2591## set description [get_property DESCRIPTION [get_drc_checks $rule]]
2592## set severity [get_property SEVERITY [get_drc_checks $rule]]
2593## puts "\t${name}(${severity}): $description"
2594## }
2595## }
2596## proc get_bad_pins { cell } {
2597## set noPP_pins [get_pins -of [get_cells $cell] -filter "HD.ASSIGNED_PPLOCS!~*INT* && HD.ASSIGNED_PPLOCS!~*INT*"]
2598## set io_pins [get_pins -of [get_nets -of [get_cells -hier -filter LIB_CELL=~*BUF*]] -filter PARENT_CELL==$cell]
2599## set count 0
2600## set clock_pins ""
2601## set bad_pins ""
2602## foreach pin $noPP_pins {
2603## set clock [get_clocks -quiet -of [get_pins $pin]]
2604## if { [lsearch -exact $io_pins $pin]!="-1" } {
2605## # puts "Found match: $pin"
2606## } else {
2607## if { $clock!=""} {
2608## # puts "Found clock: $pin"
2609## lappend clock_pins $pin
2610## } else {
2611## # puts "No match found: $pin"
2612## lappend bad_pins $pin
2613## }
2614## }
2615## }
2616## puts "[join $bad_pins "\n"]"
2617## puts "\nTotal Number of pins without PP: [llength $noPP_pins]"
2618## puts "Total Number of pins connected to buffers: [llength $io_pins]"
2619## puts "Total Number of clock pins: [llength $clock_pins]"
2620## puts "Total Number of \"bad\" pins: [llength $bad_pins]"
2621## }
2622## proc get_bad_ports { } {
2623## set noPP_ports [get_ports -filter "HD.PARTPIN_LOCS!~*INT* && HD.ASSIGNED_PPLOCS!~*INT*"]
2624## set io_ports [get_ports -of [get_nets -of [get_cells -hier -filter LIB_CELL=~*BUF*]]]
2625## set count 0
2626## set clock_ports ""
2627## set bad_ports ""
2628## foreach port $noPP_ports {
2629## set clock [get_clocks -quiet -of [get_ports $port]]
2630## if { [lsearch -exact $io_ports $port]!="-1" } {
2631## # puts "Found match: $port"
2632## } else {
2633## if { $clock!=""} {
2634## # puts "Found clock: $port"
2635## lappend clock_ports $port
2636## } else {
2637## # puts "No match found: $port"
2638## lappend bad_ports $port
2639## }
2640## }
2641## }
2642## puts "[join $bad_ports "\n"]"
2643## puts "\nTotal Number of ports without PP: [llength $noPP_ports]"
2644## puts "Total Number of ports connected to buffers: [llength $io_ports]"
2645## puts "Total Number of clock ports: [llength $clock_ports]"
2646## puts "Total Number of \"bad\" ports: [llength $bad_ports]"
2647## }
2648## proc insert_proxy_flop { cell } {
2649##
2650## if {[get_property IS_BLACKBOX [get_cells $cell]] == 0} {
2651## puts "ERROR: Specified cell $cell is not a blackbox.\nThe Tcl proc insert_proxy_flop can only be run on a cell that is a black box. Specify a black box cell, or run \'update_design -cell $cell -black_box\' prior to running this command."
2652## return 1
2653## }
2654##
2655## set all_in_pins [lsort [get_pins -of [get_cells $cell] -filter DIRECTION==IN]]
2656## set all_out_pins [lsort [get_pins -of [get_cells $cell] -filter DIRECTION==OUT]]
2657## #### Get a list of all clock pins (driver is a BUFG, BUFR, BUFH, etc)
2658## foreach inpin $all_in_pins {
2659## #Get the leaf level driver of the input pin
2660## set driver [get_cells -quiet -of [get_pins -quiet -leaf -of [get_nets -of [get_pins $inpin]] -filter DIRECTION==OUT]]
2661## #Check for direct connects to ports
2662## set port [get_ports -quiet -of [get_nets -of [get_pins $inpin]]]
2663## if {![llength $driver] || [llength $port] || [string match "GND" $driver] || [string match "VCC" $driver] } {
2664## puts "Info: No synchronous driver found for input pin $inpin. Skipping insertion."
2665## continue
2666## }
2667## if {[string match -nocase "BUF*" [get_property -quiet LIB_CELL [get_cells -quiet $driver]]]} {
2668## lappend clocks $inpin
2669## } else {
2670## lappend in_pins $inpin
2671## }
2672## }
2673## puts "Found [llength $clocks] clock pins."
2674## puts "Found [llength $in_pins] active input pins."
2675## foreach clock $clocks {
2676## puts "Creating clock net \"$clock\""
2677## create_net $clock
2678## connect_net -net $clock -objects "$clock"
2679## }
2680##
2681## ####Process input pins, minus those driven by BUFG
2682## puts "Inserting Proxy Flops for input pins"
2683## foreach inpin $in_pins {
2684## create_cell -reference FDCE ${inpin}_PROXY
2685## create_net $inpin
2686## connect_net -net $inpin -objects "$inpin ${inpin}_PROXY/D"
2687## set endpoints [get_cells -quiet -of [all_fanin -quiet -startpoints_only -flat [get_pins $inpin]]]
2688## set foundClock 0
2689## foreach endpoint $endpoints {
2690## #If the element is sequential
2691## if {[get_property -quiet IS_SEQUENTIAL [get_cells -quiet $endpoint]]} {
2692## #puts "Found sequential driver \"$endpoint\" for pin $inpin"
2693## set driver_clock [get_nets -quiet [get_nets -quiet -segments -of [get_pins -of [get_cells $endpoint] -filter IS_CLOCK]] -filter NAME=~$cell/*]
2694## if {[llength $driver_clock] > 0 && [lsearch $clocks [lindex $driver_clock 0]] >= 0} {
2695## #puts "\tFound clock connections: $driver_clock"
2696## connect_net -net [lindex $driver_clock 0] -objects "${inpin}_PROXY/C"
2697## set foundClock 1
2698## break
2699## }
2700## }
2701## }
2702## if {$foundClock == 0} {
2703## #Connect the inserted flop to the first clock in the list if the above fails
2704## puts "Info: No common clock connection found for input pin $inpin. Removing inserted flop."
2705## remove_net $inpin
2706## remove_cell ${inpin}_PROXY
2707## }
2708## }
2709##
2710## ####Process output pins
2711## puts "\nFound [llength $all_out_pins] output pins."
2712## puts "Inserting Proxy Flops for output pins"
2713## #Create a local GND cell to tie-off output flops.
2714## create_cell $cell/GND -reference GND
2715## create_net $cell/<const0>
2716## connect_net -net $cell/<const0> -objects $cell/GND/G
2717## foreach outpin $all_out_pins {
2718## create_cell -reference FDCE ${outpin}_PROXY
2719## create_net $outpin
2720## connect_net -net $outpin -objects "$outpin ${outpin}_PROXY/Q"
2721## #Tie off input to inserted output flop
2722## connect_net -net $cell/<const0> -objects "${outpin}_PROXY/D"
2723## set endpoints [get_cells -quiet -of [all_fanout -quiet -endpoints_only -flat [get_pins $outpin]]]
2724## #Check for direct connects to ports
2725## append endpoints [get_ports -quiet -of [get_nets -quiet -of [get_pins $outpin]]]
2726## if {![llength $endpoints]} {
2727## puts "Info: No loads found for output pin $outpin"
2728## }
2729## set foundClock 0
2730## foreach endpoint $endpoints {
2731## set load [get_property -quiet IS_SEQUENTIAL [get_cells -quiet $endpoint]]
2732## if {[llength $load]} {
2733## #puts "Found sequential load \"$endpoint\" for pin $outpin"
2734## set load_clock [get_nets -quiet [get_nets -quiet -segments -of [get_pins -of [get_cells $endpoint] -filter IS_CLOCK]] -filter NAME=~$cell/*]
2735## if {[llength $load_clock] > 0 && [lsearch $clocks [lindex $load_clock 0]] >= 0} {
2736## #puts "\tFound clock connections: $load_clock"
2737## connect_net -net [lindex $load_clock 0] -objects "${outpin}_PROXY/C"
2738## set foundClock 1
2739## break
2740## }
2741## }
2742## }
2743## if {$foundClock == 0} {
2744## #Connect the inserted flop to the first clock in the list if the above fails
2745## puts "Info: No common clock connection found for output pin $outpin. Removing inserted flop."
2746## remove_net $outpin
2747## remove_cell ${outpin}_PROXY
2748## }
2749## }
2750## set_property HD.PARTITION 1 [get_cells $cell]
2751## }
2752## proc verbose {} {
2753## set_param place.hardVerbose 469538
2754## set_param place.oldMsgVerbose 1
2755## set_param place.GPPlot 1
2756## set_param route.flowDbg 1
2757## set_param route.timingDbg 1
2758## set_param route.promoteErrors true
2759## }
2760## proc fix_timing {} {
2761## set clk_intr [split [report_clock_interaction -return_string] \n]
2762## foreach line $clk_intr {
2763## if { [regexp {^(\S+)\s+(\S+)\s+\S+.*Timed \(unsafe\).*} $line full src dst]} {
2764## set_false_path -from [get_clocks $src] -to [get_clocks $dst]
2765## }
2766## }
2767## }
2768# source $tclDir/hd_floorplan_utils.tcl
2769## proc create_ooc_clocks { cell hier_cell dir } {
2770## set_param tcl.statsThreshold -1
2771## set_msg_config -id "Vivado 12-1008" -suppress
2772## set_msg_config -id "Vivado 12-626" -suppress
2773##
2774## set xdcFile "$dir/${cell}_ooc_timing.xdc"
2775## if {[catch {file delete -force $xdcFile} errMSG] } {
2776## append errMsg "\nERROR: Could not delete \"$xdcFile\". Verify file is closed."
2777## error $errMsg
2778## }
2779## set fh [open "$xdcFile" w]
2780## puts "\tWriting XDC file \"$xdcFile\"."
2781## set in_pins [lsort [get_pins -of [get_cells $hier_cell] -filter DIRECTION==IN]]
2782## puts $fh "#---------------------------------------"
2783## puts $fh "# Create Clock Constraints - $hier_cell "
2784## puts $fh "#---------------------------------------"
2785## set portClocks ""
2786## foreach inpin $in_pins {
2787## set clocks [get_clocks -of [get_pins $inpin]]
2788## if {[llength $clocks] > 0} {
2789## foreach clock $clocks {
2790## set pin_split [split $inpin "/" ]
2791## set port [lindex $pin_split end]
2792## lappend portClocks $clock.$port
2793## set period [get_property PERIOD [get_clocks $clock]]
2794## set wave [get_property WAVEFORM [get_clocks $clock]]
2795## puts $fh "create_clock -period $period -name ${clock}.${port} \[get_ports \{$port\}] -waveform \{$wave\}"
2796## }
2797## if {[llength $clocks] ==2} {
2798## puts $fh "set_clock_groups -name $port -physically_exclusive -group \[get_clocks \{[lindex $portClocks end]\}] -group \[get_clocks \{[lindex $portClocks end-1]\}]"
2799## }
2800## set clk_src [get_cells -quiet -of [get_pins -quiet -leaf -of [get_nets [get_pins $inpin]] -filter DIRECTION==OUT]]
2801## if {[llength $clk_src] == 1} {
2802## set clk_src_val [get_property LOC [get_cells $clk_src]]
2803## if {[llength $clk_src_val] == 1 && [get_property IS_LOC_FIXED [get_cells $clk_src]]} {
2804## puts $fh "set_property HD.CLK_SRC $clk_src_val \[get_ports \{$port\}]"
2805## } else {
2806## puts $fh "#WARNING: Clock Source for pin \"$inpin\" ($clk_src) is not locked. Add a location constraint to the XDC prior to running this command."
2807## }
2808## }
2809## }
2810## }
2811## set_msg_config -id "Timing 38-127" -suppress
2812## set_msg_config -id "Timing 38-164" -suppress
2813## set_msg_config -id "Vivado 12-975" -suppress
2814## set numClocks [llength $portClocks]
2815## puts "\tNumber of Clocks Found: $numClocks"
2816## puts $fh "set_system_jitter 0.0"
2817## puts "\tGetting Clock Uncertainty for inter-clock paths"
2818## puts "\tCalculating Clock Latency for all Clocks"
2819## foreach portClock $portClocks {
2820## set clockSplit [split $portClock "." ]
2821## set clock [lindex $clockSplit 0]
2822## set clockPath [get_timing_paths -from [get_clocks $clock] -to [get_clocks $clock]]
2823## if {[llength $clockPath] > 0} {
2824## set uncertainty [get_property -quiet UNCERTAINTY $clockPath]
2825## set startPinDelay [get_property -quiet STARTPOINT_CLOCK_DELAY $clockPath]
2826## set startPin [get_property -quiet STARTPOINT_PIN $clockPath]
2827## set endPin [get_property -quiet ENDPOINT_PIN $clockPath]
2828## if {[string match [get_property CLASS $startPin] "pin"]} {
2829## set clkPin [get_pins -leaf -of [get_nets -of [get_pins $startPin]] -filter DIRECTION==OUT]
2830## } elseif {[string match [get_property CLASS $endPin] "pin"]} {
2831## set clkPin [get_pins -leaf -of [get_nets -of [get_pins $endPin]] -filter DIRECTION==OUT]
2832## set startPin $endPin
2833## } else {
2834## puts "info: No clock pins found in timing path"
2835## set clkPin ""
2836## }
2837## if {[llength $startPin] > 0 && [llength $clkPin] > 0} {
2838## set arcDelay_max [get_property DELAY_MAX_RISE [get_timing_arcs -from [get_pins $clkPin] -to [get_pins $startPin]]]
2839## set arcDelay_min [get_property DELAY_MIN_RISE [get_timing_arcs -from [get_pins $clkPin] -to [get_pins $startPin]]]
2840## #Subtract off minimum arcDelay from max Path delay to get maxInsertion... visa versa for minInsertion
2841## set maxInsertion [expr $startPinDelay - $arcDelay_min]
2842## set minInsertion [expr $startPinDelay - $arcDelay_max]
2843## puts $fh "set_clock_latency -source -max $maxInsertion \[get_clocks \{$portClock\}]"
2844## puts $fh "set_clock_latency -source -min $minInsertion \[get_clocks \{$portClock\}]"
2845## puts $fh "set_clock_uncertainty $uncertainty \[get_clocks \{$portClock\}]"
2846## }
2847## }
2848## }
2849##
2850## #Generate Clock Uncertainty and asynchronous clock constraints
2851## #Loop through clocks efficiently to avoid duplicate constraints being generated
2852## puts "\tGetting Clock Uncertainty for intra-clock paths"
2853## for {set i 0} {$i < [expr $numClocks-1]} {incr i} {
2854## set portClock1 [lindex $portClocks $i]
2855## set clockSplit [split $portClock1 "." ]
2856## set clock1 [lindex $clockSplit 0]
2857## for {set j [expr $i+1]} {$j < $numClocks} {incr j} {
2858## set portClock2 [lindex $portClocks $j]
2859## set clock_split [split $portClock2 "." ]
2860## set clock2 [lindex $clock_split 0]
2861## set clkPath1 [get_timing_paths -from [get_clocks $clock1] -to [get_clocks $clock2]]
2862## set clkPath2 [get_timing_paths -from [get_clocks $clock2] -to [get_clocks $clock1]]
2863## if {[llength $clkPath1] > 0 || [llength $clkPath2] > 0 } {
2864## if {[get_property -quiet SLACK $clkPath1] == "" && [get_property -quiet SLACK $clkPath2] == ""} {
2865## puts $fh "set_clock_groups -asynchronous -group \[get_clocks \{$portClock1\}] -group \[get_clocks \{$portClock2\}]"
2866## }
2867## if {[get_property -quiet SLACK $clkPath1] != ""} {
2868## puts $fh "set_clock_uncertainty -from \[get_clocks \{$portClock1\}] -to \[get_clocks \{$portClock2\}] [get_property -quiet UNCERTAINTY $clkPath1]"
2869## }
2870## if {[get_property -quiet SLACK $clkPath2] != ""} {
2871## puts $fh "set_clock_uncertainty -from \[get_clocks \{$portClock2\}] -to \[get_clocks \{$portClock1\}] [get_property -quiet UNCERTAINTY $clkPath2]"
2872## }
2873## }
2874## }
2875## }
2876##
2877## puts "\t#HD: create_ooc_clocks completed successfully\n"
2878## reset_msg_config -quiet -id "Timing 38-127" -suppress
2879## reset_msg_config -quiet -id "Timing 38-164" -suppress
2880## reset_msg_config -quiet -id "Vivado 12-975" -suppress
2881## reset_msg_config -quiet -id "Vivado 12-1008" -suppress
2882## reset_msg_config -quiet -id "Vivado 12-626" -suppress
2883## reset_param tcl.statsThreshold
2884## close $fh
2885## }
2886## proc average_clock_delay {} {
2887## #Generate Clock Latency Constraints based on average
2888## puts "\tCalculating Average Clock Latency for all Clocks"
2889## set maxPaths 10000
2890## foreach portClock1 $portClocks {
2891## set totalClock1Delay_max 0
2892## set totalClock1Delay_min 0
2893## set clockSplit [split $portClock1 "." ]
2894## set clock1 [lindex $clockSplit 0]
2895## set setupPathCount 0
2896## set holdPathCount 0
2897## foreach portClock2 $portClocks {
2898## set clock_split [split $portClock2 "." ]
2899## set clock2 [lindex $clock_split 0]
2900## set clockPaths_setup [get_timing_paths -from [get_clocks $clock1] -to [get_clocks $clock2] -max_paths $maxPaths]
2901## set clockPaths_hold [get_timing_paths -from [get_clocks $clock1] -to [get_clocks $clock2] -max_paths $maxPaths -hold]
2902## if {[llength $clockPaths_setup] > 0} {
2903## foreach setup $clockPaths_setup {
2904## incr setupPathCount
2905## set startDelay_max [get_property -quiet STARTPOINT_CLOCK_DELAY $setup]
2906## set totalClock1Delay_max [expr ($totalClock1Delay_max + $startDelay_max)]
2907## }
2908## }
2909## if {[llength $clockPaths_hold] > 0} {
2910## foreach hold $clockPaths_hold {
2911## incr holdPathCount
2912## set startDelay_min [get_property -quiet STARTPOINT_CLOCK_DELAY $hold]
2913## set totalClock1Delay_min [expr ($totalClock1Delay_min + $startDelay_min)]
2914## }
2915## }
2916## }
2917## if {[llength $clockPaths_setup] > 0} {
2918## set averageClock1Delay_max [expr {double(round(100*$totalClock1Delay_max / $setupPathCount))/100}]
2919## puts "\tClock: $portClock1, \n\t\tTotal Setup Clock Delay: $totalClock1Delay_max, \n\t\tTotal Number of Paths: $setupPathCount, \n\t\tAverage Clock Delay: $averageClock1Delay_max"
2920## puts $fh "set_clock_latency -source -max $averageClock1Delay_max \[get_clocks \{$portClock1\}]"
2921## }
2922## if {[llength $clockPaths_hold] > 0} {
2923## set averageClock1Delay_min [expr {double(round(100*$totalClock1Delay_min / $holdPathCount))/100}]
2924## puts "\tClock: $portClock1, \n\t\tTotal Hold Clock Delay: $totalClock1Delay_min, \n\t\tTotal Number of Paths: $holdPathCount, \n\t\tAverage Clock Delay: $averageClock1Delay_min"
2925## puts $fh "set_clock_latency -source -min $averageClock1Delay_min \[get_clocks \{$portClock1\}]"
2926## }
2927## }
2928## }
2929## proc create_set_logic { name hier_cell dir {cell 1}} {
2930## set_msg_config -id "Vivado 12-1023" -suppress
2931## set_msg_config -id "Vivado 12-584" -suppress
2932##
2933## if {$cell} {
2934## set xdcFile "$dir/${name}_ooc_optimize.xdc"
2935## } else {
2936## set xdcFile "$dir/${name}_optimize.xdc"
2937## }
2938##
2939## if {[catch {file delete -force $xdcFile} errMsg] } {
2940## append errMsg "\nERROR: Could not delete \"$xdcFile\". Verify file is closed."
2941## error $errMsg
2942## }
2943## set fh [open "$xdcFile" w]
2944## puts "\tWriting XDC file \"$xdcFile\"."
2945## set in_pins [lsort [get_pins -of [get_cells $hier_cell] -filter DIRECTION==IN]]
2946## set out_pins [lsort [get_pins -of [get_cells $hier_cell] -filter DIRECTION==OUT]]
2947## #set inout_pins [lsort [get_pins -of [get_cells $hier_cell] -filter DIRECTION==INOUT]]
2948## foreach inpin $in_pins {
2949## set pin_split [concat {*}[split $inpin "/"]]
2950## set port [lindex $pin_split end]
2951## set net [get_nets -of [get_pins $inpin]]
2952## if {[llength $net]==0} {
2953## #for input pins with no driver. Should be tied to Vcc or Gnd in netlist design.
2954## puts "\tWARNING: Found unconnected input pin \"$inpin\". If this script is being run on an optimzed (implemented) version of the design, pleaes close the current design and rerun on the synthesized netlist design (pre-implementation)."
2955## } else {
2956## set type [get_property TYPE [get_nets $net]]
2957## if {[string match -nocase $type "POWER"]} {
2958## #for inputs tied to Vcc
2959## if {$cell} {
2960## puts $fh "set_logic_one \[get_ports \{$port\}]"
2961## } else {
2962## puts $fh "set_logic_one \[get_pins \{$inpin\}]"
2963## }
2964## } elseif {[string match -nocase $type "GROUND"]} {
2965## #for input tied to Ground
2966## if {$cell} {
2967## puts $fh "set_logic_zero \[get_ports \{$port\}]"
2968## } else {
2969## puts $fh "set_logic_zero \[get_pins \{$inpin\}]"
2970## }
2971## }
2972## }
2973## }
2974##
2975## foreach outpin $out_pins {
2976## set pin_split [concat {*}[split $outpin "/"]]
2977## set port [lindex $pin_split end]
2978## set net [get_nets -of [get_pins $outpin]]
2979## if {[llength $net]==0} {
2980## #for output with no nets
2981## if {$cell} {
2982## puts $fh "set_logic_unconnected \[get_ports \{$port\}]"
2983## } else {
2984## puts $fh "set_logic_unconnected \[get_pins \{$outpin\}]"
2985## }
2986## } else {
2987## set pin_count [get_property FLAT_PIN_COUNT [get_nets $net]]
2988## set io_port [get_ports -of [get_nets $net]]
2989## set type [get_property TYPE [get_nets $net]]
2990## if {[llength $io_port] == 0 && $pin_count <= 1} {
2991## #for output with dangling nets
2992## if {$cell} {
2993## puts $fh "set_logic_unconnected \[get_ports \{$port\}]"
2994## } else {
2995## puts $fh "set_logic_unconnected \[get_pins \{$outpin\}]"
2996## }
2997## } elseif {[string match -nocase $type "POWER"]} {
2998## #for outputs tied to Vcc
2999## if {$cell} {
3000## # puts $fh "set_logic_one \[get_ports $port]"
3001## } else {
3002## # puts $fh "set_logic_one \[get_pins $outpin]"
3003## }
3004## } elseif {[string match -nocase $type "GROUND"]} {
3005## #for output tied to Ground
3006## if {$cell} {
3007## # puts $fh "set_logic_zero \[get_ports $port]"
3008## } else {
3009## # puts $fh "set_logic_zero \[get_pins $outpin]"
3010## }
3011## }
3012## }
3013## }
3014## reset_msg_config -quiet -id "Vivado 12-584" -suppress
3015## reset_msg_config -quiet -id "Vivado 12-1023" -suppress
3016## close $fh
3017## }
3018## proc write_hd_xdc {inst hierInst dir} {
3019## reset_property HD.PARTPIN_RANGE [get_pins $hierInst/* -filter "HD.ASSIGNED_PPLOCS=~*INT*"]
3020## set_property HD.LOC_FIXED 1 [get_pins $hierInst/*]
3021## set file "${dir}/${inst}_phys.xdc"
3022## if {[file exists $file]} {
3023## file delete -force $file
3024## }
3025## puts "\tWriting XDC file \"$file\"."
3026## write_xdc -force -cell $hierInst $file
3027##
3028## set file "${dir}/${inst}_ooc_budget.xdc"
3029## if {[file exists $file]} {
3030## file delete -force $file
3031## }
3032## puts "\tWriting XDC file \"$file\"."
3033## ::debug::gen_hd_timing_constraints -percent 50 -of [get_cells $hierInst] -file $file
3034## }
3035## proc highlight_partpins { cell index } {
3036## highlight_objects -color_index $index [get_pins $cell/*]
3037## }
3038## proc hd_floorplan {cells} {
3039## set relativeDir "Sources/xdc"
3040## set projectDir "[get_property DIRECTORY [current_project]]"
3041## set outputDir "${projectDir}/../../${relativeDir}"
3042##
3043## #If no design is open
3044## #if { [catch {current_instance}] || [string match "netlist_1" [get_property NAME [current_design]]]==0 } {}
3045## # if { [catch {current_instance}] } {
3046## # puts "ERROR: No open design... Opened the Synthesized Design prior to running this command."
3047## # return
3048## # }
3049##
3050## #Make sure cells are passed into proc
3051## if {![llength $cells]} {
3052## puts "ERROR: No cells specified for command hd_floorplan."
3053## return
3054## }
3055##
3056## puts "Processing cells: $cells"
3057## set cell_list ""
3058## set cell_count 0
3059## foreach cell $cells {
3060## set cell_split [concat {*}[split $cell "/"]]
3061## set cell_name [lindex $cell_split end]
3062## incr cell_count
3063## #If local cell name is the same for multiple instances, append a unique value
3064## #This is to prevent output files from having the same name and overwriting
3065## if {[lsearch -exact $cell_list $cell_name] >= 0} {
3066## lappend cell_list $cell_name
3067## set cell_name ${cell_name}_${cell_count}
3068## } else {
3069## lappend cell_list $cell_name
3070## }
3071## set_property HD.PARTITION 1 [get_cells $cell]
3072## create_set_logic $cell_name $cell $outputDir
3073## create_ooc_clocks $cell_name $cell $outputDir
3074## }
3075##
3076## opt_design
3077## place_design
3078##
3079## set color 1
3080## set cell_list ""
3081## set cell_count 0
3082## foreach cell $cells {
3083## set cell_split [concat {*}[split $cell "/"]]
3084## set cell_name [lindex $cell_split end]
3085## incr cell_count
3086## #If local cell name is the same for multiple instances, append a unique value
3087## #This is to prevent output files from having the same name and overwriting
3088## if {[lsearch -exact $cell_list $cell_name] >= 0} {
3089## lappend cell_list $cell_name
3090## set cell_name ${cell_name}_${cell_count}
3091## } else {
3092## lappend cell_list $cell_name
3093## }
3094## write_hd_xdc $cell_name $cell $outputDir
3095## highlight_partpins $cell $color
3096## incr color
3097## }
3098## write_checkpoint -force $projectDir/TopDown_place_design.dcp
3099## }
3100# source $tclDir/pr_utils.tcl
3101## proc expand_pr { {ratio 2} {units 3} {pplocs 3} } {
3102## set_param hd.useExpandedContainmentArea 1
3103## set_param hd.expansionRatio $ratio ;#(EXPANDED RANGE $ratio times larger)
3104## set_param hd.numberOfProgrammingUnitsForHorizontalExpansion $units
3105## set_param hd.maxPPLOCSPerIntTile_modified $pplocs ;#(MAXIMUM PPLOC PER INT is 6)
3106## set_param hd.enablePPLOCGradientCapacity false ;#(NO SPREADING)
3107## }
3108## proc pr_unlock {} {
3109## lock_design -unlock -level routing
3110## set_property IS_LOC_FIXED 0 [get_cells -hier -filter {(PRIMITIVE_LEVEL!=INTERNAL && PRIMITIVE_LEVEL!=MACRO && PRIMITIVE_LEVEL!="") && (REF_NAME=~FD* || REF_NAME=~LUT* || REF_NAME=~SRL* || REF_NAME=~CARRY* || REF_NAME=~MUX*)}]
3111## set_property IS_BEL_FIXED 0 [get_cells -hier -filter {(PRIMITIVE_LEVEL!=INTERNAL && PRIMITIVE_LEVEL!=MACRO && PRIMITIVE_LEVEL!="") && (REF_NAME=~FD* || REF_NAME=~LUT* || REF_NAME=~SRL* || REF_NAME=~CARRY* || REF_NAME=~MUX*)}]
3112## set_property IS_LOC_FIXED 0 [get_cells -hier -filter {(PRIMITIVE_LEVEL==MACRO) && (REF_NAME=~RAM* || REF_NAME=~LUT*)}]
3113## set_property IS_BEL_FIXED 0 [get_cells -hier -filter {(PRIMITIVE_LEVEL==MACRO) && (REF_NAME=~RAM* || REF_NAME=~LUT*)}]
3114## }
3115## proc pr_unplace {} {
3116## route_design -unroute
3117## place_design -unplace
3118## set cells [get_cells -quiet -hier -filter HD.RECONFIGURABLE]
3119## foreach cell $cells {
3120## reset_property HD.PARTPIN_LOCS [get_pins $cell/*]
3121## reset_property HD.PARTPIN_RANGE [get_pins $cell/*]
3122## }
3123## }
3124## proc reset_partpins {} {
3125## set cells [get_cells -quiet -hier -filter HD.RECONFIGURABLE]
3126## foreach cell $cells {
3127## reset_property HD.PARTPIN_LOCS [get_pins $cell/*]
3128## reset_property HD.PARTPIN_RANGE [get_pins $cell/*]
3129## }
3130## }
3131## proc toggle_pr { cells } {
3132## if {[catch current_instance]} {
3133## puts "INFO: No open design."
3134## return
3135## }
3136## foreach cell $cells {
3137## if {[get_property HD.RECONFIGURABLE [get_cells $cell]] != "1"} {
3138## set_property HD.RECONFIGURABLE 1 [get_cells $cell]
3139## } else {
3140## set_property HD.RECONFIGURABLE 0 [get_cells $cell]
3141## }
3142## }
3143## }
3144## proc get_rps {} {
3145## if {[catch current_instance]} {
3146## puts "INFO: No open design."
3147## return
3148## }
3149## set rps [get_cells -quiet -hier -filter HD.RECONFIGURABLE]
3150## if {![llength $rps]} {
3151## puts "Info: No cells found with HD.RECONFIGURABLE==1"
3152## return
3153## }
3154## return $rps
3155## }
3156## proc get_bb {} {
3157## if {[catch current_instance]} {
3158## puts "INFO: No open design."
3159## return
3160## }
3161## set bb [get_cells -quiet -hier -filter IS_BLACKBOX]
3162## if {![llength $bb]} {
3163## puts "Info: No blackbox cells found"
3164## return
3165## }
3166## return $bb
3167## }
3168## proc get_static_sites {} {
3169## set sliceTotal [llength [get_sites SLICE*]]
3170## set sliceExclude [llength [get_sites SLICE* -of [get_pblocks -filter EXCLUDE_PLACEMENT]]]
3171##
3172## puts "Total Slices: $sliceTotal"
3173## puts "Slices Excluded: $sliceExclude"
3174## puts "-----------------------------"
3175## puts "Static Slices: [expr $sliceTotal - $sliceExclude]"
3176## }
3177## proc bb { cells } {
3178## if {[catch current_instance]} {
3179## puts "INFO: No open design."
3180## return
3181## }
3182## foreach cell $cells {
3183## update_design -black_box -cell $cell
3184## }
3185## }
3186## proc gb { cells } {
3187## if {[catch current_instance]} {
3188## puts "INFO: No open design."
3189## return
3190## }
3191## foreach cell $cells {
3192## update_design -buffer_ports -cell $cell
3193## }
3194## }
3195## proc delete_PartPins { RPs } {
3196## foreach rp $RPs {
3197## reset_property HD.PARTPIN_RANGE [get_pins $rp/*]
3198## reset_property HD.PARTPIN_LOCS [get_pins $rp/*]
3199## }
3200## }
3201## proc get_pp_range { cell } {
3202## set pp_range_sites ""
3203## set pp_ranges ""
3204## set pins [get_pins -filter HD.PARTPIN_RANGE!="" -of [get_cells $cell]]
3205## foreach pin $pins {
3206## set ranges [get_property HD.PARTPIN_RANGE [get_pins $pin]]
3207## if {[llength $ranges]} {
3208## foreach range $ranges {
3209## if {[lsearch -exact $pp_ranges $range]==-1} {
3210## puts "Found unique range $range"
3211## lappend pp_ranges $range
3212## lappend pp_range_sites [get_sites -range $range]
3213## }
3214## }
3215## }
3216## }
3217## set sites [concat {*}$pp_range_sites]
3218## highlight_objects -color yellow [get_sites [lsort $sites]]
3219## }
3220## proc get_rp_clocks { cell {file ""}} {
3221## set table " -row {\"Clock Pin\" \"Clock Net\" \"Clock Driver\" \"Driver Type\" \"RM Loads\" \"Static Loads\"}"
3222## set count 0
3223## set clockNets ""
3224## set staticLods ""
3225## set pins [get_pins $cell/* -filter DIRECTION==IN]
3226## foreach pin $pins {
3227## set clock_driver [get_cells -quiet -of [get_pins -quiet -leaf -of [get_nets -quiet -of $pin] -filter DIRECTION==OUT] -filter REF_NAME=~BUF*]
3228## if {[llength $clock_driver]} {
3229## incr count
3230## set clock_net [get_nets -of [get_pins $pin]]
3231## set driver_type [get_property REF_NAME [get_cells $clock_driver]]
3232## set rm_loads [llength [get_pins -quiet -leaf -of $clock_net -filter NAME=~$cell/*]]
3233## set static_pins [get_pins -quiet -leaf -of $clock_net -filter "NAME!~$cell/* && DIRECTION==IN"]
3234## set static_loads [llength $static_pins]
3235## append table " -row {$pin $clock_net $clock_driver $driver_type $rm_loads $static_loads}"
3236## lappend clockNets $clock_net
3237## lappend staticLoads [get_cells -quiet -of $static_pins -filter "REF_NAME!~BUF* && REF_NAME!~MMCM* && REF_NAME!~PLL*"]
3238## }
3239## }
3240## set title "-title {#HD: Clock information for RP $cell ($count clocks total)}"
3241## set table ${title}${table}
3242## if {[llength $file]} {
3243## print_table $table -file $file
3244## } else {
3245## print_table $table
3246## }
3247## return $clockNets
3248## # return $staticLoads
3249## }
3250## proc get_limit_clocks {{limit 4}} {
3251## set clocks [get_clocks -quiet]
3252## puts "Found [llength $clocks] clocks in the design"
3253## set clockCount 0
3254## set title "-title {Total Clocks:[llength $clocks] in design. Reporting on clocks with $limit or less connections}"
3255## set table " -row {\"\" \"Clock\" \"Total Loads\" \"Load Types\" \"Driver Type\"}"
3256## foreach clock $clocks {
3257## set loads [get_pins -quiet -leaf -filter DIRECTION==IN -of [get_nets -of $clock]]
3258## set driver [get_pins -quiet -leaf -filter DIRECTION==OUT -of [get_nets -of $clock]]
3259## if {[llength $loads]<=$limit} {
3260## incr clockCount
3261## if {[llength $driver]} {
3262## append table " -row {$clockCount $clock [llength $loads] [list [get_property REF_NAME $loads]] [get_property REF_NAME $driver]}"
3263## } elseif {[llength [get_ports -quiet -of [get_nets -of $clock]]]} {
3264## set driver [get_ports -of [get_nets -of $clock]]
3265## append table " -row {$clockCount $clock [llength $loads] [list [get_property REF_NAME $loads]] Port\($driver\)}"
3266## } else {
3267## append table " -row {$clockCount $clock [llength $loads] [list [get_property REF_NAME $loads]] Unknown}"
3268## }
3269## }
3270## }
3271## print_table $table
3272## }
3273## proc mark_congestion { ranges } {
3274## set colors {red green blue magenta yellow cyan orange}
3275## set color 0
3276## foreach range $ranges {
3277## set intTile1 [lindex $range 0]
3278## set intTile2 [lindex $range end]
3279##
3280## set corner1 [lindex [split $intTile1 _] end]
3281## set corner2 [lindex [split $intTile2 _] end]
3282##
3283## set sites1 [get_sites -of [get_tiles *_$corner1]]
3284## set sites2 [get_sites -of [get_tiles *_$corner2]]
3285## puts "$corner1: $sites1"
3286## puts "$corner2: $sites2"
3287##
3288## mark_objects -color [lindex $colors $color] [get_sites -range [lindex $sites1 0]:[lindex $sites2 end]]
3289## if {$color==6} {
3290## set color 0
3291## } else {
3292## incr color
3293## }
3294## }
3295## }
3296## proc get_overlapping_nodes {{limit 0}} {
3297## set nets [get_nets -hier -filter ROUTE_STATUS==CONFLICTS]
3298## puts "Found [llength $nets] nets with Conflicts."
3299## set nodes [get_nodes -of $nets]
3300## puts "Parsing [llength $nodes] nodes for potential overlaps."
3301## set nodeOverlaps {}
3302## set count 0
3303## set lineCount 0
3304##
3305## puts -nonewline "0 "
3306## foreach node $nodes {
3307## #If a limit is specified, stop after #limit overlapping nodes are found
3308## if {$limit > 0} {
3309## if {[llength $nodeOverlaps] == $limit} {
3310## break
3311## }
3312## }
3313## set nodeNets [get_nets -quiet -of $node]
3314## if {[llength $nodeNets] > 1} {
3315## lappend nodeOverlaps $node
3316## }
3317## incr count
3318## #Add a "." for every 100 nodes checked
3319## if {[expr fmod($count,100)]==0.0} {
3320## puts -nonewline "."
3321## }
3322##
3323## #Add a new line of "."s for every 1000 nodes
3324## if {$count == 1000} {
3325## set count 0
3326## incr lineCount
3327## puts ""
3328## puts -nonewline "${lineCount}k"
3329## }
3330## }
3331## puts "\nFound [llength $nodeOverlaps] overlapping nodes."
3332## if {[llength $nodeOverlaps]} {
3333## select_objects $nodeOverlaps
3334## highlight_objects -color red [get_selected_objects]
3335## }
3336## }
3337## proc export_partpins { args } {
3338## set FH "stdout"
3339## set pins [get_pins -hier * -filter HD.ASSIGNED_PPLOCS!=""]
3340##
3341## #Override defaults with command options
3342## set argLength [llength $args]
3343## set index 0
3344## while {$index < $argLength} {
3345## set arg [lindex $args $index]
3346## set value [lindex $args [expr $index+1]]
3347## switch -exact -- $arg {
3348## {-cells} {set cells [get_cells $value]}
3349## {-file} {set FH [open $value w]}
3350## {-help} {set helpMsg "Description:"
3351## lappend helpMsg "Exports Partition Pins from in memory design to STDOUT or specified file.\n"
3352## lappend helpMsg "Syntax:"
3353## lappend helpMsg "export_partpins\t\[-cells <arg>] \[-file <arg>]\n"
3354## lappend helpMsg "Usage:"
3355## lappend helpMsg " Name Description"
3356## lappend helpMsg " ---------------------------------------"
3357## lappend helpMsg " \[-cells] Optional. Specifies the list of Cells to export."
3358## lappend helpMsg " If no Cells are specified, all PartPins will be exported."
3359## lappend helpMsg " \[-file] Optional. Specifies the output file name."
3360## lappend helpMsg " If not specified the output will be written to STDOUT"
3361## lappend helpMsg " \[-help] Displays this message\n\n"
3362## foreach line $helpMsg {
3363## puts $line
3364## }
3365## return
3366## }
3367## default {set errMsg "ERROR: Specified argument $arg is not supported.\n"
3368## append errMsg "Supported arguments are -help, -pblocks, and -file.\n"
3369## append errMsg "Use the -help option for more details"
3370## error $errMsg
3371## }
3372## }
3373## set index [expr $index + 2]
3374## }
3375##
3376## if {![info exists cells]} {
3377## set errMsg "Error: No -cells option specificed. A cell must be specified with this option."
3378## error $errMsg
3379## }
3380##
3381## #if -cell is used, clear out pin list and create a list based of of specified cells
3382## if {[llength $cells]} {
3383## foreach cell $cells {
3384## foreach pin [lsort -dict [get_pins -of [get_cells $cell] -filter HD.ASSIGNED_PPLOCS!=""]] {
3385## puts $FH "set_property HD.PARTPIN_LOCS [lindex [get_property HD.ASSIGNED_PPLOCS $pin] 0] \[get_pins \{$pin\}\]"
3386## flush $FH
3387## }
3388## }
3389## }
3390## close $FH
3391## }
3392## proc convert_pblocks {} {
3393##
3394## set filter "SNAPPING_MODE!=\"\" && SNAPPING_MODE!=OFF"
3395## set pblocks [get_pblocks -filter $filter]
3396## foreach pblock $pblocks {
3397## resize_pblock $pblock -add [get_property DERIVED_RANGES $pblock] -replace
3398## }
3399## }
3400## proc export_pblocks { args } {
3401##
3402## set FH "stdout"
3403## set pblocks [get_pblocks]
3404##
3405## #Override defaults with command options
3406## set argLength [llength $args]
3407## set index 0
3408## while {$index < $argLength} {
3409## set arg [lindex $args $index]
3410## set value [lindex $args [expr $index+1]]
3411## switch -exact -- $arg {
3412## {-pblocks} {set pblocks [get_pblocks $value]}
3413## {-file} {set FH [open $value w]}
3414## {-help} {set helpMsg "Description:"
3415## lappend helpMsg "Exports Pblocks from in memory design to STDOUT or specified file.\n"
3416## lappend helpMsg "Syntax:"
3417## lappend helpMsg "export_pblocks\t\[-pblocks <arg>] \[-file <arg>]\n"
3418## lappend helpMsg "Usage:"
3419## lappend helpMsg " Name Description"
3420## lappend helpMsg " ---------------------------------------"
3421## lappend helpMsg " \[-pblocks] Optional. Specifies the list of Pblocks to export."
3422## lappend helpMsg " If no Pblocks are specified, all Pblocks will be exported."
3423## lappend helpMsg " \[-file] Optional. Specifies the output file name."
3424## lappend helpMsg " If not specified the output will be written to STDOUT"
3425## lappend helpMsg " \[-help] Displays this message\n\n"
3426## foreach line $helpMsg {
3427## puts $line
3428## }
3429## return
3430## }
3431## default {set errMsg "ERROR: Specified argument $arg is not supported.\n"
3432## append errMsg "Supported arguments are -help, -pblocks, and -file.\n"
3433## append errMsg "Use the -help option for more details"
3434## error $errMsg
3435## }
3436## }
3437## set index [expr $index + 2]
3438## }
3439##
3440## foreach pblock $pblocks {
3441## puts $FH "\n\n####Pblock $pblock####"
3442## puts $FH "create_pblock $pblock"
3443## set cells [get_cells -quiet -of [get_pblocks $pblock]]
3444## if {[llength $cells]} {
3445## puts $FH "add_cells_to_pblock \[get_pblocks $pblock\] \[get_cells \[list $cells\]\]"
3446## }
3447## set grids [get_property GRIDTYPES [get_pblock $pblock]]
3448## set ranges [get_property GRID_RANGES [get_pblocks $pblock]]
3449## set matchedRanges ""
3450## foreach grid $grids {
3451## set grid_ranges ""
3452## foreach range $ranges {
3453## regexp {(\w+)_(X\d+Y\d+)} $range temp type value
3454## if {[string match $grid $type]} {
3455## lappend grid_ranges $range
3456## }
3457## }
3458## if {[llength $grid_ranges]} {
3459## puts $FH "resize_pblock \[get_pblocks $pblock\] -add \{$grid_ranges\}"
3460## lappend matchedRanges $grid_ranges
3461## } else {
3462## puts "Critical Warning: Found GRIDTYPE $grid, but no ranges of the matching type in Pblock range for Pblock $pblock:\n$ranges"
3463## }
3464## }
3465##
3466## #Detect Ranges in Pblock with no matching GRIDTYPES (like BUFG or IO in non-PR Pblock)
3467## foreach range $ranges {
3468## if {[lsearch [join $matchedRanges] $range]==-1} {
3469## puts $FH "resize_pblock \[get_pblocks $pblock\] -add \{$range\}"
3470## }
3471## }
3472##
3473## ##Check for addtitional Pblock properties
3474## if {[get_property PARTPIN_SPREADING [get_pblocks $pblock]] != 5} {
3475## puts $FH "set_property PARTPIN_SPREADING [get_property PARTPIN_SPREADING [get_pblocks $pblock]] \[get_pblocks $pblock\]"
3476## }
3477## if {[llength [get_property SNAPPING_MODE [get_pblocks $pblock]]]} {
3478## puts $FH "set_property SNAPPING_MODE [get_property SNAPPING_MODE [get_pblocks $pblock]] \[get_pblocks $pblock\]"
3479## }
3480## if {[get_property CONTAIN_ROUTING [get_pblocks $pblock]]} {
3481## puts $FH "set_property CONTAIN_ROUTING 1 \[get_pblocks $pblock\]"
3482## }
3483## if {[get_property EXCLUDE_PLACEMENT [get_pblocks $pblock]]} {
3484## puts $FH "set_property EXCLUDE_PLACEMENT 1 \[get_pblocks $pblock\]"
3485## }
3486## if {[get_property RESET_AFTER_RECONFIG [get_pblocks $pblock]]} {
3487## puts $FH "set_property RESET_AFTER_RECONFIG 1 \[get_pblocks $pblock\]"
3488## }
3489## if {![string match "ROOT" [get_property PARENT [get_pblocks $pblock]]]} {
3490## puts $FH "set_property PARENT [get_property PARENT [get_pblocks $pblock]] \[get_pblocks $pblock\]"
3491## }
3492## flush $FH
3493## }
3494## if {![string match $FH "stdout"]} {
3495## close $FH
3496## }
3497## }
3498## proc highlight_internal_nets { cell {color red} } {
3499##
3500## if {[get_property IS_BLACKBOX [get_cells $cell]]} {
3501## puts "Info: Cell $cell is a blackbox, and will not be processed."
3502## return
3503## }
3504## #Get a list of all nets that match the cell name, but filter out clocks and Global_Logic
3505## set nets [get_nets -hier -filter "NAME=~$cell/* && TYPE!=GLOBAL_CLOCK && TYPE!=GND && TYPE!=VCC && TYPE!= POWER && TYPE!=GROUND"]
3506## puts "All nets from $cell: [llength $nets]"
3507## set internal_nets ""
3508## foreach net $nets {
3509## #get a list of all leaf level pins that the net connects to
3510## set pins [get_pins -quiet -leaf -of [get_nets $net]]
3511## set external 0
3512## #Look at each pin to see if connects to a pin outside of the specified cell
3513## #If it does, ignore this net and move on (break)
3514## foreach pin $pins {
3515## if {![string match "$cell/*" $pin]} {
3516## set external 1
3517## break
3518## }
3519## }
3520## if {!$external} {
3521## lappend internal_nets $net
3522## }
3523## }
3524## llength $internal_nets
3525## puts "Internal nets of $cell: [llength $internal_nets]"
3526## highlight_objects -color $color [get_nets $internal_nets]
3527## }
3528## proc get_common_nets { cells } {
3529## array set netPins {}
3530## foreach cell $cells {
3531## set pins [lsort -dict [get_pins -of [get_cells $cell]]]
3532## foreach pin $pins {
3533## set net [get_nets -quiet -top -of $pin]
3534## if {[llength $net]} {
3535## lappend netPins($net) "${pin}([get_property DIRECTION $pin])"
3536## }
3537## }
3538## }
3539## #return [array get netPins]
3540## set count 0
3541## foreach net [lsort -dict [array names netPins]] {
3542## set pins $netPins($net)
3543## if {[llength $pins] > 1 && ![string match "<const*>" $net]} {
3544## incr count
3545## puts "${net}([llength $pins]): [lsort -dict $pins]"
3546## }
3547## }
3548## puts "Found $count nets with multiple PartPins"
3549## }
3550## proc rp_port_info { ports } {
3551##
3552## array set unique_ports {}
3553## foreach port [lsort -dict $ports] {
3554## set busName [get_property BUS_NAME $port]
3555## set busWidth [get_property BUS_WIDTH $port]
3556## set direction [get_property DIRECTION $port]
3557## if {[llength $busName]} {
3558## set unique_ports($busName) "$busName $busWidth $direction"
3559## } else {
3560## set unique_ports($port) "$port 0 $direction"
3561## }
3562## }
3563##
3564## set table {-title RP Ports -row \{Port Width Direction\}}
3565## foreach {port info} [lsort [array get unique_ports]] {
3566## lassign $info name width direction
3567## lappend table "-row \{$name $width $direction\}"
3568## }
3569## puts [join $table]
3570## print_table [join $table]
3571## }
3572## proc create_pr_budget { args } {
3573## set FH "stdout"
3574## set excludePins ""
3575##
3576## #Override defaults with command options
3577## set argLength [llength $args]
3578## set index 0
3579## while {$index < $argLength} {
3580## set arg [lindex $args $index]
3581## set value [lindex $args [expr $index+1]]
3582## switch -exact -- $arg {
3583## {-cell} {set cell [get_cells $value]}
3584## {-file} {set FH [open $value w]}
3585## {-exclude} {set excludePins $value}
3586## {-help} {set helpMsg "Description:"
3587## lappend helpMsg "Creates set_max_delay constraints for initial PR run.\n"
3588## lappend helpMsg "Syntax:"
3589## lappend helpMsg "create_pr_budget\ -cell <arg> \[-file <arg>] \[-exclude\]\n"
3590## lappend helpMsg "Usage:"
3591## lappend helpMsg " Name Description"
3592## lappend helpMsg " ---------------------------------------"
3593## lappend helpMsg " \[-cell] Specifies the PR cell to process."
3594## lappend helpMsg " \[-file] Optional. Specifies the output file name."
3595## lappend helpMsg " If not specified the output will be written to STDOUT"
3596## lappend helpMsg " \[-exclude] Optional. List of pins to skip."
3597## lappend helpMsg " Specifies local pin names without hierachy"
3598## lappend helpMsg " \[-help] Displays this message\n\n"
3599## foreach line $helpMsg {
3600## puts $line
3601## }
3602## return
3603## }
3604## default {set errMsg "ERROR: Specified argument $arg is not supported.\n"
3605## append errMsg "Supported arguments are -help, -cell, and -file.\n"
3606## append errMsg "Use the -help option for more details"
3607## error $errMsg
3608## }
3609## }
3610## set index [expr $index + 2]
3611## }
3612##
3613## set_msg_config -id "Constraints 18-514" -suppress
3614## set_msg_config -id "Constraints 18-515" -suppress
3615## set_msg_config -id "Constraints 18-402" -suppress
3616## puts $FH "####Budget constraints for cell $cell####"
3617##
3618##
3619## set filter "REF_NAME=~FD* || REF_NAME=~RAMB* || REF_NAME=~DSP* || REF_NAME=~SRL*"
3620## set startPoints {}
3621## set endPoints {}
3622##
3623## #Process Input Pins. Ignore pins tied to clock logic, IO buffer, or VCC/GND
3624## set inputs [get_pins -of [get_cells $cell] -filter DIRECTION==IN]
3625## puts "\tProcessing Input Pins of cell $cell ([llength $inputs] pins)"
3626## puts $FH "#Input pins:"
3627## set count 0
3628## foreach pin [lsort -dict $inputs] {
3629## if {[lsearch -exact $excludePins [lindex [split $pin /] end]] > "-1"} {
3630## puts "\tInfo: Skipping excluded pin $pin"
3631## continue
3632## }
3633## set HD_LUT [get_cells -quiet -of [get_pins -quiet -leaf -filter NAME=~$cell/HD_PR* -of [get_nets -quiet -of [get_pins $pin]]]]
3634## if {[llength $HD_LUT]} {
3635## #Get the cell names and filter out GTs, BUFG, IBUF, etc.
3636## set startPointCells [get_cells -quiet -filter $filter [all_fanin -quiet -startpoints_only -flat -only_cells $pin]]
3637## set clockPins [get_pins -quiet -filter IS_CLOCK -of $startPointCells]
3638## set clocks [get_clocks -quiet -of $clockPins]
3639## if {[llength $clocks]} {
3640## foreach clock $clocks {
3641## set timingPaths [get_timing_paths -quiet -from $startPointCells -through $pin -nworst 100000 -filter STARTPOINT_CLOCK==$clock]
3642## if {![llength $timingPaths]} {
3643## puts "\tInfo: No timing path found through pin $pin for clock $clock."
3644## continue
3645## }
3646## set startPointPins [lsort -dict -unique [join [get_pins [get_property STARTPOINT_PIN $timingPaths] -filter $filter]]]
3647## lappend startPoints [get_cells -of [get_pins $startPointPins]]
3648## set logicLevels [lindex [lsort -dict [get_property LOGIC_LEVELS $timingPaths]] end]
3649## set period [get_property PERIOD [get_clocks $clock]]
3650## #If driver is RAMB*, add level of logic to account for large clk2out times
3651## if {[lsearch [get_property REF_NAME [get_pins $startPointPins]] "RAMB*"] > "-1"} {
3652## set logicLevels [expr $logicLevels + 2]
3653## }
3654## if {$logicLevels < 1} {
3655## set percentage "0.4"
3656## } elseif {$logicLevels < 2} {
3657## set percentage "0.5"
3658## } elseif {$logicLevels < 3} {
3659## set percentage "0.6"
3660## } elseif {$logicLevels < 4} {
3661## set percentage "0.7"
3662## } elseif {$logicLevels > 4} {
3663## set percentage "0.8"
3664## puts "\tCritical Warning: Path found with $logicLevels levels of logic through pin $pin. Consider revising interface."
3665## puts "\tPath has load clock $clock with period of ${period}ns. Interface budget set to ${percentage} of period."
3666## }
3667##
3668## set value [expr $period * $percentage]
3669## puts $FH "#Pin: $pin\tLogic Levels: $logicLevels\tClock: $clock\tPeriod: $period\tBudget: $percentage"
3670## puts $FH "set_max_delay -datapath_only -from \[get_pins \[list $startPointPins\]\] -to \[get_pins $HD_LUT/I0\] $value"
3671## incr count
3672## }
3673## } elseif {[llength $clockPins]} {
3674## puts "Critical Warning: Found [llength $clockPins] clock pins \{$clockPins\} on source cells \{[lindex $startPointCells 0]\} of input pin $pin, but no clocks were defined. Ensure all required constraints have been defined. Try \"get_clocks -of \[get_pins [lindex $clockPins 0]\]\""
3675## }
3676## }
3677## if {![string match $FH "stdout"]} {
3678## flush $FH
3679## }
3680## }
3681## puts "\tAdded $count input path segmentation constraints for $cell"
3682##
3683##
3684## #Process output pins. Add set_logic_dc to prevent timing arc
3685## #from being disabled by a constant (LUT1 connected to GND).
3686## set outputs [get_pins -of [get_cells $cell] -filter DIRECTION==OUT]
3687## puts "\tProcessing Output Pins of cell $cell ([llength $outputs] pins)"
3688## puts $FH "\n#Output pins:"
3689## foreach pin [lsort -dict $outputs] {
3690## set HD_LUT [get_cells -quiet -of [get_pins -quiet -leaf -filter NAME=~$cell/HD_PR* -of [get_nets -quiet -of [get_pins $pin]]]]
3691## if {[llength $HD_LUT]} {
3692## #Set a DC on LUT initially to prevent constant propagation, or no timing paths will be found, and all_fanout will return 0 endpoints
3693## set_logic_dc [get_pins $HD_LUT/I0]
3694## }
3695## }
3696##
3697## set count 0
3698## foreach pin [lsort -dict $outputs] {
3699## if {[lsearch -exact $excludePins [lindex [split $pin /] end]] > "-1"} {
3700## puts "\tInfo: Skipping excluded pin $pin"
3701## continue
3702## }
3703## set HD_LUT [get_cells -quiet -of [get_pins -quiet -leaf -filter NAME=~$cell/HD_PR* -of [get_nets -quiet -of [get_pins $pin]]]]
3704## if {[llength $HD_LUT]} {
3705## ## #Set a DC on LUT initially to prevent constant propagation, or no timing paths will be found, and all_fanout will return 0 endpoints
3706## ## set_logic_dc [get_pins $HD_LUT/I0]
3707## #Get the cell names and filter out GTs, OBUF, etc.
3708## set endPointCells [get_cells -quiet -filter $filter [all_fanout -quiet -endpoints_only -flat -only_cells $pin]]
3709## set clockPins [get_pins -quiet -filter IS_CLOCK -of $endPointCells]
3710## set clocks [get_clocks -quiet -of $clockPins]
3711## if {[llength $clocks]} {
3712## #Add set_logic_dc to XDC or set_max_delay on outputs wont't work. Only set once on pins with endpoints.
3713## puts $FH "set_logic_dc \[get_pins $HD_LUT/I0\]"
3714## foreach clock $clocks {
3715## #set timingPaths [get_timing_paths -quiet -through $pin -to $endPointCells -max_paths 100000 -filter ENDPOINT_CLOCK==$clock]
3716## set timingPaths [get_timing_paths -quiet -through $pin -to $endPointCells -nworst 100000 -filter ENDPOINT_CLOCK==$clock]
3717## if {![llength $timingPaths]} {
3718## puts "\tCritical Warning: No timing path found through pin $pin for clock $clock."
3719## continue
3720## }
3721## set endPointPins [lsort -dict -unique [join [get_pins [get_property ENDPOINT_PIN $timingPaths] -filter $filter]]]
3722## lappend endPoints [get_cells -of [get_pins $endPointPins]]
3723## set logicLevels [lindex [lsort -dict [get_property LOGIC_LEVELS $timingPaths]] end]
3724## set period [get_property PERIOD [get_clocks $clock]]
3725## if {$logicLevels < 1} {
3726## set percentage "0.4"
3727## } elseif {$logicLevels < 2} {
3728## set percentage "0.5"
3729## } elseif {$logicLevels < 3} {
3730## set percentage "0.6"
3731## } elseif {$logicLevels < 4} {
3732## set percentage "0.7"
3733## } elseif {$logicLevels > 4} {
3734## set percentage "0.8"
3735## puts "\tCritical Warning: Path found with $logicLevels levels of logic through pin $pin. Consider revising interface."
3736## puts "\tPath has load clock $clock with period of ${period}ns. Interface budget set to ${percentage} of period."
3737## }
3738## #puts "Pin: $pin\nLoad Data Pin: $end\nLoad Clock Pin: $clock\nPeriod: $period"
3739## set value [expr $period * $percentage]
3740## puts $FH "#Pin: $pin\tLogic Levels: $logicLevels\tClock: $clock\tPeriod: $period\tBudget: $percentage"
3741## puts $FH "set_max_delay -datapath_only -from \[get_pins $HD_LUT/O\] -to \[get_pins \[list $endPointPins\]\] $value"
3742## incr count
3743## }
3744## } elseif {[llength $clockPins]} {
3745## puts "Critical Warning: Found [llength $clockPins] clock pins \{$clockPins\} on load cells \{[lindex $endPointCells 0]\} of output pin $pin, but no clocks were defined. Ensure all required constraints have been defined. Try \"get_clocks -of \[get_pins [lindex $clockPins 0]\]\""
3746## }
3747## }
3748## if {![string match $FH "stdout"]} {
3749## flush $FH
3750## }
3751## }
3752## puts "\tAdded $count output path segmentation constraints for $cell"
3753##
3754##
3755## ###Check if feedback path exists... ie. startpoint also exists as an endpoint
3756## set startPoints [lsort -dict [join $startPoints]]
3757## set endPoints [lsort -dict [join $endPoints]]
3758## foreach point $startPoints {
3759## set matches [lsearch -exact -all $endPoints $point]
3760## # puts "Cell: $point\nMatches: $matches"
3761## if {[llength $matches] > 0} {
3762## puts "\nCritical Warning: The cell \'$point\' was found in more than one budget constraint. Constraining the same cell with multiple set_max_delay may lead to undesired timing results. \nResolution:\nSearch the resulting timing constraints for the cell listed above, and determine why this is being constrained through multiple Partition Pins. Adjust the constraints or design as necessary."
3763## }
3764## }
3765##
3766## if {![string match $FH "stdout"]} {
3767## close $FH
3768## }
3769## reset_msg_config -quiet -id "Constraints 18-514" -suppress
3770## reset_msg_config -quiet -id "Constraints 18-515" -suppress
3771## reset_msg_config -quiet -id "Constraints 18-402" -suppress
3772## }
3773# check_part $part
3774INFO: Found part matching xcku060-ffva1156-2-i
3775# set verbose 1
3776# set dcpLevel 1
3777# set synthDir "./Synth${suffix}"
3778# set implDir "./Implement${suffix}"
3779# set bitDir "./Bitstreams${suffix}"
3780# set dcpDir "./Checkpoint${suffix}"
3781# set mlxDir "../mlx"
3782# set xdcDir "../sources/xdc"
3783# set verilogDir "../sources/vlog"
3784# set vhdlDir "../sources/vhdl"
3785# set xciDir "../sources/xci"
3786# set bdDir "../sources/bd"
3787# set hlsDir "../sources/ip_repo"
3788# set verilogList [glob -nocomplain $verilogDir/*.v]
3789# set vhdlList [glob -nocomplain $vhdlDir/*.vhd]
3790# set xciList [glob -nocomplain $xciDir/*/*.xci]
3791# set bdList [glob -nocomplain $bdDir/*/*.bd]
3792# set xdcList [glob -nocomplain $xdcDir/*.xdc]
3793# set xdcSynthList [list $mlxDir/mlx_user.xdc]
3794# set ipRepoList [list $hlsDir]
3795# set top "top"
3796# add_module $top
3797# set_attribute module $top moduleName $top
3798# set_attribute module $top top_level 1
3799# set_attribute module $top synthCheckpoint $mlxDir/top_synth.dcp
3800# set_attribute module $top synth 0
3801# set sbu "sbu"
3802# add_module $sbu
3803# set_attribute module $sbu moduleName $sbu
3804# set_attribute module $sbu vlog $verilogList
3805# set_attribute module $sbu vhdl $vhdlList
3806# set_attribute module $sbu ip $xciList
3807# set_attribute module $sbu bd $bdList
3808# set_attribute module $sbu ipRepo $ipRepoList
3809# set_attribute module $sbu xdc $xdcList
3810# set_attribute module $sbu synthXDC $xdcSynthList
3811# set_attribute module $sbu synth 1
3812# set sbu_instance1 "sbu"
3813# set config "Impl_fullchip"
3814# add_implementation $config
3815# set_attribute impl $config top $top
3816# set_attribute impl $config partitions [list [list $top $top implement] \
3817# [list $sbu $sbu_instance1 implement] \
3818# ]
3819# set_attribute impl $config post_phys 1
3820# set_attribute impl $config opt_directive Default
3821# set_attribute impl $config place_directive ExtraPostPlacementOpt
3822# set_attribute impl $config phys_directive AlternateFlowWithRetiming
3823# set_attribute impl $config route_directive Explore
3824# set_attribute impl $config post_phys_directive Explore
3825# set_attribute impl $config impl 1
3826# set_attribute impl $config verify 1
3827# set_attribute impl $config bitstream 1
3828# source $tclDir/run.tcl
3829## list_runs
3830
3831#HD: List of modules to be synthesized:
3832| ------- | ------------ | ---------- | --------------------------- |
3833| Module | Module Name | Top Level | Options |
3834| ------- | ------------ | ---------- | --------------------------- |
3835| sbu | sbu | 0 | -flatten_hierarchy rebuilt |
3836| ------- | ------------ | ---------- | --------------------------- |
3837
3838#HD: Defined modules not being synthesized:
3839 1. top (top)
3840#HD: No Configurations set to be implemented
3841
3842#HD: List of Implementations to be implemented:
3843| --------------- | --------------- | --------------- | ---------- | --------------- |
3844| Implementation | Top | Partitions | Flow Type | write_bistream |
3845| --------------- | --------------- | --------------- | ---------- | --------------- |
3846| Impl_fullchip | top(implement) | sbu(implement) | Flat | 1 |
3847| --------------- | --------------- | --------------- | ---------- | --------------- |
3848
3849
3850
3851## foreach module [get_modules synth] {
3852## synthesize $module
3853## }
3854#HD: Running synthesis for block sbu
3855 Writing results to: ./Synth/sbu
3856 Loading IP Repositories:
3857 + ../sources/ip_repo
3858INFO: [IP_Flow 19-234] Refreshing IP repositories
3859INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/roliveira31/Downloads/user/sources/ip_repo'.
3860INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Appl/Xilinx/Vivado/2018.1/data/ip'.
3861ERROR: [Common 17-163] Missing value for option 'objects', please type 'set_property -help' for usage info.
3862
3863 while executing
3864"source $tclDir/run.tcl"
3865 (file "create_project.tcl" line 111)
3866INFO: [Common 17-206] Exiting Vivado at Tue Jul 31 10:37:41 2018...