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34 <h1 id="firstHeading" class="firstHeading" lang="en">ST STE Scanlines</h1>
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41 <div id="mw-content-text" dir="ltr" class="mw-content-ltr" lang="en"><div class="mw-parser-output"><p>The
42 following is a pseudo code description of how the circuitry involved in
43 creating scanlines, including sync pulses and displaying of pixel data,
44 functions in the Atari ST and STE. By following the logic described
45here it's possible to implement emulators and simulators that will be
46able to run existing Atari ST and STE programs that make use of "sync
47tricks" to create fullscreens and sync scrollers.
48</p><p>Disclaimer: This page has as a goal to contain everything that's
49currently known, but by no means it should be considered complete.
50</p><p><br>
51<i>Collected, edited, researched and typed up by Troed of SYNC</i>
52</p><p><br>
53Information used to create these tables has mostly been sourced from the
54 people below, but a general thanks goes out to everyone who's ever
55written anything on the subject.
56</p>
57<ul><li> Alien of ST Connexion (Overscan Techniques part I and II) <a rel="nofollow" class="external autonumber" href="http://alive.atari.org/alive9/ovrscn1.php">[1]</a> <a rel="nofollow" class="external autonumber" href="http://alive.atari.org/alive11/menutext.php">[2]</a></li>
58<li> Paulo Simoes (posts on Atari-Forum, wakestate discovery and ST documentation) <a rel="nofollow" class="external autonumber" href="http://www.atari-forum.com/viewtopic.php?f=16&t=24855&start=183">[3]</a> </li>
59<li> Dio (posts on Atari-Forum, trace diagrams, DE-to-LOAD) <a rel="nofollow" class="external autonumber" href="http://www.atari-forum.com/viewtopic.php?f=16&t=24855&start=363">[4]</a></li>
60<li> Troed of SYNC (GLUE-CPU wakestate hypothesis, STE pre-fetch impact) <a rel="nofollow" class="external autonumber" href="http://www.atari-forum.com/viewtopic.php?f=16&t=24855&start=407">[5]</a></li>
61<li> Ijor (original research and confirmation from chip-decaps) <a rel="nofollow" class="external autonumber" href="http://www.atari-forum.com/viewtopic.php?f=16&t=29658">[6]</a></li></ul>
62<div id="toc" class="toc"><div class="toctitle"><h2>Contents</h2><span class="toctoggle"> [<a role="button" tabindex="0" class="togglelink">hide</a>] </span></div>
63<ul>
64<li class="toclevel-1 tocsection-1"><a href="#Horizontal_GLUE_state_machine.2C_ST"><span class="tocnumber">1</span> <span class="toctext">Horizontal GLUE state machine, ST</span></a></li>
65<li class="toclevel-1 tocsection-2"><a href="#MMU.2C_ST"><span class="tocnumber">2</span> <span class="toctext">MMU, ST</span></a></li>
66<li class="toclevel-1 tocsection-3"><a href="#Horizontal_GST_MCU_state_machine.2C_STE"><span class="tocnumber">3</span> <span class="toctext">Horizontal GST MCU state machine, STE</span></a></li>
67<li class="toclevel-1 tocsection-4"><a href="#Vertical_GLUE.2FGST-MCU_state_machine.2C_ST.2FSTE"><span class="tocnumber">4</span> <span class="toctext">Vertical GLUE/GST-MCU state machine, ST/STE</span></a></li>
68<li class="toclevel-1 tocsection-5"><a href="#Shifter_state_machine"><span class="tocnumber">5</span> <span class="toctext">Shifter state machine</span></a></li>
69<li class="toclevel-1 tocsection-6"><a href="#Sync_line_lengths"><span class="tocnumber">6</span> <span class="toctext">Sync line lengths</span></a></li>
70<li class="toclevel-1 tocsection-7"><a href="#Clean_vs_sync_disrupting"><span class="tocnumber">7</span> <span class="toctext">Clean vs sync disrupting</span></a></li>
71<li class="toclevel-1 tocsection-8"><a href="#Future_research_.2F_Incomplete"><span class="tocnumber">8</span> <span class="toctext">Future research / Incomplete</span></a></li>
72</ul>
73</div>
74
75<h2><span class="mw-headline" id="Horizontal_GLUE_state_machine.2C_ST">Horizontal GLUE state machine, ST</span></h2>
76<p>Due to lack of synchronisation between GLUE and CPU when an ST is
77powered on both chips, while running at 8MHz, can be offset from each
78other. This is the hypothesised cause behind what's known as ST "wakeup
79modes" (where two were known and documented beginning 2006 <a rel="nofollow" class="external autonumber" href="http://www.atari-forum.com/viewtopic.php?f=68&t=9527&start=34">[7]</a>) and more recently divided into two more making four in total, now known as "wakestates" (2013) <a rel="nofollow" class="external autonumber" href="http://www.atari-forum.com/viewtopic.php?f=16&t=24855&start=147">[8]</a>.
80</p><p>At each cycle in the table below, as seen by the CPU, the value
81can be offset 0-3 cycles set when the ST is powered on. This offset does
82 not change when reset, only when powered off and on again. While this
83looks like an emulator/simulator needing to be one-cycle accurate to
84fully capture these modes it's as far as currently known not needed.
85Since sync tricks can only be made with a resolution of two cycles (by
86using EXG+MOVE and similar instructions) it's possible to emulate all
87tricks with two cycle emulation granularity as well.
88</p><p>The GLUE combines the values of $ff820a (FREQ) and $ff8260 (RES)
89for its purposes. The tables use the short form 50/60/71 to represent
90that combined value.
91</p>
92<table>
93<tbody><tr>
94<td>VAR H
95</td>
96<td>H signal as per Alien's doc, combines with V and becomes DE detected by MMU
97</td></tr>
98<tr>
99<td>VAR LINE
100</td>
101<td>(LORES) NTSC by default; PAL = 512 cycle 50Hz, NTSC = 508 cycle 60Hz, HIRES = 224 cycle 71Hz
102</td></tr>
103<tr>
104<td>VAR BLANK
105</td>
106<td>Activate blank if true.
107</td></tr>
108<tr>
109<td>VAR HSYNC
110</td>
111<td>Activate hsync if true.
112</td></tr></tbody></table>
113<table cellspacing="0" cellpadding="4" border="1">
114<tbody><tr>
115<th>Cycle
116</th>
117<th>Action
118</th></tr>
119<tr>
120<td>4
121</td>
122<td>IF(71) H = TRUE
123</td></tr>
124<tr>
125<td>24
126</td>
127<td>IF(60) BLANK = FALSE
128</td></tr>
129<tr>
130<td>28
131</td>
132<td>IF(50) BLANK = FALSE
133</td></tr>
134<tr>
135<td>30
136</td>
137<td>Unknown. Needs to be !71 in non-mono lines.
138</td></tr>
139<tr>
140<td>52
141</td>
142<td>IF(60) H = TRUE
143</td></tr>
144<tr>
145<td>54
146</td>
147<td>IF(60) LINE = 508 ELSEIF(50) LINE = 512
148</td></tr>
149<tr>
150<td>56
151</td>
152<td>IF(50) H = TRUE
153</td></tr>
154<tr>
155<td>164
156</td>
157<td>IF(71) H = FALSE
158</td></tr>
159<tr>
160<td>184
161</td>
162<td>IF(71) BLANK = TRUE
163</td></tr>
164<tr>
165<td>372
166</td>
167<td>IF(60) H = FALSE
168</td></tr>
169<tr>
170<td>376
171</td>
172<td>IF(50) H = FALSE
173</td></tr>
174<tr>
175<td>450
176</td>
177<td>IF(!71) BLANK = TRUE
178</td></tr>
179<tr>
180<td>LINE-50
181</td>
182<td>IF(!71) HSYNC = TRUE && H = FALSE
183</td></tr>
184<tr>
185<td>LINE-10
186</td>
187<td>IF(!71) HSYNC = FALSE
188</td></tr></tbody></table>
189<p>Due to the internal workings of the GLUE it will latch 820a (FREQ)
190one cycle later than 8260 (RES). At any specific comparison cycle this
191means the GLUE will use the FREQ value written one cycle before RES.
192</p>
193<ul><li> Offset 0 reads values at cycle 56 (FREQ) and 57 (RES)</li>
194<li> Offset 1 reads values at cycle 57 (FREQ) and 58 (RES)</li>
195<li> Offset 2 reads values at cycle 58 (FREQ) and 59 (RES)</li>
196<li> Offset 3 reads values at cycle 59 (FREQ) and 60 (RES)</li></ul>
197<p>The above, as seen by a program running on the CPU, means that to be
198able to change the values of the registers for the GLUE to pick them up
199in the current wakestate they need to have been done at the following
200cycles:
201</p>
202<ul><li> WS1 (DL6): Changes made by 56 (FREQ), 56 (RES)</li>
203<li> WS3 (DL5): Changes made by 56 (FREQ), 58 (RES)</li>
204<li> WS4 (DL4): Changes made by 58 (FREQ), 58 (RES)</li>
205<li> WS2 (DL3): Changes made by 58 (FREQ), 60 (RES)</li></ul>
206<p>As can be seen above these four different combinations have been
207given their own numbering - they are the four known wakestates. Any
208program that needs to do detailed sync manipulation, depending on how
209detailed, needs to detect which wakestate the ST is in and modify its
210timing. Since wakeup modes were only documented and detected in 2006,
211some classic demos shows such side effects. The TCB "tv-snow" screen in
212Swedish New Year Demo has a disting logo that's only centered in
213wakestate 2 - in all the others it's offset to the left. <a rel="nofollow" class="external autonumber" href="http://www.atari-forum.com/viewtopic.php?f=16&t=24855&start=342">[9]</a>
214</p><p>The DL3-DL6 moniker in parenthesis above is another way to name
215the wakestates, after how long the delay is between the GLUE raising DE
216(Display Enable), which it does one cycle later than the checks
217described above, and the MMU detecting it <a rel="nofollow" class="external autonumber" href="http://www.atari-forum.com/viewtopic.php?f=16&t=24855&start=274">[10]</a>.
218 This has also the side effect of the wakestates being physically offset
219 on screen by one pixel from eachother - WS2 (DL3) leftmost and WS1
220(DL6) rightmost. This is caused by monitors using HSYNC to place the
221screen and depending on wakestate the distance between the HSYNC pulse
222and the displayed pixels differs.
223</p>
224<h2><span class="mw-headline" id="MMU.2C_ST">MMU, ST</span></h2>
225<table>
226<tbody><tr>
227<td>VAR DE
228</td>
229<td>The H signal from GLUE above combined with V
230</td></tr>
231<tr>
232<td>VAR LOAD
233</td>
234<td>Signal sent to Shifter for each new memory read available
235</td></tr></tbody></table>
236<p>MMU detects GLUE DE at cycle 62 and raises LOAD at cycle 64. From this we can calculate the DL-moniker <a rel="nofollow" class="external autonumber" href="http://www.atari-forum.com/viewtopic.php?f=16&t=24855&start=274">[11]</a> for the ST wakestates depending on when GLUE raised DE:
237</p>
238<ul><li> 64-58 = 6 = DL6</li>
239<li> 64-59 = 5 = DL5</li>
240<li> 64-60 = 4 = DL4</li>
241<li> 64-61 = 3 = DL3</li></ul>
242<p>After LOAD it takes 16 cycles, plus 2 due to internal delays, for the
243 Shifter to set the first values on the RGB pins. As long as DE is high
244LOAD will loop with new data available. For each word read by the
245Shifter the MMU will increase the video counter.
246</p><p>Note: These cycle timings are NOT affected by ST wake states
247</p><p>Examples:
248</p>
249<ul><li> Cycle 8, GLUE raised DE. MMU will raise LOAD at cycle 12</li>
250<li> Cycle 60, GLUE raised DE. MMU will raise LOAD at cycle 64</li>
251<li> Cycle 380, GLUE lowered DE. MMU will no longer raise LOAD from cycle 384</li></ul>
252<h2><span class="mw-headline" id="Horizontal_GST_MCU_state_machine.2C_STE">Horizontal GST MCU state machine, STE</span></h2>
253<p>In the STE the GLUE and MMU were combined into a single circuit, the
254GST MCU. This also meant that the GLUE and CPU were no longer offset by
2550-3 cycles as on the ST but fully synchronised at 0. Thus there are no
256GLUE wakeup modes/wakestates known on the STE. Several changes were
257however made to accommodate hardware scroll support where one of the
258more notable ones was an earlier check for starting the screen in high
259res (= left border) which caused many older border removing demos to
260fail.
261</p>
262<table>
263<tbody><tr>
264<td>VAR H
265</td>
266<td>H signal as per Alien's doc, combines with V and becomes DE
267</td></tr>
268<tr>
269<td>VAR PRELOAD
270</td>
271<td>MMU starts LOADing Shifter with words for hardware scroll purposes, no screen address changes
272</td></tr>
273<tr>
274<td>VAR LINE
275</td>
276<td>(LORES) NTSC by default; PAL = 512 cycle 50Hz, NTSC = 508 cycle 60Hz, HIRES = 224 cycle 71Hz
277</td></tr>
278<tr>
279<td>VAR BLANK
280</td>
281<td>Activate blank if true.
282</td></tr>
283<tr>
284<td>VAR HSYNC
285</td>
286<td>Activate hsync if true.
287</td></tr></tbody></table>
288<table cellspacing="0" cellpadding="4" border="1">
289<tbody><tr>
290<th>Cycle
291</th>
292<th>Action
293</th></tr>
294<tr>
295<td>0
296</td>
297<td>IF(71) PRELOAD = TRUE
298</td></tr>
299<tr>
300<td>24
301</td>
302<td>IF(60) BLANK = FALSE
303</td></tr>
304<tr>
305<td>28
306</td>
307<td>IF(50) BLANK = FALSE
308</td></tr>
309<tr>
310<td>28
311</td>
312<td>Unknown. Needs to be !71 in non-mono lines.
313</td></tr>
314<tr>
315<td>36
316</td>
317<td>IF(60) PRELOAD = TRUE
318</td></tr>
319<tr>
320<td>40
321</td>
322<td>IF(50) PRELOAD = TRUE
323</td></tr>
324<tr>
325<td>56
326</td>
327<td>IF(60) LINE = 508 ELSEIF(50) LINE = 512
328</td></tr>
329<tr>
330<td>58
331</td>
332<td>Also related to line length similar to above for 50/60Hz. Unknown cause.
333</td></tr>
334<tr>
335<td>164
336</td>
337<td>IF(71) H = FALSE
338</td></tr>
339<tr>
340<td>184
341</td>
342<td>IF(71) BLANK = TRUE
343</td></tr>
344<tr>
345<td>372
346</td>
347<td>IF(60) H = FALSE
348</td></tr>
349<tr>
350<td>376
351</td>
352<td>IF(50) H = FALSE
353</td></tr>
354<tr>
355<td>448
356</td>
357<td>IF(!71) BLANK = TRUE
358</td></tr>
359<tr>
360<td>LINE-52
361</td>
362<td>IF(!71) HSYNC = TRUE && H = FALSE
363</td></tr>
364<tr>
365<td>LINE-12
366</td>
367<td>IF(!71) HSYNC = FALSE
368</td></tr></tbody></table>
369<p>The following pseudo code describes how PRELOAD gets handled:
370</p>
371<pre>WORDS_READ=0
372WHILE(PRELOAD == TRUE) {
373 LOAD
374 WORDS_READ++
375 IF(RES == HIGH AND WORDS_READ=>1) PRELOAD = FALSE
376 IF(RES == LO AND WORDS_READ=>4) PRELOAD = FALSE
377}
378H = TRUE
379</pre>
380<p>In regular HI resolution the routine will exit after four cycles (one
381 word) and in LO resolution it will take 16 cycles (four words). This is
382 what makes the STE timings for raised DE match up with ST. It's also
383why it's possible to create +20 (left border), +4 and +6 (regular) line
384by disrupting this code, according to the following:
385</p>
386<table cellspacing="0" cellpadding="4" border="1">
387<tbody><tr>
388<th>Cycle
389</th>
390<th>Action
391</th>
392<th>Result
393</th></tr>
394<tr>
395<td>4
396</td>
397<td>IF(RES == LO) PRELOAD will run until cycle 16
398</td>
399<td>(56-16)/2 = +20
400</td></tr>
401<tr>
402<td>44
403</td>
404<td>IF(RES == HI) PRELOAD will exit after 4 cycles
405</td>
406<td>(376-44)/2 = +6
407</td></tr>
408<tr>
409<td>48
410</td>
411<td>IF(RES == HI) PRELOAD will exit after 8 cycles
412</td>
413<td>(376-48)/2 = +4
414</td></tr></tbody></table>
415<p>Todo: Describe when H becomes DE in cycles as already done for ST MMU
416</p>
417<h2><span class="mw-headline" id="Vertical_GLUE.2FGST-MCU_state_machine.2C_ST.2FSTE">Vertical GLUE/GST-MCU state machine, ST/STE</span></h2>
418<table>
419<tbody><tr>
420<td>VAR V
421</td>
422<td>V signal as per Alien's doc, combines with H and becomes DE
423</td></tr>
424<tr>
425<td>VAR VBLANK
426</td>
427<td>Activate vblank if true. When VBLANK is set no RES/FREQ checks are made (or simply no DE changes?)
428</td></tr></tbody></table>
429<table cellspacing="0" cellpadding="4" border="1">
430<tbody><tr>
431<th>Line
432</th>
433<th>Cycle
434</th>
435<th>Action
436</th></tr>
437<tr>
438<td>34
439</td>
440<td>502
441</td>
442<td>IF(60) V = TRUE
443</td></tr>
444<tr>
445<td>47/63
446</td>
447<td>502
448</td>
449<td>IF(50) V = TRUE
450</td></tr>
451<tr>
452<td>234
453</td>
454<td>502
455</td>
456<td>IF(60) V = FALSE
457</td></tr>
458<tr>
459<td>247/263
460</td>
461<td>502
462</td>
463<td>IF(50) V = FALSE
464</td></tr>
465<tr>
466<td>258
467</td>
468<td>502
469</td>
470<td>IF(60) VBLANK = TRUE
471</td></tr>
472<tr>
473<td>308
474</td>
475<td>502
476</td>
477<td>IF(50) VBLANK = TRUE
478</td></tr></tbody></table>
479<ul><li> <b>47</b>/63 and <b>247</b>/263 are what's known as the "short
480top border" STs. A few early models apparently had a different GLUE
481revision where the PAL 50Hz screen began higher up, which was then
482subsequently changed.</li>
483<li> Number of lines that will be displayed is likely to be decided when
484 the screen starts, just as number of cycles in a line. Untested.</li>
485<li> It's possible to avoid VBLANK at line 308, which will result in two
486 extra full lines of graphics as well as a few pixels on line 311 until
487VSYNC kicks in hard at cycle ~30</li></ul>
488<p>Todo: Update table with RES equivalents.
489</p>
490<h2><span class="mw-headline" id="Shifter_state_machine">Shifter state machine</span></h2>
491<p>Regular sync scrolling is made with changes affecting GLUE. 4-pixel
492sync scrolling as well as the cause for "stable" and "unstable" sync
493lines is due to Shifter.
494</p><p><b>Work in progress. Please read through Alien's articles first
495for terminology. This writeup will be expanded upon in time, and likely
496contains severe errors.</b>
497</p><p>The Shifter has two types of registers. A four word FIFO buffer
498("IR" in Alien's articles) and four words used as shift-registers ("RR")
499 that are shifted out every cycle together with a palette lookup that
500sets the correct value on the RGB/Mono pins. When Shifter receives LOAD
501from the MMU it will read a word to the FIFO. The shift-registers are
502constantly shifting out data. In low resolution all four words shift
503together, in medium resolution two of them shift together and in high
504resolution one shift at a time. Every 16 cycles a check is made to see
505whether the FIFO is full and the contents will then be copied to RR. If
506 DE is not active, LOAD will not be asserted, the FIFO will not be
507refilled, and RR will not be updated. When RR is not updated with new
508data, the registers will be 0, and the border color will be displayed.
509</p><p>The concept of a FIFO is hypothesized to be the explanation for
510"every other 16 pixels black", a Shifters substate that in reality is
511border color (palette 0), and is only "every other" in low resolution.
512In high resolution it's every fifth group of 16 pixels. The cause is
513speculated to be that sometimes the copy from IR to RR simply fails.
514This will cause all zeros (palette 0) to be shifted out for 16 cycles.
515Since the next group of 16 pixels are displayed in the correct position
516one word must've been pushed out from the FIFO and the next have been
517added correctly.
518</p>
519<h2><span class="mw-headline" id="Sync_line_lengths">Sync line lengths</span></h2>
520<p>Sync scrollers are created by combining scanlines of different
521lengths, as read in bytes, to cause the displayed screen to be offset by
522 a chosen amount. It's possible to calculate the amount of bytes lines
523created by modifying the FREQ and RES registers in GLUE use as follows
524(see the GLUE state machines for the specific actions needed):
525</p>
526<table cellspacing="0" cellpadding="4" border="1">
527<tbody><tr>
528<th> Bytes
529</th>
530<th> Method
531</th></tr>
532<tr>
533<td>0
534</td>
535<td>DE never activated
536</td></tr>
537<tr>
538<td>54
539</td>
540<td>DE activated at 60, deactivated at 168. (168-60)/2 = 54
541</td></tr>
542<tr>
543<td>56
544</td>
545<td>DE activated at 56, deactivated at 168. (168-56)/2 = 56
546</td></tr>
547<tr>
548<td>80
549</td>
550<td>DE activated at 8, deactivated at 168. (168-8)/2 = 80
551</td></tr>
552<tr>
553<td>158
554</td>
555<td>DE activated at 60, deactivated at 376. (376-60)/2 = 158
556</td></tr>
557<tr>
558<td>160
559</td>
560<td>DE activated at 56, deactivated at 376. (376-56)/2 = 160
561</td></tr>
562<tr>
563<td>160
564</td>
565<td>DE activated at 60, deactivated at 380. (380-60)/2 = 160
566</td></tr>
567<tr>
568<td>162
569</td>
570<td>DE activated at 56, deactivated at 380. (380-56)/2 = 162
571</td></tr>
572<tr>
573<td>184
574</td>
575<td>DE activated at 8, deactivated at 376. (376-8)/2 = 184
576</td></tr>
577<tr>
578<td>186
579</td>
580<td>DE activated at 8, deactivated at 380. (380-8)/2 = 186
581</td></tr>
582<tr>
583<td>204
584</td>
585<td>DE activated at 60, deactivated at 468. (468-60)/2 = 204
586</td></tr>
587<tr>
588<td>206
589</td>
590<td>DE activated at 56, deactivated at 468. (468-56)/2 = 206
591</td></tr>
592<tr>
593<td>230
594</td>
595<td>DE activated at 8, deactivated at 468. (468-8)/2 = 230
596</td></tr></tbody></table>
597<p>The above examples are PAL, as most demos use. It's however equally
598easy to calculate how wide (in bytes - multiply by two to get pixels) a
599left border would be in NTSC compared to PAL:
600</p>
601<ul><li> DE activated at 8 compared to regular NTSC line at 56. (56-8)/2 = 24 bytes</li>
602<li> DE activated at 8 compared to regular PAL line at 60. (60-8)/2 = 26 bytes</li></ul>
603<p>And a right border:
604</p>
605<ul><li> DE deactivated at 468 compared to regular PAL line at 380. (468-380)/2 = 44 bytes</li>
606<li> DE deactivated at 464 compared to regular NTSC line at 376. (464-376)/2 = 44 bytes
607<ul><li> Note: An NTSC line is 508 cycles instead of 512 so the deactivation due to HSYNC will happen at 464</li></ul></li></ul>
608<p>Paulo has written a test program for ST that displays many of the possible combinations, attached to a forum post here: <a rel="nofollow" class="external autonumber" href="http://www.atari-forum.com/viewtopic.php?f=16&t=24855&start=181">[12]</a>
609</p>
610<h2><span class="mw-headline" id="Clean_vs_sync_disrupting">Clean vs sync disrupting</span></h2>
611<p>Some effects possible to make by changing state of the GLUE also
612cause changes to the signals BLANK and HSYNC. Depending on how forgiving
613 the monitor/TV set used is these effects might seems fully working, or
614cause "bent" lines or discolorisation of parts of the screen. As a
615general rule these signals should not be modified, but since they have
616been in demos this is a brief documentation of their effects (timings
617used are ST, see STE state machine for counterparts):
618</p>
619<ul><li> Delaying BLANK at 450 - caused by the use of HI/LO stabilizer
620at 444/456. Additional pixel data, if existing, will be displayed and
621could cause sync signal disruption.</li>
622<li> Cancelling HSYNC at 462 - black line (no pixels shown) and disrupted sync signal if right border wasn't removed</li>
623<li> Cancelling HSYNC at 462 - fully displayed line with disrupted sync
624signal if the right border had been opened, Display Enable constantly
625set. This is done by mistake by the initialization code in the game
626Enchanted Lands by TCB <a rel="nofollow" class="external autonumber" href="http://www.atari-forum.com/viewtopic.php?f=68&t=9527&start=114">[13]</a></li>
627<li> Extending HSYNC at 502 - 0 byte line and disrupted sync signal.</li>
628<li> Extending BLANK at 30 - 0 byte line and disrupted sync signal.</li></ul>
629<p>It's possible (currently untested) that using MID/LO stabilizer at
630440/456 (also known as "ULM stabilizer") won't delay BLANK. For the
631other cases there are other ways to black out a line as well as creating
632 0 byte lines that do not disrupt sync.
633</p>
634<h2><span class="mw-headline" id="Future_research_.2F_Incomplete">Future research / Incomplete</span></h2>
635<ul><li> the 14 byte line (RES = HI at cycle 32 will cause HSYNC which
636will cancel DE 4 cycles later. (36-8)/2 = 14) (disrupts sync and
637shouldn't be used anyway)</li>
638<li> Shifter state machine</li></ul>
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