· 8 years ago · Feb 21, 2018, 09:52 PM
1
2
3#include "stdafx.h"
4#include <winsock2.h>
5
6#pragma comment(lib, "wsock32.lib")
7
8
9#define STUDENT_NUMBER "17018367"
10
11#define IP_ADDRESS_SERVER "127.0.0.1"
12
13#define PORT_SERVER 0x1984 // We define a port that we are going to use.
14#define PORT_CLIENT 0x1985 // We define a port that we are going to use.
15
16#define WORD unsigned short
17#define DWORD unsigned long
18#define BYTE unsigned char
19
20#define MAX_FILENAME_SIZE 500
21#define MAX_BUFFER_SIZE 500
22
23SOCKADDR_IN server_addr;
24SOCKADDR_IN client_addr;
25
26SOCKET sock; // This is our socket, it is the handle to the IO address to read/write packets
27
28WSADATA data;
29
30char InputBuffer [MAX_BUFFER_SIZE];
31
32char hex_file [MAX_BUFFER_SIZE];
33char trc_file [MAX_BUFFER_SIZE];
34
35//////////////////////////
36// Registers //
37//////////////////////////
38
39#define FLAG_I 0x10
40#define FLAG_V 0x08
41#define FLAG_N 0x04
42#define FLAG_Z 0x02
43#define FLAG_C 0x01
44#define REGISTER_A 5
45#define REGISTER_F 4
46#define REGISTER_E 3
47#define REGISTER_D 2
48#define REGISTER_C 1
49#define REGISTER_B 0
50#define REGISTER_X 0
51#define REGISTER_Y 1
52BYTE Index_Registers[2];
53
54BYTE Registers[6];
55BYTE Flags;
56WORD ProgramCounter;
57WORD StackPointer;
58
59
60////////////
61// Memory //
62////////////
63
64#define MEMORY_SIZE 65536
65
66BYTE Memory[MEMORY_SIZE];
67
68#define TEST_ADDRESS_1 0x01FA
69#define TEST_ADDRESS_2 0x01FB
70#define TEST_ADDRESS_3 0x01FC
71#define TEST_ADDRESS_4 0x01FD
72#define TEST_ADDRESS_5 0x01FE
73#define TEST_ADDRESS_6 0x01FF
74#define TEST_ADDRESS_7 0x0200
75#define TEST_ADDRESS_8 0x0201
76#define TEST_ADDRESS_9 0x0202
77#define TEST_ADDRESS_10 0x0203
78#define TEST_ADDRESS_11 0x0204
79#define TEST_ADDRESS_12 0x0205
80
81
82///////////////////////
83// Control variables //
84///////////////////////
85
86bool memory_in_range = true;
87bool halt = false;
88
89
90///////////////////////
91// Disassembly table //
92///////////////////////
93
94char opcode_mneumonics[][14] =
95{
96"ILLEGAL ",
97"ILLEGAL ",
98"STX abs ",
99"ILLEGAL ",
100"ILLEGAL ",
101"ILLEGAL ",
102"ILLEGAL ",
103"MV #,B ",
104"MV #,C ",
105"MV #,D ",
106"MV #,E ",
107"MV #,F ",
108"MAY impl ",
109"MYA impl ",
110"MAS impl ",
111"CSA impl ",
112
113"ILLEGAL ",
114"ILLEGAL ",
115"STX abs,X ",
116"ILLEGAL ",
117"ILLEGAL ",
118"ILLEGAL ",
119"SWI impl ",
120"RTI impl ",
121"CLC impl ",
122"SEC impl ",
123"CLI impl ",
124"STI impl ",
125"STV impl ",
126"3 impl ",
127"ILLEGAL ",
128"ILLEGAL ",
129
130"ILLEGAL ",
131"ILLEGAL ",
132"STX abs,Y ",
133"ADD A,B ",
134"SUB A,B ",
135"CMP A,B ",
136"OR A,B ",
137"AND A,B ",
138"EOR A,B ",
139"BT A,B ",
140"LD A,A ",
141"LD B,A ",
142"LD C,A ",
143"LD D,A ",
144"LD E,A ",
145"LD F,A ",
146
147"ILLEGAL ",
148"LDX # ",
149"STX abs,XY ",
150"ADD A,C ",
151"SUB A,C ",
152"CMP A,C ",
153"OR A,C ",
154"AND A,C ",
155"EOR A,C ",
156"BT A,C ",
157"LD A,B ",
158"LD B,B ",
159"LD C,B ",
160"LD D,B ",
161"LD E,B ",
162"LD F,B ",
163
164"ILLEGAL ",
165"LDX abs ",
166"STX (ind),XY ",
167"ADD A,D ",
168"SUB A,D ",
169"CMP A,D ",
170"OR A,D ",
171"AND A,D ",
172"EOR A,D ",
173"BT A,D ",
174"LD A,C ",
175"LD B,C ",
176"LD C,C ",
177"LD D,C ",
178"LD E,C ",
179"LD F,C ",
180
181"ILLEGAL ",
182"LDX abs,X ",
183"ILLEGAL ",
184"ADD A,E ",
185"SUB A,E ",
186"CMP A,E ",
187"OR A,E ",
188"AND A,E ",
189"EOR A,E ",
190"BT A,E ",
191"LD A,D ",
192"LD B,D ",
193"LD C,D ",
194"LD D,D ",
195"LD E,D ",
196"LD F,D ",
197
198"ILLEGAL ",
199"LDX abs,Y ",
200"ILLEGAL ",
201"ADD A,F ",
202"SUB A,F ",
203"CMP A,F ",
204"OR A,F ",
205"AND A,F ",
206"EOR A,F ",
207"BT A,F ",
208"LD A,E ",
209"LD B,E ",
210"LD C,E ",
211"LD D,E ",
212"LD E,E ",
213"LD F,E ",
214
215"ILLEGAL ",
216"LDX abs,XY ",
217"ILLEGAL ",
218"NOP impl ",
219"HLT impl ",
220"ILLEGAL ",
221"ILLEGAL ",
222"ILLEGAL ",
223"ILLEGAL ",
224"ILLEGAL ",
225"LD A,F ",
226"LD B,F ",
227"LD C,F ",
228"LD D,F ",
229"LD E,F ",
230"LD F,F ",
231
232"ILLEGAL ",
233"LDX (ind),XY ",
234"ADI # ",
235"SBI # ",
236"CPI # ",
237"ORI # ",
238"ANI # ",
239"XRI # ",
240"ILLEGAL ",
241"ILLEGAL ",
242"ILLEGAL ",
243"ILLEGAL ",
244"ILLEGAL ",
245"ILLEGAL ",
246"ILLEGAL ",
247"ILLEGAL ",
248
249"LDA # ",
250"TST abs ",
251"INC abs ",
252"DEC abs ",
253"RCR abs ",
254"RLC abs ",
255"ASL abs ",
256"SAR abs ",
257"COM abs ",
258"RAL abs ",
259"ROR abs ",
260"LX #,A ",
261"ILLEGAL ",
262"LODS # ",
263"PUSH ,A ",
264"POP A, ",
265
266"LDA abs ",
267"TST abs,X ",
268"INC abs,X ",
269"DEC abs,X ",
270"RCR abs,X ",
271"RLC abs,X ",
272"ASL abs,X ",
273"SAR abs,X ",
274"COM abs,X ",
275"RAL abs,X ",
276"ROR abs,X ",
277"ILLEGAL ",
278"STO abs ",
279"LODS abs ",
280"PUSH ,s ",
281"POP s, ",
282
283"LDA abs,X ",
284"TST abs,Y ",
285"INC abs,Y ",
286"DEC abs,Y ",
287"RCR abs,Y ",
288"RLC abs,Y ",
289"ASL abs,Y ",
290"SAR abs,Y ",
291"COM abs,Y ",
292"RAL abs,Y ",
293"ROR abs,Y ",
294"ILLEGAL ",
295"STO abs,X ",
296"LODS abs,X ",
297"PUSH ,B ",
298"POP B, ",
299
300"LDA abs,Y ",
301"TST abs,XY ",
302"INC abs,XY ",
303"DEC abs,XY ",
304"RCR abs,XY ",
305"RLC abs,XY ",
306"ASL abs,XY ",
307"SAR abs,XY ",
308"COM abs,XY ",
309"RAL abs,XY ",
310"ROR abs,XY ",
311"ILLEGAL ",
312"STO abs,Y ",
313"LODS abs,Y ",
314"PUSH ,C ",
315"POP C, ",
316
317"LDA abs,XY ",
318"TSTA A,A ",
319"INCA A,A ",
320"DECA A,A ",
321"RCRA A,A ",
322"RLCA A,A ",
323"ASLA A,A ",
324"SARA A,A ",
325"COMA A,A ",
326"RALA A,A ",
327"RORA A,A ",
328"RTN impl ",
329"STO abs,XY ",
330"LODS abs,XY ",
331"PUSH ,D ",
332"POP D, ",
333
334"LDA (ind),XY ",
335"DEX impl ",
336"INX impl ",
337"DEY impl ",
338"INCY impl ",
339"ILLEGAL ",
340"ILLEGAL ",
341"ILLEGAL ",
342"ILLEGAL ",
343"JSR abs ",
344"JMP abs ",
345"ILLEGAL ",
346"STO (ind),XY ",
347"LODS (ind),XY",
348"PUSH ,E ",
349"POP E, ",
350
351"BRA rel ",
352"BCC rel ",
353"BCS rel ",
354"BNE rel ",
355"BEQ rel ",
356"BVC rel ",
357"BVS rel ",
358"BMI rel ",
359"BPL rel ",
360"BGE rel ",
361"BLE rel ",
362"BGT rel ",
363"BLT rel ",
364"ILLEGAL ",
365"PUSH ,F ",
366"POP F, ",
367
368};
369
370////////////////////////////////////////////////////////////////////////////////
371// Simulator/Emulator (Start) //
372////////////////////////////////////////////////////////////////////////////////
373
374BYTE fetch()
375{
376 BYTE byte = 0;
377
378 if ((ProgramCounter >= 0) && (ProgramCounter <= MEMORY_SIZE))
379 {
380 memory_in_range = true;
381 byte = Memory[ProgramCounter];
382 ProgramCounter++;
383 }
384 else
385 {
386 memory_in_range = false;
387 }
388 return byte;
389}
390
391void set_flag_c(BYTE inReg)
392{
393 BYTE reg;
394 reg = inReg;
395
396 if (reg >= 0x100)
397 {
398 Flags = Flags | FLAG_C; //Set the carry flag
399 }
400 else
401 {
402 Flags = Flags & (0xFF - FLAG_C); //Clear the carry flag
403 }
404}
405
406
407
408void set_flag_n(BYTE inReg) // negative flag
409{
410 BYTE reg;
411 reg = inReg;
412
413 if ((reg & 0x80) != 0) // msbit set
414 {
415 Flags = Flags | FLAG_N;
416 }
417 else
418 {
419 Flags = Flags & (0xFF - FLAG_N);
420 }
421}
422
423void set_flag_z(BYTE inReg) { // zero flag
424 BYTE reg;
425 reg = inReg;
426
427 if (reg == 0) {
428 Flags = Flags | FLAG_Z;
429 }
430 else
431 {
432 Flags = Flags & (0xFF - FLAG_Z);
433 }
434}
435
436void set_flag_v(BYTE in1, BYTE in2, BYTE out1) //overflow code.
437
438{
439 BYTE reg1in;
440 BYTE reg2in;
441 BYTE regOut;
442
443 reg1in = in1;
444 reg2in = in2;
445 regOut = out1;
446
447 if ((((reg1in & 0x80) == 0x80) && ((reg2in & 0x80) == 0x80) && ((regOut & 0x80) != 0x80)) //overflow
448 || (((reg1in & 0x80) != 0x80) && ((reg2in & 0x80) != 0x80) && ((regOut & 0x80) == 0x80))) //overflow
449 {
450 Flags = Flags | FLAG_V;
451 }
452 else
453 {
454 Flags = Flags & (0xFF - FLAG_V);
455 }
456}
457
458
459void Group_1(BYTE opcode)
460{
461 BYTE LB = 0;
462 BYTE HB = 0;
463 WORD address = 0;
464 WORD data = 0;
465 WORD temp_word = 0;
466 WORD offset;
467 WORD saved_flags = 0 ;
468
469 switch (opcode)
470 {
471 case 0x90: //LDA Immidiate
472 data = fetch();
473 Registers[REGISTER_A] = data;
474 set_flag_n(Registers[REGISTER_A]);
475 set_flag_z(Registers[REGISTER_A]);
476 break;
477
478
479 case 0xA0: //LDA abs
480 HB = fetch();
481 LB = fetch();
482 address += (WORD)((WORD)HB << 8) + LB; //moves High bite by 8 bits to make it 16bits
483 if (address >= 0 && address < MEMORY_SIZE) { //checking if smaller than memory size
484 Registers[REGISTER_A] = Memory[address]; // saving in register A (Accumulator)
485 }
486 set_flag_n(Registers[REGISTER_A]);
487 set_flag_z(Registers[REGISTER_A]);
488 break;
489
490 case 0xB0: //LDA abs,X
491 address += Index_Registers[REGISTER_X];
492 HB = fetch();
493 LB = fetch();
494 address += (WORD)((WORD)HB << 8) + LB; // WORD is a making sure that is a 16 bit number before we move it by 8bits
495 if (address >= 0 && address < MEMORY_SIZE) {
496 Registers[REGISTER_A] = Memory[address];
497 }
498 set_flag_n(Registers[REGISTER_A]);
499 set_flag_z(Registers[REGISTER_A]);
500 break;
501
502 case 0xC0: //LDA abs,Y
503 address += Index_Registers[REGISTER_Y];
504 HB = fetch();
505 LB = fetch();
506 address += (WORD)((WORD)HB << 8) + LB;
507 if (address >= 0 && address < MEMORY_SIZE) {
508 Registers[REGISTER_A] = Memory[address];
509 }
510 set_flag_n(Registers[REGISTER_A]);
511 set_flag_z(Registers[REGISTER_A]);
512 break;
513
514 case 0xD0:
515 //LDA abs,XY
516 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X]; //adding registers x and y
517 HB = fetch();
518 LB = fetch();
519 address += (WORD)((WORD)HB << 8) + LB;
520 if (address >= 0 && address < MEMORY_SIZE) {
521 Registers[REGISTER_A] = Memory[address];
522 }
523 set_flag_n(Registers[REGISTER_A]);
524 set_flag_z(Registers[REGISTER_A]);
525 break;
526
527 case 0xE0: //LDA indirect,XY
528 HB = fetch();
529 LB = fetch();
530 address = (WORD)((WORD)HB << 8) + LB;
531 HB = Memory[address]; // changes the HB
532 LB = Memory[address + 1]; // changes the LB
533 address = (WORD)((WORD)HB << 8) + LB;
534 address += Index_Registers[REGISTER_X];
535 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8);
536 if (address >= 0 && address < MEMORY_SIZE) {
537 Registers[REGISTER_A] = Memory[address];
538 }
539 set_flag_n(Registers[REGISTER_A]);
540 set_flag_z(Registers[REGISTER_A]);
541 break;
542
543 case 0x31: //LDX Immidiate
544 data = fetch();
545 Registers[REGISTER_X] = data;
546 set_flag_n(Registers[REGISTER_X]);
547 set_flag_z(Registers[REGISTER_X]);
548 break;
549
550 case 0x41: //LDX abs
551 HB = fetch();
552 LB = fetch();
553 address += (WORD)((WORD)HB << 8) + LB; //moves High bite by 8 bits to make it 16bits
554 if (address >= 0 && address < MEMORY_SIZE) { //checking if smaller than memory size
555 Registers[REGISTER_X] = Memory[address]; // saving in register A
556 }
557 set_flag_n(Registers[REGISTER_X]);
558 set_flag_z(Registers[REGISTER_X]);
559 break;
560
561 case 0x51: //LDX abs,X
562 address += Index_Registers[REGISTER_X];
563 HB = fetch();
564 LB = fetch();
565 address += (WORD)((WORD)HB << 8) + LB; // WORD is a making sure that is a 16 bit number before we move it by 8bits
566 if (address >= 0 && address < MEMORY_SIZE) {
567 Registers[REGISTER_X] = Memory[address];
568 }
569 set_flag_n(Registers[REGISTER_X]);
570 set_flag_z(Registers[REGISTER_X]);
571 break;
572
573 case 0x61: //LDX abs,Y
574 address += Index_Registers[REGISTER_X];
575 HB = fetch();
576 LB = fetch();
577 address += (WORD)((WORD)HB << 8) + LB;
578 if (address >= 0 && address < MEMORY_SIZE) {
579 Registers[REGISTER_X] = Memory[address];
580 }
581 set_flag_n(Registers[REGISTER_X]);
582 set_flag_z(Registers[REGISTER_X]);
583 break;
584
585 case 0x71: //LDX abs,XY
586 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X]; //adding registers x and y
587 HB = fetch();
588 LB = fetch();
589 address += (WORD)((WORD)HB << 8) + LB;
590 if (address >= 0 && address < MEMORY_SIZE) {
591 Registers[REGISTER_X] = Memory[address];
592 }
593 set_flag_n(Registers[REGISTER_X]);
594 set_flag_z(Registers[REGISTER_X]);
595 break;
596
597 case 0x81: //LDX indirect,XY
598 HB = fetch();
599 LB = fetch();
600 address = (WORD)((WORD)HB << 8) + LB;
601 HB = Memory[address]; // changes the HB
602 LB = Memory[address + 1]; // changes the LB
603 address = (WORD)((WORD)HB << 8) + LB;
604 address += Index_Registers[REGISTER_X];
605 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8);
606 if (address >= 0 && address < MEMORY_SIZE) {
607 Registers[REGISTER_X] = Memory[address];
608 }
609 set_flag_n(Registers[REGISTER_X]);
610 set_flag_z(Registers[REGISTER_X]);
611 break;
612
613 case 0x9B: //LX Loads Memory into register
614 data = fetch();
615 Registers[REGISTER_A] = data;
616 Registers[REGISTER_B] = data;
617 set_flag_n(Registers[REGISTER_A]);
618 set_flag_z(Registers[REGISTER_B]);
619 set_flag_n(Registers[REGISTER_B]);
620 set_flag_z(Registers[REGISTER_A]);
621 break;
622
623 case 0xAC: //STORE abs into A STO
624 HB = fetch();
625 LB = fetch();
626 address += (WORD)((WORD)HB << 8) + LB;
627 if (address >= 0 && address < MEMORY_SIZE) {
628 Memory[address] = Registers[REGISTER_A]; // Register is being stored into memory instead of memory into register A
629 }
630 set_flag_n(Memory[address]);
631 set_flag_z(Memory[address]);
632 break;
633
634 case 0xBC: //STORE abs,x into A STO
635 address += Index_Registers[REGISTER_X];
636 HB = fetch();
637 LB = fetch();
638 address += (WORD)((WORD)HB << 8) + LB;
639 if (address >= 0 && address < MEMORY_SIZE) {
640 Memory[address] = Registers[REGISTER_A];
641 }
642 set_flag_n(Memory[address]);
643 set_flag_z(Memory[address]);
644 break;
645
646 case 0xCC: //store abs,y into A STO
647 address += Index_Registers[REGISTER_Y];
648 HB = fetch();
649 LB = fetch();
650 address += (WORD)((WORD)HB << 8) + LB;
651 if (address >= 0 && address < MEMORY_SIZE) {
652 Memory[address] = Registers[REGISTER_A];
653 }
654 set_flag_n(Memory[address]);
655 set_flag_z(Memory[address]);
656 break;
657
658 case 0xDC: //store abs,XY into A STO
659 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
660 HB = fetch();
661 LB = fetch();
662 address += (WORD)((WORD)HB << 8) + LB;
663 if (address >= 0 && address < MEMORY_SIZE) {
664 Memory[address] = Registers[REGISTER_A];
665 }
666 set_flag_n(Memory[address]);
667 set_flag_z(Memory[address]);
668 break;
669
670 case 0xEC: //store ind,XY into A STO
671 HB = fetch();
672 LB = fetch();
673 address = (WORD)((WORD)HB << 8) + LB;
674 HB = Memory[address]; // changes the HB
675 LB = Memory[address + 1]; // changes the LB
676 address = (WORD)((WORD)HB << 8) + LB;
677 address += Index_Registers[REGISTER_X];
678 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8);
679 if (address >= 0 && address < MEMORY_SIZE) {
680 Memory[address] = Registers[REGISTER_A];
681 }
682 set_flag_n(Memory[address]);
683 set_flag_z(Memory[address]);
684 break;
685
686 case 0x02: //STORE abs into x STX
687 HB = fetch();
688 LB = fetch();
689 address += (WORD)((WORD)HB << 8) + LB;
690 if (address >= 0 && address < MEMORY_SIZE) {
691 Memory[address] = Registers[REGISTER_X]; // Register is being stored into memory instead of memory into register A
692 }
693 set_flag_n(Memory[address]);
694 set_flag_z(Memory[address]);
695 break;
696
697
698 case 0x12: //STORE abs,x into x STX
699 address += Index_Registers[REGISTER_X];
700 HB = fetch();
701 LB = fetch();
702 address += (WORD)((WORD)HB << 8) + LB;
703 if (address >= 0 && address < MEMORY_SIZE) {
704 Memory[address] = Registers[REGISTER_X];
705 }
706 set_flag_n(Memory[address]);
707 set_flag_z(Memory[address]);
708 break;
709
710 case 0x22: //store abs,y into x STX
711 address += Index_Registers[REGISTER_Y];
712 HB = fetch();
713 LB = fetch();
714 address += (WORD)((WORD)HB << 8) + LB;
715 if (address >= 0 && address < MEMORY_SIZE) {
716 Memory[address] = Registers[REGISTER_X];
717 }
718 set_flag_n(Memory[address]);
719 set_flag_z(Memory[address]);
720 break;
721
722 case 0x32: //store abs,XY into x STX
723 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
724 HB = fetch();
725 LB = fetch();
726 address += (WORD)((WORD)HB << 8) + LB;
727 if (address >= 0 && address < MEMORY_SIZE) {
728 Memory[address] = Registers[REGISTER_X];
729 }
730 set_flag_n(Memory[address]);
731 set_flag_z(Memory[address]);
732 break;
733
734 case 0x42: //store ind,XY into X STX
735 HB = fetch();
736 LB = fetch();
737 address = (WORD)((WORD)HB << 8) + LB;
738 HB = Memory[address]; // changes the HB
739 LB = Memory[address + 1]; // changes the LB
740 address = (WORD)((WORD)HB << 8) + LB;
741 address += Index_Registers[REGISTER_X];
742 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8);
743 if (address >= 0 && address < MEMORY_SIZE) {
744 Memory[address] = Registers[REGISTER_A];
745 }
746 set_flag_n(Memory[address]);
747 set_flag_z(Memory[address]);
748 break;
749
750 case 0x07: //Move immidiate for registerys MV B
751 data = fetch();
752 Registers[REGISTER_B] = data;
753 set_flag_n(Registers[REGISTER_B]);
754 set_flag_z(Registers[REGISTER_B]);
755 break;
756
757 case 0x08: //MV C
758 data = fetch();
759 Registers[REGISTER_C] = data;
760 set_flag_n(Registers[REGISTER_C]);
761 set_flag_z(Registers[REGISTER_C]);
762 break;
763
764 case 0x09: //MV D
765 data = fetch();
766 Registers[REGISTER_D] = data;
767 set_flag_n(Registers[REGISTER_D]);
768 set_flag_z(Registers[REGISTER_D]);
769 break;
770
771 case 0x0A: //MV E
772 data = fetch();
773 Registers[REGISTER_E] = data;
774 set_flag_n(Registers[REGISTER_E]);
775 set_flag_z(Registers[REGISTER_E]);
776 break;
777
778 case 0x0B: //MV F
779 data = fetch();
780 Registers[REGISTER_F] = data;
781 set_flag_n(Registers[REGISTER_F]);
782 set_flag_z(Registers[REGISTER_F]);
783 break;
784
785 case 0x9D: // LODS Immidiate
786 data = fetch();
787 StackPointer = data << 8; StackPointer += fetch();
788 set_flag_n((BYTE)data);
789 set_flag_z((BYTE)data);
790 break;
791
792 case 0xAD: // LODS abs
793 HB = fetch();
794 LB = fetch();
795 address += (WORD)((WORD)HB << 8) + LB;
796 if (address >= 0 && address < MEMORY_SIZE - 1) {
797 StackPointer = (WORD)Memory[address] << 8;
798 StackPointer += Memory[address + 1];
799 }
800 break;
801
802 case 0xBD: // LODS abs,x
803 address += Index_Registers[REGISTER_X];
804 HB = fetch();
805 LB = fetch();
806 address += (WORD)((WORD)HB << 8) + LB;
807 if (address >= 0 && address < MEMORY_SIZE - 1) {
808 StackPointer = (WORD)Memory[address] << 8;
809 StackPointer += Memory[address + 1];
810 }
811 break;
812
813 case 0xCD: // LODS abs,y
814 address += Index_Registers[REGISTER_Y];
815 HB = fetch();
816 LB = fetch();
817 address += (WORD)((WORD)HB << 8) + LB;
818 if (address >= 0 && address < MEMORY_SIZE - 1) {
819 StackPointer = (WORD)Memory[address] << 8;
820 StackPointer += Memory[address + 1];
821 }
822 break;
823
824 case 0xDD: //LODS abs,XY
825 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
826 HB = fetch();
827 LB = fetch();
828 address += (WORD)((WORD)HB << 8) + LB;
829 if (address >= 0 && address < MEMORY_SIZE - 1) {
830 StackPointer = (WORD)Memory[address] << 8;
831 StackPointer += Memory[address + 1];
832 }
833 break;
834
835 case 0xED: //lODS ind,XY
836 HB = fetch();
837 LB = fetch();
838 address = (WORD)((WORD)HB << 8) + LB;
839 HB = Memory[address]; // changes the HB
840 LB = Memory[address + 1]; // changes the LB
841 address = (WORD)((WORD)HB << 8) + LB;
842 address += Index_Registers[REGISTER_X];
843 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8);
844 if (address >= 0 && address < MEMORY_SIZE - 1) {
845 StackPointer = (WORD)Memory[address] << 8;
846 StackPointer += Memory[address + 1];
847 }
848 break;
849
850 case 0x18: //Clear the carry flag
851 Flags = Flags & (0xFF - FLAG_C);
852 set_flag_v == 0;
853 break;
854
855 case 0x19: //Set carry flag
856 Flags = Flags | FLAG_C;
857 set_flag_v(Flags, Flags | FLAG_C, (BYTE)Flags);
858 break;
859
860 case 0x1A: //Clear interupt flag
861 Flags = Flags & (0xFF - FLAG_I);
862 break;
863
864 case 0x1B: // Set Interupt flag
865 Flags = Flags | FLAG_I;
866 break;
867
868 case 0x1C: // Set Overflow Flag
869 Flags = Flags | FLAG_V;
870 break;
871
872 case 0x1D: // Clear Overflow Flag
873 Flags = Flags & (0xFF - FLAG_V);
874 set_flag_v == 0;
875 break;
876
877 //adding accumulator with the carry then stores in register
878 case 0x23: // ADD A-B
879 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_B];
880 if ((Flags & FLAG_C) != 0) {
881 temp_word++;
882 }
883 if (temp_word >= 0x100) { // checks the number to be less the 255
884 //set carry flag
885 Flags = Flags | FLAG_C; //Bitwise OR
886 }
887 else {
888 //clear carry flag
889 Flags = Flags & (0xFF - FLAG_C); // Bitwise AND, FF is 255 to make sure we have a carry number
890 }
891
892 set_flag_n((BYTE)temp_word);
893 set_flag_z((BYTE)temp_word);
894 set_flag_v(Registers[REGISTER_A], Registers[REGISTER_B], (BYTE)temp_word);
895 Registers[REGISTER_A] = (BYTE)temp_word;//stores into register A
896 break;
897
898 case 0x33: //ADD A-C
899 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_C];
900 if ((Flags & FLAG_C) != 0) {
901 temp_word++;
902 }
903 if (temp_word >= 0x100) { // checks the number to be less the 255
904 //set carry flag
905 Flags = Flags | FLAG_C; //Bitwise OR
906 }
907 else {
908 //clear carry flag
909 Flags = Flags & (0xFF - FLAG_C); // Bitwise AND, FF is 255 to make sure we have a carry number
910 }
911
912 set_flag_n((BYTE)temp_word);
913 set_flag_z((BYTE)temp_word);
914 set_flag_v(Registers[REGISTER_A], Registers[REGISTER_C], (BYTE)temp_word);
915 Registers[REGISTER_A] = (BYTE)temp_word; //stores into register A
916 break;
917
918 case 0x43: //ADD A-D
919 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_D];
920 if ((Flags & FLAG_C) != 0) {
921 temp_word++;
922 }
923 if (temp_word >= 0x100) { // checks the number to be less the 255
924 //set carry flag
925 Flags = Flags | FLAG_C; //Bitwise OR
926 }
927 else {
928 //clear carry flag
929 Flags = Flags & (0xFF - FLAG_C); // Bitwise AND, FF is 255 to make sure we have a carry number
930 }
931
932 set_flag_n((BYTE)temp_word);
933 set_flag_z((BYTE)temp_word);
934 set_flag_v(Registers[REGISTER_A], Registers[REGISTER_D], (BYTE)temp_word);
935 Registers[REGISTER_A] = (BYTE)temp_word; //stores into register A
936 break;
937
938 case 0x53: //ADD A-E
939 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_E];
940 if ((Flags & FLAG_C) != 0) {
941 temp_word++;
942 }
943 if (temp_word >= 0x100) { // checks the number to be less the 255
944 //set carry flag
945 Flags = Flags | FLAG_C; //Bitwise OR
946 }
947 else {
948 //clear carry flag
949 Flags = Flags & (0xFF - FLAG_C); // Bitwise AND, FF is 255 to make sure we have a carry number
950 }
951
952 set_flag_n((BYTE)temp_word);
953 set_flag_z((BYTE)temp_word);
954 set_flag_v(Registers[REGISTER_A], Registers[REGISTER_E], (BYTE)temp_word);
955 Registers[REGISTER_A] = (BYTE)temp_word; //stores into register A
956 break;
957
958 case 0x63: //ADD A-F
959 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_F];
960 if ((Flags & FLAG_C) != 0) {
961 temp_word++;
962 }
963 if (temp_word >= 0x100) { // checks the number to be less the 255
964 //set carry flag
965 Flags = Flags | FLAG_C; //Bitwise OR
966 }
967 else {
968 //clear carry flag
969 Flags = Flags & (0xFF - FLAG_C); // Bitwise AND, FF is 255 to make sure we have a carry number
970 }
971
972 set_flag_n((BYTE)temp_word);
973 set_flag_z((BYTE)temp_word);
974 set_flag_v(Registers[REGISTER_A], Registers[REGISTER_F], (BYTE)temp_word);
975 Registers[REGISTER_A] = (BYTE)temp_word; //stores into register A
976 break;
977
978 case 0x25: // compare A - B
979 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_B];
980 if (temp_word >= 0x100) { // checks the number to be less the 255
981 //set carry flag
982 Flags = Flags | FLAG_C; //Bitwise OR
983 }
984 else {
985 //clear carry flag
986 Flags = Flags & (0xFF - FLAG_C); // Bitwise AND, FF is 255 to make sure we have a carry number
987 }
988 set_flag_n((BYTE)temp_word);
989 set_flag_z((BYTE)temp_word);
990 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_B], (BYTE)temp_word);
991 break;
992
993 case 0x35: // compare A - C
994 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_C];
995 if (temp_word >= 0x100) { // checks the number to be less the 255
996 //set carry flag
997 Flags = Flags | FLAG_C; //Bitwise OR
998 }
999 else {
1000 //clear carry flag
1001 Flags = Flags & (0xFF - FLAG_C); // Bitwise AND, FF is 255 to make sure we have a carry number
1002 }
1003 set_flag_n((BYTE)temp_word);
1004 set_flag_z((BYTE)temp_word);
1005 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_C], (BYTE)temp_word);
1006 break;
1007
1008 case 0x45: // compare A - D
1009 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_D];
1010 if (temp_word >= 0x100) { // checks the number to be less the 255
1011 //set carry flag
1012 Flags = Flags | FLAG_C; //Bitwise OR
1013 }
1014 else {
1015 //clear carry flag
1016 Flags = Flags & (0xFF - FLAG_C); // Bitwise AND, FF is 255 to make sure we have a carry number
1017 }
1018 set_flag_n((BYTE)temp_word);
1019 set_flag_z((BYTE)temp_word);
1020 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_D], (BYTE)temp_word);
1021 break;
1022
1023 case 0x55: // compare A - E
1024 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_E];
1025 if (temp_word >= 0x100) { // checks the number to be less the 255
1026 //set carry flag
1027 Flags = Flags | FLAG_C; //Bitwise OR
1028 }
1029 else {
1030 //clear carry flag
1031 Flags = Flags & (0xFF - FLAG_C); // Bitwise AND, FF is 255 to make sure we have a carry number
1032 }
1033 set_flag_n((BYTE)temp_word);
1034 set_flag_z((BYTE)temp_word);
1035 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_E], (BYTE)temp_word);
1036 break;
1037
1038 case 0x65: // compare A - F
1039 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_F];
1040 if (temp_word >= 0x100) { // checks the number to be less the 255
1041 //set carry flag
1042 Flags = Flags | FLAG_C; //Bitwise OR
1043 }
1044 else {
1045 //clear carry flag
1046 Flags = Flags & (0xFF - FLAG_C); // Bitwise AND, FF is 255 to make sure we have a carry number
1047 }
1048 set_flag_n((BYTE)temp_word);
1049 set_flag_z((BYTE)temp_word);
1050 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_F], (BYTE)temp_word);
1051 break;
1052
1053 case 0x0F: //CSA
1054 Registers[REGISTER_A] = Flags;
1055 set_flag_n(Registers[REGISTER_A]);
1056 set_flag_z(Registers[REGISTER_A]);
1057 break;
1058
1059 case 0x0E: // MAS Transfers accumulator into status register
1060 Flags = Registers[REGISTER_A];
1061 break;
1062
1063 case 0x2A: // A - A
1064 Registers[REGISTER_A] = Registers[REGISTER_A];
1065 break;
1066 case 0x3A: // A - B
1067 Registers[REGISTER_B] = Registers[REGISTER_A];
1068 break;
1069 case 0x4A: // A - C
1070 Registers[REGISTER_C] = Registers[REGISTER_A];
1071 break;
1072 case 0x5A: // A - D
1073 Registers[REGISTER_D] = Registers[REGISTER_A];
1074 break;
1075 case 0x6A: // A - E
1076 Registers[REGISTER_E] = Registers[REGISTER_A];
1077 break;
1078 case 0x7A: // A - F
1079 Registers[REGISTER_F] = Registers[REGISTER_A];
1080 break;
1081 case 0x2B: // B - A
1082 Registers[REGISTER_A] = Registers[REGISTER_B];
1083 break;
1084 case 0x3B: // B - B
1085 Registers[REGISTER_B] = Registers[REGISTER_B];
1086 break;
1087 case 0x4B: // B - C
1088 Registers[REGISTER_C] = Registers[REGISTER_B];
1089 break;
1090 case 0x5B: // B - D
1091 Registers[REGISTER_D] = Registers[REGISTER_B];
1092 break;
1093 case 0x6B: // B - E
1094 Registers[REGISTER_E] = Registers[REGISTER_B];
1095 break;
1096 case 0x7B: // B - F
1097 Registers[REGISTER_F] = Registers[REGISTER_B];
1098 break;
1099 case 0x2C: // C - A
1100 Registers[REGISTER_A] = Registers[REGISTER_C];
1101 break;
1102 case 0x3C: // C - B
1103 Registers[REGISTER_B] = Registers[REGISTER_C];
1104 break;
1105 case 0x4C: // C - C
1106 Registers[REGISTER_C] = Registers[REGISTER_C];
1107 break;
1108 case 0x5C: // C - D
1109 Registers[REGISTER_D] = Registers[REGISTER_C];
1110 break;
1111 case 0x6C: // C - E
1112 Registers[REGISTER_E] = Registers[REGISTER_C];
1113 break;
1114 case 0x7C: // C - F
1115 Registers[REGISTER_F] = Registers[REGISTER_C];
1116 break;
1117 case 0x2D: // A - D
1118 Registers[REGISTER_A] = Registers[REGISTER_D];
1119 break;
1120 case 0x3D: // B - D
1121 Registers[REGISTER_B] = Registers[REGISTER_D];
1122 break;
1123 case 0x4D: // C - D
1124 Registers[REGISTER_C] = Registers[REGISTER_D];
1125 break;
1126 case 0x5D: // D - D
1127 Registers[REGISTER_D] = Registers[REGISTER_D];
1128 break;
1129 case 0x6D: // E - D
1130 Registers[REGISTER_E] = Registers[REGISTER_D];
1131 break;
1132 case 0x7D: // F - D
1133 Registers[REGISTER_F] = Registers[REGISTER_D];
1134 break;
1135 case 0x2E: // A - D
1136 Registers[REGISTER_A] = Registers[REGISTER_D];
1137 break;
1138 case 0x3E: // B - D
1139 Registers[REGISTER_B] = Registers[REGISTER_D];
1140 break;
1141 case 0x4E: // C - D
1142 Registers[REGISTER_C] = Registers[REGISTER_D];
1143 break;
1144 case 0x5E: // D - D
1145 Registers[REGISTER_D] = Registers[REGISTER_D];
1146 break;
1147 case 0x6E: // E - D
1148 Registers[REGISTER_E] = Registers[REGISTER_D];
1149 break;
1150 case 0x7E: // F - D
1151 Registers[REGISTER_F] = Registers[REGISTER_D];
1152 break;
1153 case 0x2F: // A - F
1154 Registers[REGISTER_A] = Registers[REGISTER_F];
1155 break;
1156 case 0x3F: // B - F
1157 Registers[REGISTER_B] = Registers[REGISTER_F];
1158 break;
1159 case 0x4F: // C - F
1160 Registers[REGISTER_C] = Registers[REGISTER_F];
1161 break;
1162 case 0x5F: // D - F
1163 Registers[REGISTER_D] = Registers[REGISTER_F];
1164 break;
1165 case 0x6F: // E - F
1166 Registers[REGISTER_E] = Registers[REGISTER_F];
1167 break;
1168 case 0x7F: // F - F
1169 Registers[REGISTER_F] = Registers[REGISTER_F];
1170 break;
1171
1172 case 0x0C: // MAY Storeing Accunmulator into Y
1173 Registers[REGISTER_Y] = Registers[REGISTER_A];
1174 set_flag_n(Registers[REGISTER_Y]);
1175 break;
1176
1177 case 0x0D: // MYA Storeing Y into Accumulator
1178 Registers[REGISTER_A] = Registers[REGISTER_Y];
1179 set_flag_n(Registers[REGISTER_A]);
1180 set_flag_z(Registers[REGISTER_A]);
1181 break;
1182
1183 case 0x9E: // PUSH MISSING MARK, REGISTER A
1184 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) { //starts at 1 else when we decrement it'd go past 0
1185 Memory[StackPointer] = Registers[REGISTER_A];
1186 StackPointer--; // decrement
1187 }
1188 break;
1189
1190 case 0xAE: // PUSH MISSING MARK, REGISTER FL
1191 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) { //starts at 1 else when we decrement it'd go past 0
1192 Memory[StackPointer] = Flags;
1193 StackPointer--; // decrement
1194 }
1195 break;
1196
1197 case 0xBE: // PUSH MISSING MARK, Register B
1198 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) { //starts at 1 else when we decrement it'd go past 0
1199 Memory[StackPointer] = Registers[REGISTER_B];
1200 StackPointer--; // decrement
1201 }
1202 break;
1203
1204 case 0xCE: // PUSH MISSING MARK, Register C
1205 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) { //starts at 1 else when we decrement it'd go past 0
1206 Memory[StackPointer] = Registers[REGISTER_C];
1207 StackPointer--; // decrement
1208 }
1209 break;
1210
1211 case 0xDE: // PUSH MISSING MARK, Register D
1212 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) { //starts at 1 else when we decrement it'd go past 0
1213 Memory[StackPointer] = Registers[REGISTER_D];
1214 StackPointer--; // decrement
1215 }
1216 break;
1217
1218 case 0xEE: // PUSH MISSING MARK, Register E
1219 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) { //starts at 1 else when we decrement it'd go past 0
1220 Memory[StackPointer] = Registers[REGISTER_E];
1221 StackPointer--; // decrement
1222 }
1223 break;
1224
1225 case 0xFE: // PUSH MISSING MARK, Register F
1226 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) { //starts at 1 else when we decrement it'd go past 0
1227 Memory[StackPointer] = Registers[REGISTER_F];
1228 StackPointer--; // decrement
1229 }
1230 break;
1231
1232 case 0x9F: //POP MISSING MARK, Register A
1233 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1234 StackPointer++; //increment
1235 Registers[REGISTER_A] = Memory[StackPointer];
1236 }
1237 break;
1238
1239 case 0xAF: //POP MISSING MARK, Register FL
1240 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1241 StackPointer++; //increment
1242 Flags = Memory[StackPointer];
1243 }
1244 break;
1245
1246 case 0xBF: //POP MISSING MARK, Register B
1247 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1248 StackPointer++; //increment
1249 Registers[REGISTER_B] = Memory[StackPointer];
1250 }
1251 break;
1252
1253 case 0xCF: //POP MISSING MARK, Register C
1254 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1255 StackPointer++; //increment
1256 Registers[REGISTER_C] = Memory[StackPointer];
1257 }
1258 break;
1259
1260 case 0xDF: //POP MISSING MARK, Register D
1261 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1262 StackPointer++; //increment
1263 Registers[REGISTER_D] = Memory[StackPointer];
1264 }
1265 break;
1266
1267 case 0xEF: //POP MISSING MARK, Register E
1268 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1269 StackPointer++; //increment
1270 Registers[REGISTER_E] = Memory[StackPointer];
1271 }
1272 break;
1273
1274 case 0xFF: //POP MISSING MARK, Register F
1275 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1276 StackPointer++; //increment
1277 Registers[REGISTER_F] = Memory[StackPointer];
1278 }
1279 break;
1280
1281 case 0xEA: //JMP abs
1282 HB = fetch();
1283 LB = fetch();
1284 address = ((WORD)HB << 8) + (WORD)LB;
1285 ProgramCounter = address;
1286 break;
1287
1288 case 0xE9: //JSR abs jump to sub routine
1289 if ((StackPointer >= 2) && (StackPointer < MEMORY_SIZE)) { //enogth memory to store address
1290 Memory[StackPointer] = (BYTE)(ProgramCounter & 0xFF); //storing a byte, taking lb
1291 StackPointer --;
1292 Memory[StackPointer] = (BYTE)((ProgramCounter >>8)& 0xFF);// moves hb by 8 bits and stores
1293 StackPointer --;
1294 }
1295 ProgramCounter = address;
1296 break;
1297
1298 case 0xDB: //RTN Return, opposite of JSR
1299
1300 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 2)) {
1301 StackPointer++;
1302 HB = Memory[StackPointer];
1303 StackPointer++;
1304 LB = Memory[StackPointer];
1305 ProgramCounter = ((WORD)HB << 8) + (WORD)LB;
1306 break;
1307 }
1308
1309 case 0xF0: //BRA Branch Always
1310 LB = fetch();
1311 offset = (WORD)LB;
1312 if ((offset & 0x80) != 0) { //need to sign extend
1313 offset = offset + 0xFF00;
1314 }
1315 address = ProgramCounter + offset;
1316 ProgramCounter = address;
1317 break;
1318
1319
1320 case 0xF1: //BCC Clear Carry
1321 LB = fetch();
1322 offset = (WORD)LB;
1323 if ((offset & 0x80) != 0) { //need to sign extend
1324 offset = offset + 0xFF00;
1325 }
1326 if ((Flags & FLAG_C) != FLAG_C) { //is carry flag set to 0
1327
1328 address = ProgramCounter + offset;
1329 ProgramCounter = address;
1330 }
1331
1332 break;
1333
1334 case 0xF2: //BCS Set carry
1335 LB = fetch();
1336 offset = (WORD)LB;
1337 if ((offset & 0x80) != 0) { //need to sign extend
1338 offset = offset + 0xFF00;
1339 }
1340 if ((Flags & FLAG_C) == FLAG_C) { //is carry flag set to
1341
1342 address = ProgramCounter + offset;
1343 ProgramCounter = address;
1344 }
1345
1346 break;
1347
1348 case 0xF3: //BNE Negative not zero
1349 LB = fetch();
1350 offset = (WORD)LB;
1351 if ((offset & 0x80) != 0) { //need to sign extend
1352 offset = offset + 0xFF00;
1353 }
1354 if ((Flags & FLAG_Z) != FLAG_Z) { // is negative flag not zero
1355
1356 address = ProgramCounter + offset;
1357 ProgramCounter = address;
1358 }
1359 break;
1360
1361 case 0xF4: //BEQ Negative Equal to zero
1362 LB = fetch();
1363 offset = (WORD)LB;
1364 if ((offset & 0x80) != 0) { //need to sign extend
1365 offset = offset + 0xFF00;
1366 }
1367 if ((Flags & FLAG_Z) == FLAG_Z) { //is zero flag equal to 0
1368
1369 address = ProgramCounter + offset;
1370 ProgramCounter = address;
1371 }
1372
1373 case 0xF5: //BVC, Overflow flag
1374 LB = fetch();
1375 offset = (WORD)LB;
1376 if ((offset & 0x80) != 0) { //need to sign extend
1377 offset = offset + 0xFF00;
1378 }
1379 if ((Flags & FLAG_V) != FLAG_V) { //is Overflow flag set to 0
1380
1381 address = ProgramCounter + offset;
1382 ProgramCounter = address;
1383 }
1384 break;
1385
1386 case 0xF6: //BVS, Overflow flag
1387 LB = fetch();
1388 offset = (WORD)LB;
1389 if ((offset & 0x80) != 0) { //need to sign extend
1390 offset = offset + 0xFF00;
1391 }
1392 if ((Flags & FLAG_V) == FLAG_V) { //is Overflow flag equal to 0
1393
1394 address = ProgramCounter + offset;
1395 ProgramCounter = address;
1396 }
1397 break;
1398
1399 case 0xF7: //BMI Negative Flag
1400 LB = fetch();
1401 offset = (WORD)LB;
1402 if ((offset & 0x80) != 0) { //need to sign extend
1403 offset = offset + 0xFF00;
1404 }
1405 if ((Flags & FLAG_N) == FLAG_N) { //is negative flag equal to 0
1406
1407 address = ProgramCounter + offset;
1408 ProgramCounter = address;
1409 }
1410 break;
1411
1412 case 0xF8: //BPL Negative Flag
1413 LB = fetch();
1414 offset = (WORD)LB;
1415 if ((offset & 0x80) != 0) { //need to sign extend
1416 offset = offset + 0xFF00;
1417 }
1418 if ((Flags & FLAG_N) != FLAG_N) { //is negative flag equal to 0
1419
1420 address = ProgramCounter + offset;
1421 ProgramCounter = address;
1422 }
1423 break;
1424
1425 case 0xF9: // BGE Less than or equal too
1426 LB = fetch();
1427 offset = (WORD)LB;
1428 if ((offset & 0x80) != 0) { //need to sign extend
1429 offset = offset + 0xFF00;
1430 }
1431 if (((Flags & FLAG_Z) == FLAG_Z) | (Flags & FLAG_N) == FLAG_N) { //Is Negative flag = to 0 or is Zero flag equal to 0
1432
1433 address = ProgramCounter + offset;
1434 ProgramCounter = address;
1435 }
1436 break;
1437
1438 case 0xFA: // BLE Less than or equal too
1439 LB = fetch();
1440 offset = (WORD)LB;
1441 if ((offset & 0x80) != 0) { //need to sign extend
1442 offset = offset + 0xFF00;
1443 }
1444 if (((Flags & FLAG_Z) == FLAG_Z) | (Flags & FLAG_N) != FLAG_N) { //Is Negative flag = to 0 or is Zero flag equal to 0
1445
1446 address = ProgramCounter + offset;
1447 ProgramCounter = address;
1448 }
1449 break;
1450
1451 case 0xFB: // BGT Less than or equal too
1452 LB = fetch();
1453 offset = (WORD)LB;
1454 if ((offset & 0x80) != 0) { //need to sign extend
1455 offset = offset + 0xFF00;
1456 }
1457 if (((Flags & FLAG_Z) == FLAG_Z) | (Flags & FLAG_N) != FLAG_N) { //Is Negative flag = to 0 or is Zero flag equal to 0
1458
1459 address = ProgramCounter + offset;
1460 ProgramCounter = address;
1461 }
1462 break;
1463
1464 case 0xFC: // BLT Greater than or equal too
1465 LB = fetch();
1466 offset = (WORD)LB;
1467 if ((offset & 0x80) != 0) { //need to sign extend
1468 offset = offset + 0xFF00;
1469 }
1470 if (((Flags & FLAG_Z) == FLAG_Z) | (Flags & FLAG_N) != FLAG_N) { //Is Negative flag = to 0 or is Zero flag equal to 0
1471
1472 address = ProgramCounter + offset;
1473 ProgramCounter = address;
1474 }
1475 break;
1476
1477
1478 case 0xD2: // INCA, Increment
1479
1480 ++Registers[REGISTER_A];
1481
1482 set_flag_n(Registers[REGISTER_A]);
1483 set_flag_z(Registers[REGISTER_A]);
1484 break;
1485
1486 case 0x93: //DEC abs
1487 HB = fetch();
1488 LB = fetch();
1489 address += (WORD)((WORD)HB << 8) + LB;
1490 --Memory[address];
1491 set_flag_n(Memory[address]);
1492 set_flag_z(Memory[address]);
1493 break;
1494
1495 case 0xA3: //DEC abs X
1496 address += Index_Registers[REGISTER_X];
1497 HB = fetch();
1498 LB = fetch();
1499 address += (WORD)((WORD)HB << 8) + LB;
1500 --Memory[address];
1501 set_flag_n(Memory[address]);
1502 set_flag_z(Memory[address]);
1503 break;
1504
1505 case 0xB3: //DEC abs Y
1506 address += Index_Registers[REGISTER_Y];
1507 HB = fetch();
1508 LB = fetch();
1509 address += (WORD)((WORD)HB << 8) + LB;
1510 --Memory[address];
1511 set_flag_n(Memory[address]);
1512 set_flag_z(Memory[address]);
1513 break;
1514
1515 case 0xC3: //DEC abs XY
1516 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1517 HB = fetch();
1518 LB = fetch();
1519 address += (WORD)((WORD)HB << 8) + LB;
1520 --Memory[address];
1521 set_flag_n(Memory[address]);
1522 set_flag_z(Memory[address]);
1523 break;
1524
1525 case 0xD3: // DECA, Decrement
1526
1527 --Registers[REGISTER_A];
1528
1529 set_flag_n(Registers[REGISTER_A]);
1530 set_flag_z(Registers[REGISTER_A]);
1531 break;
1532
1533 case 0xE1: // DEX
1534 --Registers[REGISTER_X];
1535
1536 set_flag_z(Registers[REGISTER_X]);
1537 break;
1538
1539 case 0xE2: //INX
1540 ++Index_Registers[REGISTER_X];
1541
1542 set_flag_z(Index_Registers[REGISTER_X]);
1543 break;
1544
1545 case 0xE3: //DEY
1546 --Index_Registers[REGISTER_Y];
1547
1548 set_flag_z(Index_Registers[REGISTER_Y]);
1549 break;
1550
1551 case 0xE4: //INCY
1552 ++Index_Registers[REGISTER_Y];
1553
1554 set_flag_z(Index_Registers[REGISTER_Y]);
1555 break;
1556
1557 case 0x29: //BT A-B
1558 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_B];
1559
1560 set_flag_n((BYTE)temp_word);
1561 set_flag_z((BYTE)temp_word);
1562
1563 Flags = Flags & (0xFF - FLAG_V);
1564 break;
1565
1566 case 0x39: //BT A-C
1567 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_C];
1568
1569 set_flag_n((BYTE)temp_word);
1570 set_flag_z((BYTE)temp_word);
1571
1572 Flags = Flags & (0xFF - FLAG_V);
1573 break;
1574 case 0x49: // BT A-D
1575 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_D];
1576
1577 set_flag_n((BYTE)temp_word);
1578 set_flag_z((BYTE)temp_word);
1579
1580 Flags = Flags & (0xFF - FLAG_V);
1581
1582 break;
1583 case 0x59: // BT A-E
1584 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_E];
1585
1586 set_flag_n((BYTE)temp_word);
1587 set_flag_z((BYTE)temp_word);
1588
1589 Flags = Flags & (0xFF - FLAG_V);
1590
1591 break;
1592 case 0x69: // BT A-F
1593 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_F];
1594
1595 set_flag_n((BYTE)temp_word);
1596 set_flag_z((BYTE)temp_word);
1597
1598 Flags = Flags & (0xFF - FLAG_V);
1599
1600 break;
1601 case 0x24: //SUBTRACT A-B
1602 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_B];
1603 if ((Flags & FLAG_C) != 0) {
1604 temp_word--;
1605 }
1606 if (temp_word >= 0x100) {// checks the number to be less the 255
1607 //set carry flag
1608 Flags = Flags | FLAG_C;//Bitwise OR
1609 }
1610 else {
1611
1612 Flags = Flags & (0xFF - FLAG_C);// Bitwise AND, FF is 255 to make sure we have a carry number
1613 }
1614 //sets or clears affected flags
1615 set_flag_n((BYTE)temp_word);
1616 set_flag_z((BYTE)temp_word);
1617 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_B], (BYTE)temp_word);
1618 Registers[REGISTER_A] = (BYTE)temp_word;
1619 break;
1620
1621
1622 case 0x34: //SUBTRACT A-C
1623 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_C];
1624 if ((Flags & FLAG_C) != 0) {
1625 temp_word--;
1626 }
1627 if (temp_word >= 0x100) {// checks the number to be less the 255
1628 //set carry flag
1629 Flags = Flags | FLAG_C;//Bitwise OR
1630 }
1631 else {
1632
1633 Flags = Flags & (0xFF - FLAG_C);// Bitwise AND, FF is 255 to make sure we have a carry number
1634 }
1635 //sets or clears affected flags
1636 set_flag_n((BYTE)temp_word);
1637 set_flag_z((BYTE)temp_word);
1638 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_C], (BYTE)temp_word);
1639 Registers[REGISTER_A] = (BYTE)temp_word;
1640 break;
1641
1642 case 0x44: //SUBTRACT A-B
1643 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_D];
1644 if ((Flags & FLAG_C) != 0) {
1645 temp_word--;
1646 }
1647 if (temp_word >= 0x100) {// checks the number to be less the 255
1648 //set carry flag
1649 Flags = Flags | FLAG_C;//Bitwise OR
1650 }
1651 else {
1652
1653 Flags = Flags & (0xFF - FLAG_C);// Bitwise AND, FF is 255 to make sure we have a carry number
1654 }
1655 //sets or clears affected flags
1656 set_flag_n((BYTE)temp_word);
1657 set_flag_z((BYTE)temp_word);
1658 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_D], (BYTE)temp_word);
1659 Registers[REGISTER_A] = (BYTE)temp_word;
1660 break;
1661
1662 case 0x54: //SUBTRACT A-E
1663 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_E];
1664 if ((Flags & FLAG_C) != 0) {
1665 temp_word--;
1666 }
1667 if (temp_word >= 0x100) {// checks the number to be less the 255
1668 //set carry flag
1669 Flags = Flags | FLAG_C;//Bitwise OR
1670 }
1671 else {
1672
1673 Flags = Flags & (0xFF - FLAG_C);// Bitwise AND, FF is 255 to make sure we have a carry number
1674 }
1675 //sets or clears affected flags
1676 set_flag_n((BYTE)temp_word);
1677 set_flag_z((BYTE)temp_word);
1678 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_E], (BYTE)temp_word);
1679 Registers[REGISTER_A] = (BYTE)temp_word;
1680 break;
1681
1682 case 0x64: //SUBTRACT A-F
1683 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_F];
1684 if ((Flags & FLAG_C) != 0) {
1685 temp_word--;
1686 }
1687 if (temp_word >= 0x100) {// checks the number to be less the 255
1688 //set carry flag
1689 Flags = Flags | FLAG_C;//Bitwise OR
1690 }
1691 else {
1692
1693 Flags = Flags & (0xFF - FLAG_C);// Bitwise AND, FF is 255 to make sure we have a carry number
1694 }
1695 //sets or clears affected flags
1696 set_flag_n((BYTE)temp_word);
1697 set_flag_z((BYTE)temp_word);
1698 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_F], (BYTE)temp_word);
1699 Registers[REGISTER_A] = (BYTE)temp_word;
1700 break;
1701
1702 case 0x95: //RLC Absolute
1703 {
1704 HB = fetch();
1705 LB = fetch();
1706 address = ((WORD)HB << 8) + LB;
1707 BYTE temp_byte = (Memory[address] << 1) & 0xFE;
1708
1709 if (address >= 0 && address < MEMORY_SIZE) {
1710 if ((Flags & FLAG_C) == FLAG_C) {
1711 temp_byte = temp_byte | 0x1;
1712 }
1713 }
1714
1715 if ((Memory[address] & 0x80) == 0x80) {
1716 Flags |= FLAG_C;
1717 }
1718 else {
1719 Flags &= (0xFF - FLAG_C);
1720 }
1721 set_flag_n(temp_byte);
1722 set_flag_z(temp_byte);
1723 Memory[address] = temp_byte;
1724 }
1725 break;
1726
1727 case 0xA5: //RLC Absolute X
1728 {
1729 address += Index_Registers[REGISTER_X];
1730 HB = fetch();
1731 LB = fetch();
1732 address = ((WORD)HB << 8) + LB;
1733 BYTE temp_byte = (Memory[address] << 1) & 0xFE;
1734
1735 if (address >= 0 && address < MEMORY_SIZE) {
1736 if ((Flags & FLAG_C) == FLAG_C) {
1737 temp_byte = temp_byte | 0x1;
1738 }
1739 }
1740
1741 if ((Memory[address] & 0x80) == 0x80) {
1742 Flags |= FLAG_C;
1743 }
1744 else {
1745 Flags &= (0xFF - FLAG_C);
1746 }
1747 set_flag_n(temp_byte);
1748 set_flag_z(temp_byte);
1749 Memory[address] = temp_byte;
1750 }
1751 break;
1752
1753 case 0xB5: //RLC Absolute Y
1754 {
1755 address += Index_Registers[REGISTER_Y];
1756 HB = fetch();
1757 LB = fetch();
1758 address = ((WORD)HB << 8) + LB;
1759 BYTE temp_byte = (Memory[address] << 1) & 0xFE;
1760
1761 if (address >= 0 && address < MEMORY_SIZE) {
1762 if ((Flags & FLAG_C) == FLAG_C) {
1763 temp_byte = temp_byte | 0x1;
1764 }
1765 }
1766
1767 if ((Memory[address] & 0x80) == 0x80) {
1768 Flags |= FLAG_C;
1769 }
1770 else {
1771 Flags &= (0xFF - FLAG_C);
1772 }
1773 set_flag_n(temp_byte);
1774 set_flag_z(temp_byte);
1775 Memory[address] = temp_byte;
1776 }
1777 break;
1778
1779 case 0xC5: //RLC Absolute XY
1780 {
1781 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1782 HB = fetch();
1783 LB = fetch();
1784 address = ((WORD)HB << 8) + LB;
1785 BYTE temp_byte = (Memory[address] << 1) & 0xFE;
1786
1787 if (address >= 0 && address < MEMORY_SIZE) {
1788 if ((Flags & FLAG_C) == FLAG_C) {
1789 temp_byte = temp_byte | 0x1;
1790 }
1791 }
1792
1793 if ((Memory[address] & 0x80) == 0x80) {
1794 Flags |= FLAG_C;
1795 }
1796 else {
1797 Flags &= (0xFF - FLAG_C);
1798 }
1799 set_flag_n(temp_byte);
1800 set_flag_z(temp_byte);
1801 Memory[address] = temp_byte;
1802 }
1803 break;
1804
1805 case 0xD5: //RLCA Addresing A
1806 saved_flags = Flags;
1807
1808 if ((Registers[REGISTER_A] & 0x80) == 0x80) { //checks 8th bit and sets carry
1809 Flags = Flags | FLAG_C;
1810 }
1811 else {
1812 Flags = Flags & (0xFF - FLAG_C);
1813 }
1814
1815 Registers[REGISTER_A] = (Registers[REGISTER_A] << 1) & 0xFE;
1816
1817 if ((saved_flags & FLAG_C) == FLAG_C) {
1818 Registers[REGISTER_A] = Registers[REGISTER_A] | 0x01;
1819 }
1820 set_flag_n((BYTE)temp_word);
1821 set_flag_z((BYTE)temp_word);
1822 break;
1823
1824 case 0xD4: //RCRA
1825 saved_flags = Flags;
1826 if ((Registers[REGISTER_A] & 0x01) == 0x01) {
1827 Flags = Flags | FLAG_C;
1828 }
1829 else {
1830 Flags = Flags & (0xFF - FLAG_C);
1831 }
1832
1833 Registers[REGISTER_A] = (Registers[REGISTER_A] >> 1) & 0x7F;
1834 if ((saved_flags & FLAG_C) == FLAG_C) {
1835 Registers[REGISTER_A] = Registers[REGISTER_A] | 0x80;
1836 }
1837 set_flag_z(Registers[REGISTER_A]);
1838 set_flag_n(Registers[REGISTER_A]);
1839 break;
1840
1841 case 0xD6: // ASLA
1842 saved_flags = Flags;
1843 if ((Registers[REGISTER_A] & 0x80) == 0x80) {
1844 Flags = Flags | FLAG_C;
1845 }
1846 else {
1847 Flags = Flags & (0xFF - FLAG_C);
1848 }
1849 Registers[REGISTER_A] = (Registers[REGISTER_A] << 1) & 0xFE;
1850
1851 set_flag_z(Registers[REGISTER_A]);
1852 set_flag_n(Registers[REGISTER_A]);
1853 break;
1854
1855 case 0x97: //SAR ABS
1856 HB = fetch();
1857 LB = fetch();
1858 address += (WORD)((WORD)HB << 8) + LB;
1859 if ((Memory[address] & 0x01) == 0x01) {
1860 Flags = Flags | FLAG_C;
1861 }
1862 else {
1863 Flags = Flags & (0xFF - FLAG_C);
1864 }
1865
1866 if (address >= 0 && address < MEMORY_SIZE) {
1867 Memory[address] = (Memory[address] >> 1) & 0x7F;
1868 }
1869 if ((Flags & FLAG_N) == FLAG_N) {
1870 Memory[address] = Memory[address] | 0x80;
1871 }
1872 set_flag_c(Registers[REGISTER_A]);
1873 set_flag_z(Registers[REGISTER_A]);
1874 set_flag_n(Registers[REGISTER_A]);
1875 break;
1876
1877 case 0xA7: //SAR ABS,X
1878 address += Index_Registers[REGISTER_X];
1879 HB = fetch();
1880 LB = fetch();
1881 address += (WORD)((WORD)HB << 8) + LB;
1882 if ((Memory[address] & 0x01) == 0x01) {
1883 Flags = Flags | FLAG_C;
1884 }
1885 else {
1886 Flags = Flags & (0xFF - FLAG_C);
1887 }
1888
1889 if (address >= 0 && address < MEMORY_SIZE) {
1890 Memory[address] = (Memory[address] >> 1) & 0x7F;
1891 }
1892 if ((Flags & FLAG_N) == FLAG_N) {
1893 Memory[address] = Memory[address] | 0x80;
1894 }
1895 set_flag_c(Registers[REGISTER_X]);
1896 set_flag_z(Registers[REGISTER_X]);
1897 set_flag_n(Registers[REGISTER_X]);
1898 break;
1899
1900 case 0xB7: //SAR ABS,Y
1901 address += Index_Registers[REGISTER_Y];
1902 HB = fetch();
1903 LB = fetch();
1904 address += (WORD)((WORD)HB << 8) + LB;
1905 if ((Memory[address] & 0x01) == 0x01) {
1906 Flags = Flags | FLAG_C;
1907 }
1908 else {
1909 Flags = Flags & (0xFF - FLAG_C);
1910 }
1911
1912 if (address >= 0 && address < MEMORY_SIZE) {
1913 Memory[address] = (Memory[address] >> 1) & 0x7F;
1914 }
1915 if ((Flags & FLAG_N) == FLAG_N) {
1916 Memory[address] = Memory[address] | 0x80;
1917 }
1918 set_flag_c(Registers[REGISTER_Y]);
1919 set_flag_z(Registers[REGISTER_Y]);
1920 set_flag_n(Registers[REGISTER_Y]);
1921 break;
1922
1923 case 0xC7: //SAR ABS,XY
1924 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1925 HB = fetch();
1926 LB = fetch();
1927 address += (WORD)((WORD)HB << 8) + LB;
1928 if ((Memory[address] & 0x01) == 0x01) {
1929 Flags = Flags | FLAG_C;
1930 }
1931 else {
1932 Flags = Flags & (0xFF - FLAG_C);
1933 }
1934
1935 if (address >= 0 && address < MEMORY_SIZE) {
1936 Memory[address] = (Memory[address] >> 1) & 0x7F;
1937 }
1938 if ((Flags & FLAG_N) == FLAG_N) {
1939 Memory[address] = Memory[address] | 0x80;
1940 }
1941 set_flag_c(Registers[REGISTER_X]);
1942 set_flag_z(Registers[REGISTER_X]);
1943 set_flag_n(Registers[REGISTER_X]);
1944 break;
1945
1946 case 0xD7: //SARA
1947 saved_flags = Flags;
1948
1949 if ((Registers[REGISTER_A] & 0x01) == 0x01) { //checks value of first bit and sets carry
1950 Flags = Flags | FLAG_C;
1951 }
1952 else {
1953 Flags = Flags & (0xFF - FLAG_C);
1954 }
1955 break;
1956
1957 case 0xD9: //RALA Check if correct
1958 Registers[REGISTER_A] = (Registers[REGISTER_A] << 1) & 0xFE;
1959
1960 if ((saved_flags & FLAG_C) == FLAG_C) {
1961 Registers[REGISTER_A] = Registers[REGISTER_A] | 0x01;
1962 }
1963 set_flag_n((BYTE)temp_word);
1964 set_flag_z((BYTE)temp_word);
1965 break;
1966
1967 case 0xDA: // RORA Check if correct
1968 Registers[REGISTER_A] = (Registers[REGISTER_A] << 1) & 0x01;
1969
1970 if ((saved_flags & FLAG_C) == FLAG_C) {
1971 Registers[REGISTER_A] = Registers[REGISTER_A] | 0x01;
1972 }
1973 set_flag_n((BYTE)temp_word);
1974 set_flag_z((BYTE)temp_word);
1975 break;
1976
1977 break;
1978
1979 case 0xD8: //COMA INCOMPLETE
1980
1981 set_flag_n((BYTE)temp_word);
1982 set_flag_z((BYTE)temp_word);
1983 break;
1984
1985 case 0x98: //COM - Negates Memory or Accumulator
1986 HB = fetch();
1987 LB = fetch();
1988 address = ((WORD)HB << 8) + LB;
1989
1990 if (address >= 0 && address < MEMORY_SIZE) {
1991 temp_word = ~Memory[address];
1992 if (temp_word >= 0x100) {
1993 Flags = Flags | FLAG_C; // Set Carry Flag
1994 }
1995 else {
1996 Flags = Flags & (0xFF - FLAG_C); // Clear Carry Flag
1997 }
1998 set_flag_z((BYTE)temp_word);
1999 set_flag_n((BYTE)temp_word);
2000 Memory[address] = (BYTE)temp_word;
2001 }
2002 break;
2003
2004 case 0xA8: //COM Absolute X
2005 address += Index_Registers[REGISTER_X];
2006 HB = fetch();
2007 LB = fetch();
2008 address = ((WORD)HB << 8) + LB;
2009
2010 if (address >= 0 && address < MEMORY_SIZE) {
2011 temp_word = ~Memory[address];
2012 if (temp_word >= 0x100) {
2013 Flags = Flags | FLAG_C; // Set Carry Flag
2014 }
2015 else {
2016 Flags = Flags & (0xFF - FLAG_C); // Clear Carry Flag
2017 }
2018 set_flag_z((BYTE)temp_word);
2019 set_flag_n((BYTE)temp_word);
2020 Memory[address] = (BYTE)temp_word;
2021 }
2022 break;
2023
2024 case 0xB8: //COM Absolute Y
2025 address += Index_Registers[REGISTER_Y];
2026 HB = fetch();
2027 LB = fetch();
2028 address = ((WORD)HB << 8) + LB;
2029
2030 if (address >= 0 && address < MEMORY_SIZE) {
2031 temp_word = ~Memory[address];
2032 if (temp_word >= 0x100) {
2033 Flags = Flags | FLAG_C; // Set Carry Flag
2034 }
2035 else {
2036 Flags = Flags & (0xFF - FLAG_C); // Clear Carry Flag
2037 }
2038 set_flag_z((BYTE)temp_word);
2039 set_flag_n((BYTE)temp_word);
2040 Memory[address] = (BYTE)temp_word;
2041 }
2042 break;
2043
2044 case 0xC8: //COM Absolute X, Y
2045 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2046 HB = fetch();
2047 LB = fetch();
2048 address = ((WORD)HB << 8) + LB;
2049
2050 if (address >= 0 && address < MEMORY_SIZE) {
2051 temp_word = ~Memory[address];
2052 if (temp_word >= 0x100) {
2053 Flags = Flags | FLAG_C; // Set Carry Flag
2054 }
2055 else {
2056 Flags = Flags & (0xFF - FLAG_C); // Clear Carry Flag
2057 }
2058 set_flag_z((BYTE)temp_word);
2059 set_flag_n((BYTE)temp_word);
2060 Memory[address] = (BYTE)temp_word;
2061 }
2062 break;
2063
2064 case 0x26: //OR (A-B)
2065 temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_B];
2066 set_flag_n((BYTE)temp_word);
2067 set_flag_z((BYTE)temp_word);
2068 Flags = Flags & (0xFF - FLAG_V);
2069 Registers[REGISTER_A] = (BYTE)temp_word;
2070 break;
2071
2072 case 0x36: //OR (A-C)
2073 temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_C];
2074 set_flag_n((BYTE)temp_word);
2075 set_flag_z((BYTE)temp_word);
2076 Flags = Flags & (0xFF - FLAG_V);
2077 Registers[REGISTER_A] = (BYTE)temp_word;
2078 break;
2079
2080 case 0x46: //OR (A-D)
2081 temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_D];
2082 set_flag_n((BYTE)temp_word);
2083 set_flag_z((BYTE)temp_word);
2084 Flags = Flags & (0xFF - FLAG_V);
2085 Registers[REGISTER_A] = (BYTE)temp_word;
2086 break;
2087
2088 case 0x56: //OR (A-E)
2089 temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_E];
2090 set_flag_n((BYTE)temp_word);
2091 set_flag_z((BYTE)temp_word);
2092 Flags = Flags & (0xFF - FLAG_V);
2093 Registers[REGISTER_A] = (BYTE)temp_word;
2094 break;
2095
2096 case 0x66: //OR (A-F)
2097 temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_F];
2098 set_flag_n((BYTE)temp_word);
2099 set_flag_z((BYTE)temp_word);
2100 Flags = Flags & (0xFF - FLAG_V);
2101 Registers[REGISTER_A] = (BYTE)temp_word;
2102 break;
2103
2104 case 0x28: //EOR A-B
2105 temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_B];
2106
2107 set_flag_n((BYTE)temp_word);
2108 set_flag_z((BYTE)temp_word);
2109
2110 Flags = Flags & (0xFF - FLAG_V);
2111 Registers[REGISTER_A] = (BYTE)temp_word;
2112 break;
2113
2114 case 0x38: // EOR A-C
2115
2116 temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_C];
2117
2118 set_flag_n((BYTE)temp_word);
2119 set_flag_z((BYTE)temp_word);
2120
2121 Flags = Flags & (0xFF - FLAG_V);
2122 Registers[REGISTER_A] = (BYTE)temp_word;
2123 break;
2124
2125 case 0x48: //EOR A-D
2126
2127 temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_D];
2128
2129 set_flag_n((BYTE)temp_word);
2130 set_flag_z((BYTE)temp_word);
2131
2132 Flags = Flags & (0xFF - FLAG_V);
2133 Registers[REGISTER_A] = (BYTE)temp_word;
2134 break;
2135
2136 case 0x58: //EOR A-E
2137
2138 temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_E];
2139
2140 set_flag_n((BYTE)temp_word);
2141 set_flag_z((BYTE)temp_word);
2142
2143 Flags = Flags & (0xFF - FLAG_V);
2144 Registers[REGISTER_A] = (BYTE)temp_word;
2145 break;
2146
2147 case 0x68: //EOR A-F
2148
2149 temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_F];
2150
2151 set_flag_n((BYTE)temp_word);
2152 set_flag_z((BYTE)temp_word);
2153
2154 Flags = Flags & (0xFF - FLAG_V);
2155 Registers[REGISTER_A] = (BYTE)temp_word;
2156 break;
2157
2158 case 0x27: // logical AND A-B
2159
2160 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_B];
2161
2162 set_flag_n((BYTE)temp_word);
2163 set_flag_z((BYTE)temp_word);
2164
2165
2166 Registers[REGISTER_A] = (BYTE)temp_word;
2167 Flags = Flags & (0xFF - FLAG_V);
2168 break;
2169
2170 case 0x37: // logical AND A-C
2171
2172 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_C];
2173
2174 set_flag_n((BYTE)temp_word);
2175 set_flag_z((BYTE)temp_word);
2176
2177
2178 Registers[REGISTER_A] = (BYTE)temp_word;
2179 Flags = Flags & (0xFF - FLAG_V);
2180 break;
2181
2182 case 0x47: // logical AND A-D
2183
2184 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_D];
2185
2186 set_flag_n((BYTE)temp_word);
2187 set_flag_z((BYTE)temp_word);
2188
2189
2190 Registers[REGISTER_A] = (BYTE)temp_word;
2191 Flags = Flags & (0xFF - FLAG_V);
2192 break;
2193
2194 case 0x57: // logical AND A-E
2195
2196 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_E];
2197
2198 set_flag_n((BYTE)temp_word);
2199 set_flag_z((BYTE)temp_word);
2200
2201 Registers[REGISTER_A] = (BYTE)temp_word;
2202 Flags = Flags & (0xFF - FLAG_V);
2203 break;
2204
2205 case 0x67: // logical AND A-F
2206
2207 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_F];
2208
2209 set_flag_n((BYTE)temp_word);
2210 set_flag_z((BYTE)temp_word);
2211
2212
2213 Registers[REGISTER_A] = (BYTE)temp_word;
2214 Flags = Flags & (0xFF - FLAG_V);
2215 break;
2216
2217 }
2218}
2219
2220
2221void Group_2_Move(BYTE opcode)
2222
2223{
2224 ///////////////////////////////////////////////////////////// LD ///////////////////////////////////////////////////
2225
2226 BYTE destination = opcode >> 4; //top four bits point at one register....shift right to keep only top four
2227 BYTE source = opcode & 0x0F;//takes bottom four bits
2228
2229 int destReg = 0;
2230 int sourceReg = 0;
2231
2232 switch (destination)//COMBO OF DEST AND SOURCE GIVE REGISTERS ADDRESSES TO FOR MEMORY ADRESSER AT BOTTOMM
2233 {
2234 case 0x02://top four bits from op code
2235 destReg = REGISTER_A;
2236 break;
2237
2238 case 0x03:
2239 destReg = REGISTER_B;
2240 break;
2241
2242 case 0x04:
2243 destReg = REGISTER_C;
2244 break;
2245
2246 case 0x05:
2247 destReg = REGISTER_D;
2248 break;
2249
2250 case 0x06:
2251 destReg = REGISTER_E;
2252 break;
2253
2254 case 0x07:
2255 destReg = REGISTER_F;
2256 break;
2257
2258 }
2259
2260 switch (source)
2261 {
2262
2263 case 0x0A:
2264 sourceReg = REGISTER_A;
2265 break;
2266
2267 case 0x0B:
2268 sourceReg = REGISTER_B;
2269 break;
2270
2271 case 0x0C:
2272 sourceReg = REGISTER_C;
2273 break;
2274
2275 case 0x0D:
2276 sourceReg = REGISTER_D;
2277 break;
2278
2279 case 0x0E:
2280 sourceReg = REGISTER_E;
2281 break;
2282
2283 case 0x0F:
2284 sourceReg = REGISTER_F;
2285 break;
2286 }
2287 Registers[sourceReg] = Registers[destReg];//code to assign sourcereg to dest reg
2288}
2289
2290
2291
2292
2293void execute(BYTE opcode)
2294{
2295 if (((opcode >= 0x2A) && (opcode <= 0x2F))
2296 || ((opcode >= 0x3A) && (opcode <= 0x3F))
2297 || ((opcode >= 0x4A) && (opcode <= 0x4F))
2298 || ((opcode >= 0x5A) && (opcode <= 0x5F))
2299 || ((opcode >= 0x6A) && (opcode <= 0x6F))
2300 || ((opcode >= 0x7A) && (opcode <= 0x7F)))
2301 {
2302 Group_2_Move(opcode);
2303 }
2304 else
2305 {
2306 Group_1(opcode);
2307 }
2308}
2309//uncomment all printf statements.
2310void emulate()
2311{
2312 BYTE opcode;
2313 int sanity;
2314
2315 sanity = 0;
2316 ProgramCounter = 0;
2317 halt = false;
2318 memory_in_range = true;
2319
2320 printf(" A B C D E F X Y SP\n");
2321
2322 while ((!halt) && (memory_in_range)) {
2323 sanity++;
2324 if (sanity > 500) halt = true;
2325 printf("%04X ", ProgramCounter); // Print current address
2326 opcode = fetch();
2327 execute(opcode);
2328
2329 printf("%s ", opcode_mneumonics[opcode]); // Print current opcode
2330
2331 //printf("%02X ", Registers[REGISTER_A]);
2332 //printf("%02X ", Registers[REGISTER_B]);
2333 //printf("%02X ", Registers[REGISTER_C]);
2334 //printf("%02X ", Registers[REGISTER_D]);
2335 //printf("%02X ", Registers[REGISTER_E]);
2336 //printf("%02X ", Registers[REGISTER_F]);
2337 //printf("%02X ", Index_Registers[REGISTER_X]);
2338 //printf("%02X ", Index_Registers[REGISTER_Y]);
2339 //printf("%04X ", StackPointer); // Print Stack Pointer
2340
2341 if ((Flags & FLAG_I) == FLAG_I)
2342 {
2343 //printf("I=1 ");
2344 }
2345 else
2346 {
2347 //printf("I=0 ");
2348 }
2349 if ((Flags & FLAG_V) == FLAG_V)
2350 {
2351 //printf("V=1 ");
2352 }
2353 else
2354 {
2355 //printf("V=0 ");
2356 }
2357 if ((Flags & FLAG_N) == FLAG_N)
2358 {
2359 //printf("N=1 ");
2360 }
2361 else
2362 {
2363 //printf("N=0 ");
2364 }
2365 if ((Flags & FLAG_Z) == FLAG_Z)
2366 {
2367 //printf("Z=1 ");
2368 }
2369 else
2370 {
2371 //printf("Z=0 ");
2372 }
2373 if ((Flags & FLAG_C) == FLAG_C)
2374 {
2375 //printf("C=1 ");
2376 }
2377 else
2378 {
2379 //printf("C=0 ");
2380 }
2381
2382 //printf("\n"); // New line
2383 }
2384
2385 //printf("\n"); // New line
2386}
2387
2388
2389////////////////////////////////////////////////////////////////////////////////
2390// Simulator/Emulator (End) //
2391////////////////////////////////////////////////////////////////////////////////
2392
2393
2394void initialise_filenames() {
2395 int i;
2396
2397 for (i=0; i<MAX_FILENAME_SIZE; i++) {
2398 hex_file [i] = '\0';
2399 trc_file [i] = '\0';
2400 }
2401}
2402
2403
2404
2405
2406int find_dot_position(char *filename) {
2407 int dot_position;
2408 int i;
2409 char chr;
2410
2411 dot_position = 0;
2412 i = 0;
2413 chr = filename[i];
2414
2415 while (chr != '\0') {
2416 if (chr == '.') {
2417 dot_position = i;
2418 }
2419 i++;
2420 chr = filename[i];
2421 }
2422
2423 return (dot_position);
2424}
2425
2426
2427int find_end_position(char *filename) {
2428 int end_position;
2429 int i;
2430 char chr;
2431
2432 end_position = 0;
2433 i = 0;
2434 chr = filename[i];
2435
2436 while (chr != '\0') {
2437 end_position = i;
2438 i++;
2439 chr = filename[i];
2440 }
2441
2442 return (end_position);
2443}
2444
2445
2446bool file_exists(char *filename) {
2447 bool exists;
2448 FILE *ifp;
2449
2450 exists = false;
2451
2452 if ( ( ifp = fopen( filename, "r" ) ) != NULL ) {
2453 exists = true;
2454
2455 fclose(ifp);
2456 }
2457
2458 return (exists);
2459}
2460
2461
2462
2463void create_file(char *filename) {
2464 FILE *ofp;
2465
2466 if ( ( ofp = fopen( filename, "w" ) ) != NULL ) {
2467 fclose(ofp);
2468 }
2469}
2470
2471
2472
2473bool getline(FILE *fp, char *buffer) {
2474 bool rc;
2475 bool collect;
2476 char c;
2477 int i;
2478
2479 rc = false;
2480 collect = true;
2481
2482 i = 0;
2483 while (collect) {
2484 c = getc(fp);
2485
2486 switch (c) {
2487 case EOF:
2488 if (i > 0) {
2489 rc = true;
2490 }
2491 collect = false;
2492 break;
2493
2494 case '\n':
2495 if (i > 0) {
2496 rc = true;
2497 collect = false;
2498 buffer[i] = '\0';
2499 }
2500 break;
2501
2502 default:
2503 buffer[i] = c;
2504 i++;
2505 break;
2506 }
2507 }
2508
2509 return (rc);
2510}
2511
2512
2513
2514
2515
2516
2517void load_and_run(int args,_TCHAR** argv) {
2518 char chr;
2519 int ln;
2520 int dot_position;
2521 int end_position;
2522 long i;
2523 FILE *ifp;
2524 long address;
2525 long load_at;
2526 int code;
2527
2528 // Prompt for the .hex file
2529
2530 printf("\n");
2531 printf("Enter the hex filename (.hex): ");
2532
2533 if(args == 2){
2534 ln = 0;
2535 chr = argv[1][ln];
2536 while (chr != '\0')
2537 {
2538 if (ln < MAX_FILENAME_SIZE)
2539 {
2540 hex_file [ln] = chr;
2541 trc_file [ln] = chr;
2542 ln++;
2543 }
2544 chr = argv[1][ln];
2545 }
2546 } else {
2547 ln = 0;
2548 chr = '\0';
2549 while (chr != '\n') {
2550 chr = getchar();
2551
2552 switch(chr) {
2553 case '\n':
2554 break;
2555 default:
2556 if (ln < MAX_FILENAME_SIZE) {
2557 hex_file [ln] = chr;
2558 trc_file [ln] = chr;
2559 ln++;
2560 }
2561 break;
2562 }
2563 }
2564
2565 }
2566 // Tidy up the file names
2567
2568 dot_position = find_dot_position(hex_file);
2569 if (dot_position == 0) {
2570 end_position = find_end_position(hex_file);
2571
2572 hex_file[end_position + 1] = '.';
2573 hex_file[end_position + 2] = 'h';
2574 hex_file[end_position + 3] = 'e';
2575 hex_file[end_position + 4] = 'x';
2576 hex_file[end_position + 5] = '\0';
2577 } else {
2578 hex_file[dot_position + 0] = '.';
2579 hex_file[dot_position + 1] = 'h';
2580 hex_file[dot_position + 2] = 'e';
2581 hex_file[dot_position + 3] = 'x';
2582 hex_file[dot_position + 4] = '\0';
2583 }
2584
2585 dot_position = find_dot_position(trc_file);
2586 if (dot_position == 0) {
2587 end_position = find_end_position(trc_file);
2588
2589 trc_file[end_position + 1] = '.';
2590 trc_file[end_position + 2] = 't';
2591 trc_file[end_position + 3] = 'r';
2592 trc_file[end_position + 4] = 'c';
2593 trc_file[end_position + 5] = '\0';
2594 } else {
2595 trc_file[dot_position + 0] = '.';
2596 trc_file[dot_position + 1] = 't';
2597 trc_file[dot_position + 2] = 'r';
2598 trc_file[dot_position + 3] = 'c';
2599 trc_file[dot_position + 4] = '\0';
2600 }
2601
2602 if (file_exists(hex_file)) {
2603 // Clear Registers and Memory
2604
2605 Registers[REGISTER_A] = 0;
2606 Registers[REGISTER_B] = 0;
2607 Registers[REGISTER_C] = 0;
2608 Registers[REGISTER_D] = 0;
2609 Registers[REGISTER_E] = 0;
2610 Registers[REGISTER_F] = 0;
2611 Index_Registers[REGISTER_X] = 0;
2612 Index_Registers[REGISTER_Y] = 0;
2613 Flags = 0;
2614 ProgramCounter = 0;
2615 StackPointer = 0;
2616
2617 for (i=0; i<MEMORY_SIZE; i++) {
2618 Memory[i] = 0x00;
2619 }
2620
2621 // Load hex file
2622
2623 if ( ( ifp = fopen( hex_file, "r" ) ) != NULL ) {
2624 printf("Loading file...\n\n");
2625
2626 load_at = 0;
2627
2628 while (getline(ifp, InputBuffer)) {
2629 if (sscanf(InputBuffer, "L=%x", &address) == 1) {
2630 load_at = address;
2631 } else if (sscanf(InputBuffer, "%x", &code) == 1) {
2632 if ((load_at >= 0) && (load_at <= MEMORY_SIZE)) {
2633 Memory[load_at] = (BYTE)code;
2634 }
2635 load_at++;
2636 } else {
2637 printf("ERROR> Failed to load instruction: %s \n", InputBuffer);
2638 }
2639 }
2640
2641 fclose(ifp);
2642 }
2643
2644 // Emulate
2645
2646 emulate();
2647 } else {
2648 printf("\n");
2649 printf("ERROR> Input file %s does not exist!\n", hex_file);
2650 printf("\n");
2651 }
2652}
2653
2654void building(int args,_TCHAR** argv){
2655 char buffer[1024];
2656 load_and_run(args,argv);
2657 sprintf(buffer, "0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X",
2658 Memory[TEST_ADDRESS_1],
2659 Memory[TEST_ADDRESS_2],
2660 Memory[TEST_ADDRESS_3],
2661 Memory[TEST_ADDRESS_4],
2662 Memory[TEST_ADDRESS_5],
2663 Memory[TEST_ADDRESS_6],
2664 Memory[TEST_ADDRESS_7],
2665 Memory[TEST_ADDRESS_8],
2666 Memory[TEST_ADDRESS_9],
2667 Memory[TEST_ADDRESS_10],
2668 Memory[TEST_ADDRESS_11],
2669 Memory[TEST_ADDRESS_12]
2670 );
2671 sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
2672}
2673
2674
2675
2676void test_and_mark() {
2677 char buffer[1024];
2678 bool testing_complete;
2679 int len = sizeof(SOCKADDR);
2680 char chr;
2681 int i;
2682 int j;
2683 bool end_of_program;
2684 long address;
2685 long load_at;
2686 int code;
2687 int mark;
2688 int passed;
2689
2690 printf("\n");
2691 printf("Automatic Testing and Marking\n");
2692 printf("\n");
2693
2694 testing_complete = false;
2695
2696 sprintf(buffer, "Test Student %s", STUDENT_NUMBER);
2697 sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
2698
2699 while (!testing_complete) {
2700 memset(buffer, '\0', sizeof(buffer));
2701
2702 if (recvfrom(sock, buffer, sizeof(buffer)-1, 0, (SOCKADDR *)&client_addr, &len) != SOCKET_ERROR) {
2703 printf("Incoming Data: %s \n", buffer);
2704
2705 //if (strcmp(buffer, "Testing complete") == 1)
2706 if (sscanf(buffer, "Testing complete %d", &mark) == 1) {
2707 testing_complete = true;
2708 printf("Current mark = %d\n", mark);
2709
2710 }else if (sscanf(buffer, "Tests passed %d", &passed) == 1) {
2711 //testing_complete = true;
2712 printf("Passed = %d\n", passed);
2713
2714 } else if (strcmp(buffer, "Error") == 0) {
2715 printf("ERROR> Testing abnormally terminated\n");
2716 testing_complete = true;
2717 } else {
2718 // Clear Registers and Memory
2719
2720 Registers[REGISTER_A] = 0;
2721 Registers[REGISTER_B] = 0;
2722 Registers[REGISTER_C] = 0;
2723 Registers[REGISTER_D] = 0;
2724 Registers[REGISTER_E] = 0;
2725 Registers[REGISTER_F] = 0;
2726 Index_Registers[REGISTER_X] = 0;
2727 Index_Registers[REGISTER_Y] = 0;
2728 Flags = 0;
2729 ProgramCounter = 0;
2730 StackPointer = 0;
2731 for (i=0; i<MEMORY_SIZE; i++) {
2732 Memory[i] = 0;
2733 }
2734
2735 // Load hex file
2736
2737 i = 0;
2738 j = 0;
2739 load_at = 0;
2740 end_of_program = false;
2741 FILE *ofp;
2742 fopen_s(&ofp ,"branch.txt", "a");
2743
2744 while (!end_of_program) {
2745 chr = buffer[i];
2746 switch (chr) {
2747 case '\0':
2748 end_of_program = true;
2749
2750 case ',':
2751 if (sscanf(InputBuffer, "L=%x", &address) == 1) {
2752 load_at = address;
2753 } else if (sscanf(InputBuffer, "%x", &code) == 1) {
2754 if ((load_at >= 0) && (load_at <= MEMORY_SIZE)) {
2755 Memory[load_at] = (BYTE)code;
2756 fprintf(ofp, "%02X\n", (BYTE)code);
2757 }
2758 load_at++;
2759 } else {
2760 printf("ERROR> Failed to load instruction: %s \n", InputBuffer);
2761 }
2762 j = 0;
2763 break;
2764
2765 default:
2766 InputBuffer[j] = chr;
2767 j++;
2768 break;
2769 }
2770 i++;
2771 }
2772 fclose(ofp);
2773 // Emulate
2774
2775 if (load_at > 1) {
2776 emulate();
2777 // Send and store results
2778 sprintf(buffer, "%02X%02X %02X%02X %02X%02X %02X%02X %02X%02X %02X%02X",
2779 Memory[TEST_ADDRESS_1],
2780 Memory[TEST_ADDRESS_2],
2781 Memory[TEST_ADDRESS_3],
2782 Memory[TEST_ADDRESS_4],
2783 Memory[TEST_ADDRESS_5],
2784 Memory[TEST_ADDRESS_6],
2785 Memory[TEST_ADDRESS_7],
2786 Memory[TEST_ADDRESS_8],
2787 Memory[TEST_ADDRESS_9],
2788 Memory[TEST_ADDRESS_10],
2789 Memory[TEST_ADDRESS_11],
2790 Memory[TEST_ADDRESS_12]
2791 );
2792 sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
2793 }
2794 }
2795 }
2796 }
2797}
2798
2799
2800
2801int _tmain(int argc, _TCHAR* argv[])
2802{
2803 char chr;
2804 char dummy;
2805
2806 printf("\n");
2807 printf("Microprocessor Emulator\n");
2808 printf("UWE Computer and Network Systems Assignment 1\n");
2809 printf("\n");
2810
2811 initialise_filenames();
2812
2813 if (WSAStartup(MAKEWORD(2, 2), &data) != 0) return(0);
2814
2815 sock = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); // Here we create our socket, which will be a UDP socket (SOCK_DGRAM).
2816 if (!sock) {
2817 // Creation failed!
2818 }
2819
2820 memset(&server_addr, 0, sizeof(SOCKADDR_IN));
2821 server_addr.sin_family = AF_INET;
2822 server_addr.sin_addr.s_addr = inet_addr(IP_ADDRESS_SERVER);
2823 server_addr.sin_port = htons(PORT_SERVER);
2824
2825 memset(&client_addr, 0, sizeof(SOCKADDR_IN));
2826 client_addr.sin_family = AF_INET;
2827 client_addr.sin_addr.s_addr = inet_addr("127.0.0.1");
2828 client_addr.sin_port = htons(PORT_CLIENT);
2829
2830 chr = '\0';
2831 while ((chr != 'e') && (chr != 'E'))
2832 {
2833 printf("\n");
2834 printf("Please select option\n");
2835 printf("L - Load and run a hex file\n");
2836 printf("T - Have the server test and mark your emulator\n");
2837 printf("E - Exit\n");
2838 if(argc == 2){ building(argc,argv); exit(0);}
2839 printf("Enter option: ");
2840 chr = getchar();
2841 if (chr != 0x0A)
2842 {
2843 dummy = getchar(); // read in the <CR>
2844 }
2845 printf("\n");
2846
2847 switch (chr)
2848 {
2849 case 'L':
2850 case 'l':
2851 load_and_run(argc,argv);
2852 break;
2853
2854 case 'T':
2855 case 't':
2856 test_and_mark();
2857 break;
2858
2859 default:
2860 break;
2861 }
2862 }
2863
2864 closesocket(sock);
2865 WSACleanup();
2866
2867
2868 return 0;
2869}