Af5a3ei5

1/*
2* Author: Jan Klimaszewski (17026846)
3* Created: 05/02/2019
4* Revised: 20/02/2019
5* Description: Program that emulates the Chimera-2016-I Processor
6* User advice: none
7*/
8
9#include "stdafx.h"
10#include <winsock2.h>
11
12#pragma comment(lib, "wsock32.lib")
13
14
15#define STUDENT_NUMBER    "17026846"
16
17#define IP_ADDRESS_SERVER "127.0.0.1"
18
19#define PORT_SERVER 0x1984 // We define a port that we are going to use.
20#define PORT_CLIENT 0x1985 // We define a port that we are going to use.
21
22#define WORD  unsigned short
23#define DWORD unsigned long
24#define BYTE  unsigned char
25
26#define MAX_FILENAME_SIZE 500
27#define MAX_BUFFER_SIZE   500
28
29SOCKADDR_IN server_addr;
30SOCKADDR_IN client_addr;
31
32SOCKET sock;  // This is our socket, it is the handle to the IO address to read/write packets
33
34WSADATA data;
35
36char InputBuffer[MAX_BUFFER_SIZE];
37
38char hex_file[MAX_BUFFER_SIZE];
39char trc_file[MAX_BUFFER_SIZE];
40
41//////////////////////////
42//   Registers          //
43//////////////////////////
44
45#define FLAG_Z  0x80
46#define FLAG_I  0x20
47#define FLAG_N  0x08
48#define FLAG_C  0x01
49#define REGISTER_M	5
50#define REGISTER_A	4
51#define REGISTER_H	3
52#define REGISTER_L	2
53#define REGISTER_C	1
54#define REGISTER_B	0
55#define REGISTER_X 0
56#define REGISTER_Y 1
57BYTE Index_Registers[2];
58
59BYTE Registers[6];
60BYTE Flags;
61WORD ProgramCounter;
62WORD StackPointer;
63
64
65////////////
66// Memory //
67////////////
68
69#define MEMORY_SIZE	65536
70
71BYTE Memory[MEMORY_SIZE];
72
73#define TEST_ADDRESS_1  0x01FA
74#define TEST_ADDRESS_2  0x01FB
75#define TEST_ADDRESS_3  0x01FC
76#define TEST_ADDRESS_4  0x01FD
77#define TEST_ADDRESS_5  0x01FE
78#define TEST_ADDRESS_6  0x01FF
79#define TEST_ADDRESS_7  0x0200
80#define TEST_ADDRESS_8  0x0201
81#define TEST_ADDRESS_9  0x0202
82#define TEST_ADDRESS_10  0x0203
83#define TEST_ADDRESS_11  0x0204
84#define TEST_ADDRESS_12  0x0205
85
86
87///////////////////////
88// Control variables //
89///////////////////////
90
91bool memory_in_range = true;
92bool halt = false;
93
94
95///////////////////////
96// Disassembly table //
97///////////////////////
98
99char opcode_mneumonics[][14] =
100{
101"ILLEGAL     ",
102"ILLEGAL     ",
103"SWI impl     ",
104"RTI impl     ",
105"STO abs      ",
106"STOX abs     ",
107"STOY abs     ",
108"JMPR abs     ",
109"CCC abs      ",
110"CCS abs      ",
111"CNE abs      ",
112"CEQ abs      ",
113"CMI abs      ",
114"CPL abs      ",
115"ILLEGAL     ",
116"STOS abs     ",
117
118"ILLEGAL     ",
119"ILLEGAL     ",
120"ILLEGAL     ",
121"ILLEGAL     ",
122"STO abs,X    ",
123"STOX abs,X   ",
124"STOY abs,X   ",
125"NOP impl     ",
126"WAI impl     ",
127"ILLEGAL     ",
128"ILLEGAL     ",
129"ILLEGAL     ",
130"ADI  #       ",
131"CPI  #       ",
132"ANI  #       ",
133"STOS abs,X   ",
134
135"LODS  #      ",
136"LDX  #       ",
137"LODY  #      ",
138"RT impl      ",
139"STO abs,Y    ",
140"STOX abs,Y   ",
141"STOY abs,Y   ",
142"MVR  #,B     ",
143"MVR  #,C     ",
144"MVR  #,L     ",
145"MVR  #,H     ",
146"TAY impl     ",
147"TYA impl     ",
148"MSA impl     ",
149"ILLEGAL     ",
150"STOS abs,Y   ",
151
152"LODS abs     ",
153"LDX abs      ",
154"LODY abs     ",
155"ILLEGAL     ",
156"STO abs,XY   ",
157"STOX abs,XY  ",
158"STOY abs,XY  ",
159"ILLEGAL     ",
160"JUMP abs     ",
161"JCC abs      ",
162"JCS abs      ",
163"JNE abs      ",
164"JEQ abs      ",
165"JMI abs      ",
166"JPL abs      ",
167"STOS abs,XY  ",
168
169"LODS abs,X   ",
170"LDX abs,X    ",
171"LODY abs,X   ",
172"LD  #        ",
173"STO zpg      ",
174"STOX zpg     ",
175"STOY zpg     ",
176"ILLEGAL     ",
177"ILLEGAL     ",
178"ILLEGAL     ",
179"DEX impl     ",
180"INX impl     ",
181"DEY impl     ",
182"INY impl     ",
183"ILLEGAL     ",
184"STOS zpg     ",
185
186"LODS abs,Y   ",
187"LDX abs,Y    ",
188"LODY abs,Y   ",
189"LD abs       ",
190"TEST abs     ",
191"INC abs      ",
192"DEC abs      ",
193"RR abs       ",
194"RCL abs      ",
195"SAL abs      ",
196"SHR abs      ",
197"COM abs      ",
198"NEG abs      ",
199"RAL abs      ",
200"ROR abs      ",
201"CLR abs      ",
202
203"LODS abs,XY  ",
204"LDX abs,XY   ",
205"LODY abs,XY  ",
206"LD abs,X     ",
207"TEST abs,X   ",
208"INC abs,X    ",
209"DEC abs,X    ",
210"RR abs,X     ",
211"RCL abs,X    ",
212"SAL abs,X    ",
213"SHR abs,X    ",
214"COM abs,X    ",
215"NEG abs,X    ",
216"RAL abs,X    ",
217"ROR abs,X    ",
218"CLR abs,X    ",
219
220"LODS zpg     ",
221"LDX zpg      ",
222"LODY zpg     ",
223"LD abs,Y     ",
224"TEST abs,Y   ",
225"INC abs,Y    ",
226"DEC abs,Y    ",
227"RR abs,Y     ",
228"RCL abs,Y    ",
229"SAL abs,Y    ",
230"SHR abs,Y    ",
231"COM abs,Y    ",
232"NEG abs,Y    ",
233"RAL abs,Y    ",
234"ROR abs,Y    ",
235"CLR abs,Y    ",
236
237"ILLEGAL     ",
238"ILLEGAL     ",
239"ILLEGAL     ",
240"LD abs,XY    ",
241"TEST abs,XY  ",
242"INC abs,XY   ",
243"DEC abs,XY   ",
244"RR abs,XY    ",
245"RCL abs,XY   ",
246"SAL abs,XY   ",
247"SHR abs,XY   ",
248"COM abs,XY   ",
249"NEG abs,XY   ",
250"RAL abs,XY   ",
251"ROR abs,XY   ",
252"CLR abs,XY   ",
253
254"ILLEGAL     ",
255"ILLEGAL     ",
256"ILLEGAL     ",
257"LD zpg       ",
258"TESTA A,A    ",
259"INCA A,A     ",
260"DECA A,A     ",
261"RRA A,A      ",
262"RCLA A,A     ",
263"SALA A,A     ",
264"SHRA A,A     ",
265"COMA A,A     ",
266"NEGA A,0     ",
267"RALA A,A     ",
268"RORA A,A     ",
269"CLRA A,0     ",
270
271"MV A,A       ",
272"MV B,A       ",
273"MV C,A       ",
274"MV L,A       ",
275"MV H,A       ",
276"MV M,A       ",
277"CLC impl     ",
278"SEC impl     ",
279"CLI impl     ",
280"SEI impl     ",
281"CMC impl     ",
282"ILLEGAL     ",
283"ILLEGAL     ",
284"ILLEGAL     ",
285"PUSH  ,A     ",
286"POP A,       ",
287
288"MV A,B       ",
289"MV B,B       ",
290"MV C,B       ",
291"MV L,B       ",
292"MV H,B       ",
293"MV M,B       ",
294"ADC A,B      ",
295"SBC A,B      ",
296"ADD A,B      ",
297"SUB A,B      ",
298"CMP A,B      ",
299"OR A,B       ",
300"AND A,B      ",
301"XOR A,B      ",
302"PUSH  ,s     ",
303"POP s,       ",
304
305"MV A,C       ",
306"MV B,C       ",
307"MV C,C       ",
308"MV L,C       ",
309"MV H,C       ",
310"MV M,C       ",
311"ADC A,C      ",
312"SBC A,C      ",
313"ADD A,C      ",
314"SUB A,C      ",
315"CMP A,C      ",
316"OR A,C       ",
317"AND A,C      ",
318"XOR A,C      ",
319"PUSH  ,B     ",
320"POP B,       ",
321
322"MV A,L       ",
323"MV B,L       ",
324"MV C,L       ",
325"MV L,L       ",
326"MV H,L       ",
327"MV M,L       ",
328"ADC A,L      ",
329"SBC A,L      ",
330"ADD A,L      ",
331"SUB A,L      ",
332"CMP A,L      ",
333"OR A,L       ",
334"AND A,L      ",
335"XOR A,L      ",
336"PUSH  ,C     ",
337"POP C,       ",
338
339"MV A,H       ",
340"MV B,H       ",
341"MV C,H       ",
342"MV L,H       ",
343"MV H,H       ",
344"MV M,H       ",
345"ADC A,H      ",
346"SBC A,H      ",
347"ADD A,H      ",
348"SUB A,H      ",
349"CMP A,H      ",
350"OR A,H       ",
351"AND A,H      ",
352"XOR A,H      ",
353"PUSH  ,L     ",
354"POP L,       ",
355
356"MV A,M       ",
357"MV B,M       ",
358"MV C,M       ",
359"MV L,M       ",
360"MV H,M       ",
361"MV -,-       ",
362"ADC A,M      ",
363"SBC A,M      ",
364"ADD A,M      ",
365"SUB A,M      ",
366"CMP A,M      ",
367"OR A,M       ",
368"AND A,M      ",
369"XOR A,M      ",
370"PUSH  ,H     ",
371"POP H,       ",
372
373};
374
375////////////////////////////////////////////////////////////////////////////////
376//                           Simulator/Emulator (Start)                       //
377////////////////////////////////////////////////////////////////////////////////
378BYTE fetch()
379{
380	BYTE byte = 0;
381
382	if ((ProgramCounter >= 0) && (ProgramCounter <= MEMORY_SIZE))
383	{
384		memory_in_range = true;
385		byte = Memory[ProgramCounter];
386		ProgramCounter++;
387	}
388	else
389	{
390		memory_in_range = false;
391	}
392	return byte;
393}
394
395void set_flag_n(BYTE inReg) {
396	BYTE reg;
397	reg = inReg;
398
399	if ((reg & 0x80) != 0) // msbit set 
400	{
401		Flags = Flags | FLAG_N;
402	}
403	else
404	{
405		Flags = Flags & (0xFF - FLAG_N);
406	}
407}
408
409void set_flag_z(BYTE inReg) {
410
411	BYTE reg;
412	reg = inReg;
413
414	if (reg == 0) // msbit set 
415	{
416		Flags = Flags | FLAG_Z;
417	}
418	else
419	{
420		Flags = Flags & (0xFF - FLAG_Z);
421	}
422}
423
424void Group_1(BYTE opcode) {
425	BYTE LB = 0;
426	BYTE HB = 0;
427	BYTE saved_flags = 0;
428	WORD address = 0;
429	WORD data = 0;
430	WORD temp_word = 0;
431
432	switch (opcode) {
433	case 0x43: //LD Immediate
434		data = fetch();
435		Registers[REGISTER_A] = data;
436		set_flag_n((BYTE)Registers[REGISTER_A]);
437		set_flag_z((BYTE)Registers[REGISTER_A]);
438		break;
439
440	case 0x53: //LD Absoulute 
441		LB = fetch();
442		HB = fetch();
443		address += (WORD)((WORD)HB << 8) + LB;
444		if (address >= 0 && address < MEMORY_SIZE) {
445			Registers[REGISTER_A] = Memory[address];
446		}
447		set_flag_n((BYTE)Registers[REGISTER_A]);
448		set_flag_z((BYTE)Registers[REGISTER_A]);
449		break;
450
451	case 0x63://LD Absoulte X
452		address += Index_Registers[REGISTER_X];
453		LB = fetch();
454		HB = fetch();
455		address += (WORD)((WORD)HB << 8) + LB;
456		if (address >= 0 && address < MEMORY_SIZE) {
457			Registers[REGISTER_A] = Memory[address];
458		}
459		set_flag_n((BYTE)Registers[REGISTER_A]);
460		set_flag_z((BYTE)Registers[REGISTER_A]);
461		break;
462
463	case 0x73://LD Absoulte Y
464		address += Index_Registers[REGISTER_Y];
465		LB = fetch();
466		HB = fetch();
467		address += (WORD)((WORD)HB << 8) + LB;
468		if (address >= 0 && address < MEMORY_SIZE) {
469			Registers[REGISTER_A] = Memory[address];
470		}
471		set_flag_n((BYTE)Registers[REGISTER_A]);
472		set_flag_z((BYTE)Registers[REGISTER_A]);
473		break;
474
475	case 0x83://LD Absoulte XY
476		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
477		LB = fetch();
478		HB = fetch();
479		address += (WORD)((WORD)HB << 8) + LB;
480		if (address >= 0 && address < MEMORY_SIZE) {
481			Registers[REGISTER_A] = Memory[address];
482		}
483		set_flag_n((BYTE)Registers[REGISTER_A]);
484		set_flag_z((BYTE)Registers[REGISTER_A]);
485		break;
486
487	case 0x93://LD zpg
488		address += 0x0000 | (WORD)fetch();
489		if (address >= 0 && address < MEMORY_SIZE) {
490			Registers[REGISTER_A] = Memory[address];
491		}
492		set_flag_n((BYTE)Registers[REGISTER_A]);
493		set_flag_z((BYTE)Registers[REGISTER_A]);
494		break;
495
496	case 0x04://STO Absolute
497		LB = fetch();
498		HB = fetch();
499		address += (WORD)((WORD)HB << 8) + LB;
500		if (address >= 0 && address < MEMORY_SIZE) {
501			Memory[address] = Registers[REGISTER_A];
502		}
503		set_flag_n((BYTE)Memory[address]);
504		set_flag_z((BYTE)Memory[address]);
505		break;
506
507	case 0x14://STO Absolute X
508		address += Index_Registers[REGISTER_X];
509		LB = fetch();
510		HB = fetch();
511		address += (WORD)((WORD)HB << 8) + LB;
512		if (address >= 0 && address < MEMORY_SIZE) {
513			Memory[address] = Registers[REGISTER_A];
514		}
515		set_flag_n((BYTE)Memory[address]);
516		set_flag_z((BYTE)Memory[address]);
517		break;
518
519	case 0x24: //STO Absolute Y
520		address += Index_Registers[REGISTER_Y];
521		LB = fetch();
522		HB = fetch();
523		address += (WORD)((WORD)HB << 8) + LB;
524		if (address >= 0 && address < MEMORY_SIZE) {
525			Memory[address] = Registers[REGISTER_A];
526		}
527		set_flag_n((BYTE)Memory[address]);
528		set_flag_z((BYTE)Memory[address]);
529		break;
530
531	case 0x34://STO Absolute XY
532		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
533		LB = fetch();
534		HB = fetch();
535		address += (WORD)((WORD)HB << 8) + LB;
536		if (address >= 0 && address < MEMORY_SIZE) {
537			Memory[address] = Registers[REGISTER_A];
538		}
539		set_flag_n((BYTE)Memory[address]);
540		set_flag_z((BYTE)Memory[address]);
541		break;
542
543	case 0x44://STO zpg
544		address += 0x0000 | (WORD)fetch();
545		if (address >= 0 && address < MEMORY_SIZE) {
546			Memory[address] = Registers[REGISTER_A];
547		}
548		set_flag_n((BYTE)Memory[address]);
549		set_flag_z((BYTE)Memory[address]);
550		break;
551
552	case 0x21://LDX Immediate
553		data = fetch();
554		Index_Registers[REGISTER_X] = data;
555		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
556		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
557		break;
558
559	case 0x31: //LDX Absoulute 
560		LB = fetch();
561		HB = fetch();
562		address += (WORD)((WORD)HB << 8) + LB;
563		if (address >= 0 && address < MEMORY_SIZE) {
564			Index_Registers[REGISTER_X] = Memory[address];
565		}
566		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
567		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
568		break;
569
570	case 0x41://LDX Absoulte X
571		address += Index_Registers[REGISTER_X];
572		LB = fetch();
573		HB = fetch();
574		address += (WORD)((WORD)HB << 8) + LB;
575		if (address >= 0 && address < MEMORY_SIZE) {
576			Index_Registers[REGISTER_X] = Memory[address];
577		}
578		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
579		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
580		break;
581
582	case 0x51://LDX Absoulte Y
583		address += Index_Registers[REGISTER_Y];
584		LB = fetch();
585		HB = fetch();
586		address += (WORD)((WORD)HB << 8) + LB;
587		if (address >= 0 && address < MEMORY_SIZE) {
588			Index_Registers[REGISTER_X] = Memory[address];
589		}
590		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
591		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
592		break;
593
594	case 0x61://LDX Absoulte XY
595		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
596		LB = fetch();
597		HB = fetch();
598		address += (WORD)((WORD)HB << 8) + LB;
599		if (address >= 0 && address < MEMORY_SIZE) {
600			Index_Registers[REGISTER_X] = Memory[address];
601		}
602		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
603		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
604		break;
605
606	case 0x71://LDX zpg
607		address += 0x0000 | (WORD)fetch();
608		if (address >= 0 && address < MEMORY_SIZE) {
609			Index_Registers[REGISTER_X] = Memory[address];
610		}
611		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
612		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
613		break;
614
615	case 0x22://LODY Immediate
616		data = fetch();
617		Index_Registers[REGISTER_Y] = data;
618		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
619		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
620		break;
621
622	case 0x32: //LODY Absoulute 
623		LB = fetch();
624		HB = fetch();
625		address += (WORD)((WORD)HB << 8) + LB;
626		if (address >= 0 && address < MEMORY_SIZE) {
627			Index_Registers[REGISTER_Y] = Memory[address];
628		}
629		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
630		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
631		break;
632
633	case 0x42://LODY Absoulte X
634		address += Index_Registers[REGISTER_X];
635		LB = fetch();
636		HB = fetch();
637		address += (WORD)((WORD)HB << 8) + LB;
638		if (address >= 0 && address < MEMORY_SIZE) {
639			Index_Registers[REGISTER_Y] = Memory[address];
640		}
641		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
642		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
643		break;
644
645	case 0x52://LODY Absoulte Y
646		address += Index_Registers[REGISTER_Y];
647		LB = fetch();
648		HB = fetch();
649		address += (WORD)((WORD)HB << 8) + LB;
650		if (address >= 0 && address < MEMORY_SIZE) {
651			Index_Registers[REGISTER_Y] = Memory[address];
652		}
653		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
654		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
655		break;
656
657	case 0x62://LODY Absoulte XY
658		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
659		LB = fetch();
660		HB = fetch();
661		address += (WORD)((WORD)HB << 8) + LB;
662		if (address >= 0 && address < MEMORY_SIZE) {
663			Index_Registers[REGISTER_Y] = Memory[address];
664		}
665		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
666		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
667		break;
668
669	case 0x72://LODY zpg
670		address += 0x0000 | (WORD)fetch();
671		if (address >= 0 && address < MEMORY_SIZE) {
672			Index_Registers[REGISTER_Y] = Memory[address];
673		}
674		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
675		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
676		break;
677
678	case 0x27://Register B MVR Intermediate
679		data = fetch();
680		Registers[REGISTER_B] = data;
681		set_flag_n((BYTE)Registers[REGISTER_B]);
682		set_flag_z((BYTE)Registers[REGISTER_B]);
683		break;
684
685	case 0x28://Register C MVR Intermediate
686		data = fetch();
687		Registers[REGISTER_C] = data;
688		set_flag_n((BYTE)Registers[REGISTER_C]);
689		set_flag_z((BYTE)Registers[REGISTER_C]);
690		break;
691
692	case 0x29://Register L MVR Intermediate
693		data = fetch();
694		Registers[REGISTER_L] = data;
695		set_flag_n((BYTE)Registers[REGISTER_L]);
696		set_flag_z((BYTE)Registers[REGISTER_L]);
697		break;
698
699	case 0x2A://Register H MVR Intermediate
700		data = fetch();
701		Registers[REGISTER_H] = data;
702		set_flag_n((BYTE)Registers[REGISTER_H]);
703		set_flag_z((BYTE)Registers[REGISTER_H]);
704		break;
705
706	case 0x20://LODS Immediate
707		data = fetch();
708		StackPointer = data;
709		StackPointer += (WORD)fetch() << 8;
710		set_flag_n((BYTE)StackPointer);
711		set_flag_z((BYTE)StackPointer);
712		break;
713
714	case 0x30://LODS Absoulte
715		LB = fetch();
716		HB = fetch();
717		address += (WORD)((WORD)HB << 8) + LB;
718		if (address >= 0 && address < MEMORY_SIZE - 1) {
719			StackPointer = Memory[address];
720			StackPointer += (WORD)Memory[address + 1] << 8;
721		}
722		set_flag_n((BYTE)StackPointer);
723		set_flag_z((BYTE)StackPointer);
724		break;
725
726	case 0x40://LODS Absoulte X
727		address += Index_Registers[REGISTER_X];
728		LB = fetch();
729		HB = fetch();
730		address += (WORD)((WORD)HB << 8) + LB;
731		if (address >= 0 && address < MEMORY_SIZE - 1) {
732			StackPointer = Memory[address];
733			StackPointer += (WORD)Memory[address + 1] << 8;
734		}
735		set_flag_n((BYTE)StackPointer);
736		set_flag_z((BYTE)StackPointer);
737		break;
738
739	case 0x50://LODS Absoulte Y
740		address += Index_Registers[REGISTER_Y];
741		LB = fetch();
742		HB = fetch();
743		address += (WORD)((WORD)HB << 8) + LB;
744		if (address >= 0 && address < MEMORY_SIZE - 1) {
745			StackPointer = Memory[address];
746			StackPointer += (WORD)Memory[address + 1] << 8;
747		}
748		set_flag_n((BYTE)StackPointer);
749		set_flag_z((BYTE)StackPointer);
750		break;
751
752	case 0x60://LODS Absolute XY
753		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
754		LB = fetch();
755		HB = fetch();
756		address += (WORD)((WORD)HB << 8) + LB;
757		if (address >= 0 && address < MEMORY_SIZE - 1) {
758			StackPointer = Memory[address];
759			StackPointer += (WORD)Memory[address + 1] << 8;
760		}
761		set_flag_n((BYTE)StackPointer);
762		set_flag_z((BYTE)StackPointer);
763		break;
764
765	case 0x70://LODS zpg
766		address += 0x0000 | (WORD)fetch();
767		if (address >= 0 && address < MEMORY_SIZE - 1) {
768			StackPointer = Memory[address];
769			StackPointer += (WORD)Memory[address + 1] << 8;
770		}
771		set_flag_n((BYTE)StackPointer);
772		set_flag_z((BYTE)StackPointer);
773		break;
774
775	case 0x0F://STOS Absoulte
776		LB = fetch();
777		HB = fetch();
778		address += (WORD)((WORD)HB << 8) + LB;
779		if (address >= 0 && address < MEMORY_SIZE - 1) {
780			HB = (BYTE)(StackPointer >> 8);
781			LB = (BYTE)StackPointer;
782			Memory[address] = LB;
783			Memory[address + 1] = HB;
784		}
785		set_flag_n((BYTE)StackPointer);
786		set_flag_z((BYTE)StackPointer);
787		break;
788
789	case 0x1F://STOS Absoulte X
790		address += Index_Registers[REGISTER_X];
791		LB = fetch();
792		HB = fetch();
793		address += (WORD)((WORD)HB << 8) + LB;
794		if (address >= 0 && address < MEMORY_SIZE - 1) {
795			HB = (BYTE)(StackPointer >> 8);
796			LB = (BYTE)StackPointer;
797			Memory[address] = LB;
798			Memory[address + 1] = HB;
799
800		}
801		set_flag_n((BYTE)StackPointer);
802		set_flag_z((BYTE)StackPointer);
803		break;
804
805	case 0x2F://STOS Absoulte Y
806		address += Index_Registers[REGISTER_Y];
807		LB = fetch();
808		HB = fetch();
809		address += (WORD)((WORD)HB << 8) + LB;
810		if (address >= 0 && address < MEMORY_SIZE - 1) {
811			HB = (BYTE)(StackPointer >> 8);
812			LB = (BYTE)StackPointer;
813			Memory[address] = LB;
814			Memory[address + 1] = HB;
815		}
816		set_flag_n((BYTE)StackPointer);
817		set_flag_z((BYTE)StackPointer);
818		break;
819
820	case 0x3F://STOS Absolute XY
821		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
822		LB = fetch();
823		HB = fetch();
824		address += (WORD)((WORD)HB << 8) + LB;
825		if (address >= 0 && address < MEMORY_SIZE - 1) {
826			HB = (BYTE)(StackPointer >> 8);
827			LB = (BYTE)StackPointer;
828			Memory[address] = LB;
829			Memory[address + 1] = HB;
830		}
831		set_flag_n((BYTE)StackPointer);
832		set_flag_z((BYTE)StackPointer);
833		break;
834
835	case 0x4F://STOS zpg
836		address += 0x0000 | (WORD)fetch();
837		if (address >= 0 && address < MEMORY_SIZE - 1) {
838			HB = (BYTE)(StackPointer >> 8);
839			LB = (BYTE)StackPointer;
840			Memory[address] = LB;
841			Memory[address + 1] = HB;
842		}
843		set_flag_n((BYTE)StackPointer);
844		set_flag_z((BYTE)StackPointer);
845		break;
846
847	case 0x05://STOX Absolute
848		LB = fetch();
849		HB = fetch();
850		address += (WORD)((WORD)HB << 8) + LB;
851		if (address >= 0 && address < MEMORY_SIZE) {
852			Memory[address] = Index_Registers[REGISTER_X];
853		}
854		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
855		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
856		break;
857
858	case 0x15://STOX Absolute X
859		address += Index_Registers[REGISTER_X];
860		LB = fetch();
861		HB = fetch();
862		address += (WORD)((WORD)HB << 8) + LB;
863		if (address >= 0 && address < MEMORY_SIZE) {
864			Memory[address] = Index_Registers[REGISTER_X];
865		}
866		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
867		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
868		break;
869
870	case 0x25: //STOX Absolute Y
871		address += Index_Registers[REGISTER_Y];
872		LB = fetch();
873		HB = fetch();
874		address += (WORD)((WORD)HB << 8) + LB;
875		if (address >= 0 && address < MEMORY_SIZE) {
876			Memory[address] = Index_Registers[REGISTER_X];
877		}
878		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
879		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
880		break;
881
882	case 0x35://STOX Absolute XY
883		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
884		LB = fetch();
885		HB = fetch();
886		address += (WORD)((WORD)HB << 8) + LB;
887		if (address >= 0 && address < MEMORY_SIZE) {
888			Memory[address] = Index_Registers[REGISTER_X];
889		}
890		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
891		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
892		break;
893
894	case 0x45://STOX zpg
895		address += 0x0000 | (WORD)fetch();
896		if (address >= 0 && address < MEMORY_SIZE) {
897			Memory[address] = Index_Registers[REGISTER_X];
898		}
899		set_flag_n((BYTE)Index_Registers[REGISTER_X]);
900		set_flag_z((BYTE)Index_Registers[REGISTER_X]);
901		break;
902
903	case 0x06://STOY Absolute
904		LB = fetch();
905		HB = fetch();
906		address += (WORD)((WORD)HB << 8) + LB;
907		if (address >= 0 && address < MEMORY_SIZE) {
908			Memory[address] = Index_Registers[REGISTER_Y];
909		}
910		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
911		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
912		break;
913
914	case 0x16://STOY Absolute X
915		address += Index_Registers[REGISTER_X];
916		LB = fetch();
917		HB = fetch();
918		address += (WORD)((WORD)HB << 8) + LB;
919		if (address >= 0 && address < MEMORY_SIZE) {
920			Memory[address] = Index_Registers[REGISTER_Y];
921		}
922		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
923		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
924		break;
925
926	case 0x26: //STOY Absolute Y
927		address += Index_Registers[REGISTER_Y];
928		LB = fetch();
929		HB = fetch();
930		address += (WORD)((WORD)HB << 8) + LB;
931		if (address >= 0 && address < MEMORY_SIZE) {
932			Memory[address] = Index_Registers[REGISTER_Y];
933		}
934		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
935		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
936		break;
937
938	case 0x36://STOY Absolute XY
939		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
940		LB = fetch();
941		HB = fetch();
942		address += (WORD)((WORD)HB << 8) + LB;
943		if (address >= 0 && address < MEMORY_SIZE) {
944			Memory[address] = Index_Registers[REGISTER_Y];
945		}
946		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
947		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
948		break;
949
950	case 0x46://STOY zpg
951		address += 0x0000 | (WORD)fetch();
952		if (address >= 0 && address < MEMORY_SIZE) {
953			Memory[address] = Index_Registers[REGISTER_Y];
954		}
955		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
956		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
957		break;
958
959	case 0xB6://ADC A,B
960		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_B];
961		if ((Flags & FLAG_C) != 0)
962		{
963			temp_word++;
964		}
965		if (temp_word >= 0x100)
966		{
967			Flags = Flags | FLAG_C;
968		}
969		else
970		{
971			Flags = Flags & (0xFF - FLAG_C);
972		}
973		set_flag_n((BYTE)temp_word);
974		set_flag_z((BYTE)temp_word);
975		Registers[REGISTER_A] = (BYTE)temp_word;
976		break;
977
978	case 0xC6://ADC A,C
979		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_C];
980		if ((Flags & FLAG_C) != 0)
981		{
982			temp_word++;
983		}
984		if (temp_word >= 0x100)
985		{
986			Flags = Flags | FLAG_C;
987		}
988		else
989		{
990			Flags = Flags & (0xFF - FLAG_C);
991		}
992		set_flag_n((BYTE)temp_word);
993		set_flag_z((BYTE)temp_word);
994		Registers[REGISTER_A] = (BYTE)temp_word;
995		break;
996
997	case 0xD6://ADC A,L
998		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_L];
999		if ((Flags & FLAG_C) != 0)
1000		{
1001			temp_word++;
1002		}
1003		if (temp_word >= 0x100)
1004		{
1005			Flags = Flags | FLAG_C;
1006		}
1007		else
1008		{
1009			Flags = Flags & (0xFF - FLAG_C);
1010		}
1011		set_flag_n((BYTE)temp_word);
1012		set_flag_z((BYTE)temp_word);
1013		Registers[REGISTER_A] = (BYTE)temp_word;
1014		break;
1015
1016	case 0xE6://ADC A,H
1017		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_H];
1018		if ((Flags & FLAG_C) != 0)
1019		{
1020			temp_word++;
1021		}
1022		if (temp_word >= 0x100)
1023		{
1024			Flags = Flags | FLAG_C;
1025		}
1026		else
1027		{
1028			Flags = Flags & (0xFF - FLAG_C);
1029		}
1030		set_flag_n((BYTE)temp_word);
1031		set_flag_z((BYTE)temp_word);
1032		Registers[REGISTER_A] = (BYTE)temp_word;
1033		break;
1034
1035	case 0xF6://ADC A,M
1036		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_M];
1037		if ((Flags & FLAG_C) != 0)
1038		{
1039			temp_word++;
1040		}
1041		if (temp_word >= 0x100)
1042		{
1043			Flags = Flags | FLAG_C;
1044		}
1045		else
1046		{
1047			Flags = Flags & (0xFF - FLAG_C);
1048		}
1049		set_flag_n((BYTE)temp_word);
1050		set_flag_z((BYTE)temp_word);
1051		Registers[REGISTER_A] = (BYTE)temp_word;
1052		break;
1053
1054	case 0xB8://ADD A,B
1055		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_B];
1056		if (temp_word >= 0x100)
1057		{
1058			Flags = Flags | FLAG_C;
1059		}
1060		else
1061		{
1062			Flags = Flags & (0xFF - FLAG_C);
1063		}
1064		set_flag_n((BYTE)temp_word);
1065		set_flag_z((BYTE)temp_word);
1066		Registers[REGISTER_A] = (BYTE)temp_word;
1067		break;
1068
1069	case 0xC8://ADD A,C
1070		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_C];
1071		if (temp_word >= 0x100)
1072		{
1073			Flags = Flags | FLAG_C;
1074		}
1075		else
1076		{
1077			Flags = Flags & (0xFF - FLAG_C);
1078		}
1079		set_flag_n((BYTE)temp_word);
1080		set_flag_z((BYTE)temp_word);
1081		Registers[REGISTER_A] = (BYTE)temp_word;
1082		break;
1083
1084	case 0xD8://ADD A,L
1085		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_L];
1086		if (temp_word >= 0x100)
1087		{
1088			Flags = Flags | FLAG_C;
1089		}
1090		else
1091		{
1092			Flags = Flags & (0xFF - FLAG_C);
1093		}
1094		set_flag_n((BYTE)temp_word);
1095		set_flag_z((BYTE)temp_word);
1096		Registers[REGISTER_A] = (BYTE)temp_word;
1097		break;
1098
1099	case 0xE8://ADD A,H
1100		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_H];
1101		if (temp_word >= 0x100)
1102		{
1103			Flags = Flags | FLAG_C;
1104		}
1105		else
1106		{
1107			Flags = Flags & (0xFF - FLAG_C);
1108		}
1109		set_flag_n((BYTE)temp_word);
1110		set_flag_z((BYTE)temp_word);
1111		Registers[REGISTER_A] = (BYTE)temp_word;
1112		break;
1113
1114	case 0xF8://ADD A,M
1115		temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_M];
1116		if (temp_word >= 0x100)
1117		{
1118			Flags = Flags | FLAG_C;
1119		}
1120		else
1121		{
1122			Flags = Flags & (0xFF - FLAG_C);
1123		}
1124		set_flag_n((BYTE)temp_word);
1125		set_flag_z((BYTE)temp_word);
1126		Registers[REGISTER_A] = (BYTE)temp_word;
1127		break;
1128
1129	case 0xBA://CMP A,B
1130		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_B];
1131		if (temp_word >= 0x100) {
1132			Flags = Flags | FLAG_C; // Set carry flag
1133		}
1134		else {
1135			Flags = Flags & (0xFF - FLAG_C); // Clear carry flag
1136		}
1137		set_flag_n((BYTE)temp_word);
1138		set_flag_z((BYTE)temp_word);
1139		break;
1140
1141	case 0xCA://CMP A,C
1142		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_C];
1143		if (temp_word >= 0x100) {
1144			Flags = Flags | FLAG_C; // Set carry flag
1145		}
1146		else {
1147			Flags = Flags & (0xFF - FLAG_C); // Clear carry flag
1148		}
1149		set_flag_n((BYTE)temp_word);
1150		set_flag_z((BYTE)temp_word);
1151		break;
1152
1153	case 0xDA://CMP A,L
1154		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_L];
1155		if (temp_word >= 0x100) {
1156			Flags = Flags | FLAG_C; // Set carry flag
1157		}
1158		else {
1159			Flags = Flags & (0xFF - FLAG_C); // Clear carry flag
1160		}
1161		set_flag_n((BYTE)temp_word);
1162		set_flag_z((BYTE)temp_word);
1163		break;
1164
1165	case 0xEA://CMP A,H
1166		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_H];
1167		if (temp_word >= 0x100)
1168		{
1169			Flags = Flags | FLAG_C; // Set carry flag
1170		}
1171		else
1172		{
1173			Flags = Flags & (0xFF - FLAG_C); // Clear carry flag
1174		}
1175		set_flag_n((BYTE)temp_word);
1176		set_flag_z((BYTE)temp_word);
1177		break;
1178
1179	case 0xFA://CMP A,M
1180		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_M];
1181		if (temp_word >= 0x100)
1182		{
1183			Flags = Flags | FLAG_C; // Set carry flag
1184		}
1185		else
1186		{
1187			Flags = Flags & (0xFF - FLAG_C); // Clear carry flag
1188		}
1189		set_flag_n((BYTE)temp_word);
1190		set_flag_z((BYTE)temp_word);
1191		break;
1192
1193	case 0x2D://MSA
1194		Registers[REGISTER_A] = Flags;
1195		break;
1196
1197	case 0x2B://TAY
1198		Index_Registers[REGISTER_Y] = Registers[REGISTER_A];
1199		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
1200		break;
1201
1202	case 0x2C://TYA
1203		Registers[REGISTER_A] = Index_Registers[REGISTER_Y];
1204		set_flag_n((BYTE)Index_Registers[REGISTER_Y]);
1205		set_flag_z((BYTE)Index_Registers[REGISTER_Y]);
1206		break;
1207
1208	case 0xA6://CLC
1209		Flags = Flags & (0xFF - FLAG_C);
1210		break;
1211
1212	case 0xA7://SEC
1213		Flags = Flags | FLAG_C;
1214		break;
1215
1216	case 0xA8://CLI
1217		Flags = Flags & (0xFF - FLAG_I);
1218		break;
1219
1220	case 0xA9://SEI
1221		Flags = Flags | FLAG_I;
1222		break;
1223
1224	case 0xAA://CMC
1225		Flags = Flags ^ FLAG_C;
1226		break;
1227
1228	case 0xAE://PUSH REGISTER A
1229		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1230			StackPointer--;
1231			Memory[StackPointer] = Registers[REGISTER_A];
1232		}
1233		break;
1234
1235	case 0xBE://PUSH FLAGS
1236		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1237			StackPointer--;
1238			Memory[StackPointer] = Flags;
1239		}
1240		break;
1241
1242	case 0xCE://PUSH REGISTER B
1243		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1244			StackPointer--;
1245			Memory[StackPointer] = Registers[REGISTER_B];
1246		}
1247		break;
1248
1249	case 0xDE://PUSH REGISTER C
1250		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1251			StackPointer--;
1252			Memory[StackPointer] = Registers[REGISTER_C];
1253		}
1254		break;
1255
1256	case 0xEE://PUSH REGISTER L
1257		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1258			StackPointer--;
1259			Memory[StackPointer] = Registers[REGISTER_L];
1260		}
1261		break;
1262
1263	case 0xFE://PUSH REGISTER H
1264		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1265			StackPointer--;
1266			Memory[StackPointer] = Registers[REGISTER_H];
1267		}
1268		break;
1269
1270	case 0xAF://POP REGISTER A
1271		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1272			Registers[REGISTER_A] = Memory[StackPointer];
1273			StackPointer++;
1274		}
1275		break;
1276
1277	case 0xBF://POP FLAGS
1278		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1279			Flags = Memory[StackPointer];
1280			StackPointer++;
1281		}
1282		break;
1283
1284	case 0xCF://POP REGISTER B
1285		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1286			Registers[REGISTER_B] = Memory[StackPointer];
1287			StackPointer++;
1288		}
1289		break;
1290
1291	case 0xDF://POP REGISTER C
1292		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1293			Registers[REGISTER_C] = Memory[StackPointer];
1294			StackPointer++;
1295		}
1296		break;
1297
1298	case 0xEF://POP REGISTER L
1299		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1300			Registers[REGISTER_L] = Memory[StackPointer];
1301			StackPointer++;
1302		}
1303		break;
1304
1305	case 0xFF://POP REGISTER H
1306		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1307			Registers[REGISTER_H] = Memory[StackPointer];
1308			StackPointer++;
1309		}
1310		break;
1311
1312	case 0x38: //JUMP abs
1313		LB = fetch();
1314		HB = fetch();
1315		address = ((WORD)HB << 8) + (WORD)LB;
1316		ProgramCounter = address;
1317		break;
1318
1319	case 0x07://JMPR abs
1320		HB = fetch();
1321		LB = fetch();
1322		if ((StackPointer >= 2) && (StackPointer < MEMORY_SIZE)) {
1323			StackPointer--;
1324			Memory[StackPointer] = (BYTE)((ProgramCounter >> 8) & 0xFF);
1325			StackPointer--;
1326			Memory[StackPointer] = (BYTE)(ProgramCounter & 0xFF);
1327			ProgramCounter = address;
1328		}
1329		break;
1330
1331	case 0x23: //RT impl
1332		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 2)) {
1333			LB = Memory[StackPointer];
1334			StackPointer++;
1335			HB = Memory[StackPointer];
1336			StackPointer++;
1337			ProgramCounter = ((WORD)HB << 8) + (WORD)LB;
1338		}
1339		break;
1340
1341	case 0x39://JCC
1342		LB = fetch();
1343		HB = fetch();
1344		address = ((WORD)HB << 8) + (WORD)LB;
1345		if ((Flags & FLAG_C) == 0)
1346		{
1347			ProgramCounter = address;
1348		}
1349		break;
1350
1351	case 0x3A://JCS
1352		LB = fetch();
1353		HB = fetch();
1354		address = ((WORD)HB << 8) + (WORD)LB;
1355		if ((Flags & FLAG_C) == FLAG_C)
1356		{
1357			ProgramCounter = address;
1358		}
1359		break;
1360
1361	case 0x3B://JNE abs
1362		LB = fetch();
1363		HB = fetch();
1364		address = ((WORD)HB << 8) + (WORD)LB;
1365		if ((Flags & FLAG_Z) == 0)
1366		{
1367			ProgramCounter = address;
1368		}
1369		break;
1370
1371	case 0x3C://JEQ
1372		LB = fetch();
1373		HB = fetch();
1374		address = ((WORD)HB << 8) + (WORD)LB;
1375		if ((Flags & FLAG_Z) == FLAG_Z)
1376		{
1377			ProgramCounter = address;
1378		}
1379		break;
1380
1381	case 0x3D://JMI abs
1382		LB = fetch();
1383		HB = fetch();
1384		address = ((WORD)HB << 8) + (WORD)LB;
1385		if ((Flags & FLAG_N) == FLAG_N)
1386		{
1387			ProgramCounter = address;
1388		}
1389		break;
1390
1391	case 0x3E://JPL abs
1392		LB = fetch();
1393		HB = fetch();
1394		address = ((WORD)HB << 8) + (WORD)LB;
1395		if ((Flags & FLAG_N) == 0)
1396		{
1397			ProgramCounter = address;
1398		}
1399		break;
1400
1401	case 0x08: //CCC abs
1402		LB = fetch();
1403		HB = fetch();
1404		address = ((WORD)HB << 8) + (WORD)LB;
1405		if ((Flags & FLAG_C) == 0)
1406		{
1407			if ((StackPointer >= 2) && (StackPointer < MEMORY_SIZE)) {
1408				StackPointer--;
1409				Memory[StackPointer] = (BYTE)((ProgramCounter >> 8) & 0xFF);
1410				StackPointer--;
1411				Memory[StackPointer] = (BYTE)(ProgramCounter & 0xFF);
1412				ProgramCounter = address;
1413			}
1414		}
1415		break;
1416
1417	case 0x09:// CCS abs
1418		LB = fetch();
1419		HB = fetch();
1420		address = ((WORD)HB << 8) + (WORD)LB;
1421		if ((Flags & FLAG_C) == FLAG_C)
1422		{
1423			if ((StackPointer >= 2) && (StackPointer < MEMORY_SIZE)) {
1424				StackPointer--;
1425				Memory[StackPointer] = (BYTE)((ProgramCounter >> 8) & 0xFF);
1426				StackPointer--;
1427				Memory[StackPointer] = (BYTE)(ProgramCounter & 0xFF);
1428				ProgramCounter = address;
1429			}
1430		}
1431		break;
1432
1433	case 0x0A: //CNE abs
1434		LB = fetch();
1435		HB = fetch();
1436		address = ((WORD)HB << 8) + (WORD)LB;
1437		if ((Flags & FLAG_Z) == 0)
1438		{
1439			if ((StackPointer >= 2) && (StackPointer < MEMORY_SIZE)) {
1440				StackPointer--;
1441				Memory[StackPointer] = (BYTE)((ProgramCounter >> 8) & 0xFF);
1442				StackPointer--;
1443				Memory[StackPointer] = (BYTE)(ProgramCounter & 0xFF);
1444				ProgramCounter = address;
1445			}
1446		}
1447		break;
1448
1449	case 0x0B:// CEQ abs
1450		LB = fetch();
1451		HB = fetch();
1452		address = ((WORD)HB << 8) + (WORD)LB;
1453		if ((Flags & FLAG_Z) == FLAG_Z)
1454		{
1455			if ((StackPointer >= 2) && (StackPointer < MEMORY_SIZE)) {
1456				StackPointer--;
1457				Memory[StackPointer] = (BYTE)((ProgramCounter >> 8) & 0xFF);
1458				StackPointer--;
1459				Memory[StackPointer] = (BYTE)(ProgramCounter & 0xFF);
1460				ProgramCounter = address;
1461			}
1462		}
1463		break;
1464
1465	case 0x0C: //CMI abs
1466		LB = fetch();
1467		HB = fetch();
1468		address = ((WORD)HB << 8) + (WORD)LB;
1469		if ((Flags & FLAG_N) == FLAG_N)
1470		{
1471			if ((StackPointer >= 2) && (StackPointer < MEMORY_SIZE)) {
1472				StackPointer--;
1473				Memory[StackPointer] = (BYTE)((ProgramCounter >> 8) & 0xFF);
1474				StackPointer--;
1475				Memory[StackPointer] = (BYTE)(ProgramCounter & 0xFF);
1476				ProgramCounter = address;
1477			}
1478		}
1479		break;
1480
1481	case 0x0D: // CPL abs
1482		LB = fetch();
1483		HB = fetch();
1484		address = ((WORD)HB << 8) + (WORD)LB;
1485		if ((Flags & FLAG_N) == 0)
1486		{
1487			if ((StackPointer >= 2) && (StackPointer < MEMORY_SIZE)) {
1488				StackPointer--;
1489				Memory[StackPointer] = (BYTE)((ProgramCounter >> 8) & 0xFF);
1490				StackPointer--;
1491				Memory[StackPointer] = (BYTE)(ProgramCounter & 0xFF);
1492				ProgramCounter = address;
1493			}
1494		}
1495		break;
1496
1497	case 0x95: //INCA
1498		++Registers[REGISTER_A];
1499		set_flag_n(Registers[REGISTER_A]);
1500		set_flag_z(Registers[REGISTER_A]);
1501		break;
1502
1503	case 0xBC: // AND Register A,B
1504		temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_B];
1505		set_flag_n((BYTE)temp_word);
1506		set_flag_z((BYTE)temp_word);
1507		Registers[REGISTER_A] = (BYTE)temp_word;
1508		break;
1509
1510	case 0xCC: // AND Register A,C
1511		temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_C];
1512		set_flag_n((BYTE)temp_word);
1513		set_flag_z((BYTE)temp_word);
1514		Registers[REGISTER_A] = (BYTE)temp_word;
1515		break;
1516
1517	case 0xDC: // AND Register A,L
1518		temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_L];
1519		set_flag_n((BYTE)temp_word);
1520		set_flag_z((BYTE)temp_word);
1521		Registers[REGISTER_A] = (BYTE)temp_word;
1522		break;
1523
1524	case 0xEC: // AND Register A,H
1525		temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_H];
1526		set_flag_n((BYTE)temp_word);
1527		set_flag_z((BYTE)temp_word);
1528		Registers[REGISTER_A] = (BYTE)temp_word;
1529		break;
1530
1531	case 0xFC: // AND Register A,M
1532		temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_M];
1533		set_flag_n((BYTE)temp_word);
1534		set_flag_z((BYTE)temp_word);
1535		Registers[REGISTER_A] = (BYTE)temp_word;
1536		break;
1537
1538	case 0x9F: //CLRA
1539		Registers[REGISTER_A] = 0;
1540		Flags = Flags | FLAG_Z;
1541		Flags = Flags & (0xFF - FLAG_N);
1542		Flags = Flags & (0xFF - FLAG_C);
1543		break;
1544
1545	case 0x55: // INC abs
1546		LB = fetch();
1547		HB = fetch();
1548		address += (WORD)((WORD)HB << 8) + LB;
1549		++Memory[address];
1550		set_flag_n(Memory[address]);
1551		set_flag_z(Memory[address]);
1552		break;
1553
1554	case 0x65: // INC abs X
1555		address += Index_Registers[REGISTER_X];
1556		LB = fetch();
1557		HB = fetch();
1558		address += (WORD)((WORD)HB << 8) + LB;
1559		if (address >= 0 && address < MEMORY_SIZE)
1560		{
1561			++Memory[address];
1562		}
1563		set_flag_n(Memory[address]);
1564		set_flag_z(Memory[address]);
1565		break;
1566
1567	case 0x75: // INC abs Y
1568		address += Index_Registers[REGISTER_Y];
1569		LB = fetch();
1570		HB = fetch();
1571		address += (WORD)((WORD)HB << 8) + LB;
1572		if (address >= 0 && address < MEMORY_SIZE)
1573		{
1574			++Memory[address];
1575		}
1576		set_flag_n(Memory[address]);
1577		set_flag_z(Memory[address]);
1578		break;
1579
1580	case 0x85: // INC abs XY
1581		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1582		LB = fetch();
1583		HB = fetch();
1584		address += (WORD)((WORD)HB << 8) + LB;
1585		if (address >= 0 && address < MEMORY_SIZE)
1586		{
1587			++Memory[address];
1588		}
1589		set_flag_n(Memory[address]);
1590		set_flag_z(Memory[address]);
1591		break;
1592
1593	case 0x5F: // CLR abs
1594		LB = fetch();
1595		HB = fetch();
1596		address += (WORD)((WORD)HB << 8) + LB;
1597		Memory[address] = 0;
1598		Flags = Flags | FLAG_Z;
1599		Flags = Flags & (0xFF - FLAG_N);
1600		Flags = Flags & (0xFF - FLAG_C);
1601		break;
1602
1603	case 0x6F: // CLR abs X
1604		address += Index_Registers[REGISTER_X];
1605		LB = fetch();
1606		HB = fetch();
1607		address += (WORD)((WORD)HB << 8) + LB;
1608		Memory[address] = 0;
1609		Flags = Flags | FLAG_Z;
1610		Flags = Flags & (0xFF - FLAG_N);
1611		Flags = Flags & (0xFF - FLAG_C);
1612		break;
1613
1614	case 0x7F: // CLR abs Y
1615		address += Index_Registers[REGISTER_Y];
1616		LB = fetch();
1617		HB = fetch();
1618		address += (WORD)((WORD)HB << 8) + LB;
1619		Memory[address] = 0;
1620		Flags = Flags | FLAG_Z;
1621		Flags = Flags & (0xFF - FLAG_N);
1622		Flags = Flags & (0xFF - FLAG_C);
1623		break;
1624
1625	case 0x8F: // CLR abs XY
1626		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1627		LB = fetch();
1628		HB = fetch();
1629		address += (WORD)((WORD)HB << 8) + LB;
1630		Memory[address] = 0;
1631		Flags = Flags | FLAG_Z;
1632		Flags = Flags & (0xFF - FLAG_N);
1633		Flags = Flags & (0xFF - FLAG_C);
1634		break;
1635
1636	case 0x4A: // DEX imply
1637		Index_Registers[REGISTER_X]--;
1638		set_flag_z(Index_Registers[REGISTER_X]);
1639		break;
1640
1641	case 0x4B: //INX impl
1642		++Index_Registers[REGISTER_X];
1643		set_flag_z(Index_Registers[REGISTER_X]);
1644		break;
1645
1646	case 0x4C: //DEY impl
1647		Index_Registers[REGISTER_Y]--;
1648		set_flag_z(Index_Registers[REGISTER_Y]);
1649		break;
1650
1651	case 0x4D: //INY impl
1652		++Index_Registers[REGISTER_Y];
1653		set_flag_z(Index_Registers[REGISTER_Y]);
1654		break;
1655
1656	case 0xB7: //SBC A,B
1657		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_B];
1658		if ((Flags & FLAG_C) != 0)
1659		{
1660			temp_word--;
1661		}
1662		if (temp_word >= 0x100)
1663		{
1664			Flags = Flags | FLAG_C;
1665		}
1666		else
1667		{
1668			Flags = Flags & (0xFF - FLAG_C);
1669		}
1670		set_flag_n((BYTE)temp_word);
1671		set_flag_z((BYTE)temp_word);
1672		Registers[REGISTER_A] = (BYTE)temp_word;
1673		break;
1674
1675	case 0xC7: //SBC A,C
1676		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_C];
1677		if ((Flags & FLAG_C) != 0)
1678		{
1679			temp_word--;
1680		}
1681		if (temp_word >= 0x100)
1682		{
1683			Flags = Flags | FLAG_C;
1684		}
1685		else
1686		{
1687			Flags = Flags & (0xFF - FLAG_C);
1688		}
1689		set_flag_n((BYTE)temp_word);
1690		set_flag_z((BYTE)temp_word);
1691		Registers[REGISTER_A] = (BYTE)temp_word;
1692		break;
1693
1694	case 0xD7: //SBC A,L
1695		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_L];
1696		if ((Flags & FLAG_C) != 0)
1697		{
1698			temp_word--;
1699		}
1700		if (temp_word >= 0x100)
1701		{
1702			Flags = Flags | FLAG_C;
1703		}
1704		else
1705		{
1706			Flags = Flags & (0xFF - FLAG_C);
1707		}
1708		set_flag_n((BYTE)temp_word);
1709		set_flag_z((BYTE)temp_word);
1710		Registers[REGISTER_A] = (BYTE)temp_word;
1711		break;
1712
1713	case 0xE7: //SBC A,H
1714		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_H];
1715		if ((Flags & FLAG_C) != 0)
1716		{
1717			temp_word--;
1718		}
1719		if (temp_word >= 0x100)
1720		{
1721			Flags = Flags | FLAG_C;
1722		}
1723		else
1724		{
1725			Flags = Flags & (0xFF - FLAG_C);
1726		}
1727		set_flag_n((BYTE)temp_word);
1728		set_flag_z((BYTE)temp_word);
1729		Registers[REGISTER_A] = (BYTE)temp_word;
1730		break;
1731
1732	case 0xF7: //SBC A,M
1733		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_M];
1734		if ((Flags & FLAG_C) != 0)
1735		{
1736			temp_word--;
1737		}
1738		if (temp_word >= 0x100)
1739		{
1740			Flags = Flags | FLAG_C;
1741		}
1742		else
1743		{
1744			Flags = Flags & (0xFF - FLAG_C);
1745		}
1746		set_flag_n((BYTE)temp_word);
1747		set_flag_z((BYTE)temp_word);
1748		Registers[REGISTER_A] = (BYTE)temp_word;
1749		break;
1750
1751	case 0xBB: //OR A,B
1752		temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_B];
1753		set_flag_n((BYTE)temp_word);
1754		set_flag_z((BYTE)temp_word);
1755		Registers[REGISTER_A] = (BYTE)temp_word;
1756		break;
1757
1758	case 0xCB: //OR A,C
1759		temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_C];
1760		set_flag_n((BYTE)temp_word);
1761		set_flag_z((BYTE)temp_word);
1762		Registers[REGISTER_A] = (BYTE)temp_word;
1763		break;
1764
1765	case 0xDB: //OR A,L
1766		temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_L];
1767		set_flag_n((BYTE)temp_word);
1768		set_flag_z((BYTE)temp_word);
1769		Registers[REGISTER_A] = (BYTE)temp_word;
1770		break;
1771
1772	case 0xEB: //OR A,H
1773		temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_H];
1774		set_flag_n((BYTE)temp_word);
1775		set_flag_z((BYTE)temp_word);
1776		Registers[REGISTER_A] = (BYTE)temp_word;
1777		break;
1778
1779	case 0xFB: //OR A,M
1780		temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_M];
1781		set_flag_n((BYTE)temp_word);
1782		set_flag_z((BYTE)temp_word);
1783		Registers[REGISTER_A] = (BYTE)temp_word;
1784		break;
1785
1786	case 0x9B: //COMA
1787		Registers[REGISTER_A] = Registers[REGISTER_A] ^ 0xFF;
1788		Flags = Flags | FLAG_C;
1789		set_flag_n(Registers[REGISTER_A]);
1790		set_flag_z(Registers[REGISTER_A]);
1791		break;
1792
1793	case 0xB9: //SUB A,B
1794		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_B];
1795		if (temp_word >= 0x100)
1796		{
1797			Flags = Flags | FLAG_C;
1798		}
1799		else
1800		{
1801			Flags = Flags & (0xFF - FLAG_C);
1802		}
1803		set_flag_n((BYTE)temp_word);
1804		set_flag_z((BYTE)temp_word);
1805		Registers[REGISTER_A] = (BYTE)temp_word;
1806		break;
1807
1808	case 0xC9: //SUB A,C
1809		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_C];
1810		if (temp_word >= 0x100)
1811		{
1812			Flags = Flags | FLAG_C;
1813		}
1814		else
1815		{
1816			Flags = Flags & (0xFF - FLAG_C);
1817		}
1818		set_flag_n((BYTE)temp_word);
1819		set_flag_z((BYTE)temp_word);
1820		Registers[REGISTER_A] = (BYTE)temp_word;
1821		break;
1822
1823	case 0xD9: //SUB A,L
1824		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_L];
1825		if (temp_word >= 0x100)
1826		{
1827			Flags = Flags | FLAG_C;
1828		}
1829		else
1830		{
1831			Flags = Flags & (0xFF - FLAG_C);
1832		}
1833		set_flag_n((BYTE)temp_word);
1834		set_flag_z((BYTE)temp_word);
1835		Registers[REGISTER_A] = (BYTE)temp_word;
1836		break;
1837
1838	case 0xE9: //SUB A,H
1839		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_H];
1840		if (temp_word >= 0x100)
1841		{
1842			Flags = Flags | FLAG_C;
1843		}
1844		else
1845		{
1846			Flags = Flags & (0xFF - FLAG_C);
1847		}
1848		set_flag_n((BYTE)temp_word);
1849		set_flag_z((BYTE)temp_word);
1850		Registers[REGISTER_A] = (BYTE)temp_word;
1851		break;
1852
1853	case 0xF9: //SUB A,C
1854		temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_M];
1855		if (temp_word >= 0x100)
1856		{
1857			Flags = Flags | FLAG_C;
1858		}
1859		else
1860		{
1861			Flags = Flags & (0xFF - FLAG_C);
1862		}
1863		set_flag_n((BYTE)temp_word);
1864		set_flag_z((BYTE)temp_word);
1865		Registers[REGISTER_A] = (BYTE)temp_word;
1866		break;
1867
1868	case 0xBD: //XOR A,B
1869		temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_B];
1870		set_flag_n((BYTE)temp_word);
1871		set_flag_z((BYTE)temp_word);
1872		Registers[REGISTER_A] = (BYTE)temp_word;
1873		break;
1874
1875	case 0xCD: //XOR A,C
1876		temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_C];
1877		set_flag_n((BYTE)temp_word);
1878		set_flag_z((BYTE)temp_word);
1879		Registers[REGISTER_A] = (BYTE)temp_word;
1880		break;
1881
1882	case 0xDD: //XOR A,L
1883		temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_L];
1884		set_flag_n((BYTE)temp_word);
1885		set_flag_z((BYTE)temp_word);
1886		Registers[REGISTER_A] = (BYTE)temp_word;
1887		break;
1888
1889	case 0xED: //XOR A,H
1890		temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_H];
1891		set_flag_n((BYTE)temp_word);
1892		set_flag_z((BYTE)temp_word);
1893		Registers[REGISTER_A] = (BYTE)temp_word;
1894		break;
1895
1896	case 0xFD: //XOR A,M
1897		temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_M];
1898		set_flag_n((BYTE)temp_word);
1899		set_flag_z((BYTE)temp_word);
1900		Registers[REGISTER_A] = (BYTE)temp_word;
1901		break;
1902
1903	case 0x54: //TEST Absolute
1904		LB = fetch();
1905		HB = fetch();
1906		address += (WORD)((WORD)HB << 8) + LB;
1907		data = Memory[address];
1908		set_flag_n(data);
1909		set_flag_z(data);
1910		break;
1911
1912	case 0x64: //TEST Absolute X
1913		address += Index_Registers[REGISTER_X];
1914		LB = fetch();
1915		HB = fetch();
1916		address += (WORD)((WORD)HB << 8) + LB;
1917		data = Memory[address];
1918		set_flag_n(data);
1919		set_flag_z(data);
1920		break;
1921
1922	case 0x74: //TEST Absolute Y
1923		address += Index_Registers[REGISTER_Y];
1924		LB = fetch();
1925		HB = fetch();
1926		address += (WORD)((WORD)HB << 8) + LB;
1927		data = Memory[address];
1928		set_flag_n(data);
1929		set_flag_z(data);
1930		break;
1931
1932	case 0x84: //TEST Absolute X,Y
1933		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1934		LB = fetch();
1935		HB = fetch();
1936		address += (WORD)((WORD)HB << 8) + LB;
1937		data = Memory[address];
1938		set_flag_n(data);
1939		set_flag_z(data);
1940		break;
1941
1942	case 0x56: //DEC Absolute
1943		LB = fetch();
1944		HB = fetch();
1945		address += (WORD)((WORD)HB << 8) + LB;
1946		Memory[address]--;
1947		set_flag_n(Memory[address]);
1948		set_flag_z(Memory[address]);
1949		break;
1950
1951	case 0x66: //DEC Absolute X
1952		address += Index_Registers[REGISTER_X];
1953		LB = fetch();
1954		HB = fetch();
1955		address += (WORD)((WORD)HB << 8) + LB;
1956		if (address >= 0 && address < MEMORY_SIZE)
1957		{
1958			Memory[address]--;
1959		}
1960		set_flag_n(Memory[address]);
1961		set_flag_z(Memory[address]);
1962		break;
1963
1964	case 0x76: //DEC Absolute Y
1965		address += Index_Registers[REGISTER_Y];
1966		LB = fetch();
1967		HB = fetch();
1968		address += (WORD)((WORD)HB << 8) + LB;
1969		if (address >= 0 && address < MEMORY_SIZE)
1970		{
1971			Memory[address]--;
1972		}
1973		set_flag_n(Memory[address]);
1974		set_flag_z(Memory[address]);
1975		break;
1976
1977	case 0x86: //DEC Absolute X,Y
1978		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1979		LB = fetch();
1980		HB = fetch();
1981		address += (WORD)((WORD)HB << 8) + LB;
1982		if (address >= 0 && address < MEMORY_SIZE)
1983		{
1984			Memory[address]--;
1985		}
1986		set_flag_n(Memory[address]);
1987		set_flag_z(Memory[address]);
1988		break;
1989
1990	case 0x59: //SAL Absolute
1991		LB = fetch();
1992		HB = fetch();
1993		address = (WORD)((WORD)HB << 8) + LB;
1994		saved_flags = Flags;
1995
1996		if ((Memory[address] & 0x80) == 0x80) {
1997			Flags = Flags | FLAG_C;
1998		}
1999		else {
2000			Flags = Flags & (0xFF - FLAG_C);
2001		}
2002
2003		Memory[address] = (Memory[address] << 1) & 0xFE;
2004		
2005		set_flag_n(Memory[address]);
2006		set_flag_z(Memory[address]);
2007		break;
2008
2009	case 0x69: //SAL Absolute X
2010		address += Index_Registers[REGISTER_X];
2011		LB = fetch();
2012		HB = fetch();
2013		address = (WORD)((WORD)HB << 8) + LB;
2014		saved_flags = Flags;
2015
2016		if ((Memory[address] & 0x80) == 0x80) {
2017			Flags = Flags | FLAG_C;
2018		}
2019		else {
2020			Flags = Flags & (0xFF - FLAG_C);
2021		}
2022
2023		Memory[address] = (Memory[address] << 1) & 0xFE;
2024
2025		set_flag_n(Memory[address]);
2026		set_flag_z(Memory[address]);
2027		break;
2028
2029	case 0x79: //SAL Absolute Y
2030		address += Index_Registers[REGISTER_Y];
2031		LB = fetch();
2032		HB = fetch();
2033		address = (WORD)((WORD)HB << 8) + LB;
2034		saved_flags = Flags;
2035
2036		if ((Memory[address] & 0x80) == 0x80) {
2037			Flags = Flags | FLAG_C;
2038		}
2039		else {
2040			Flags = Flags & (0xFF - FLAG_C);
2041		}
2042
2043		Memory[address] = (Memory[address] << 1) & 0xFE;
2044
2045		set_flag_n(Memory[address]);
2046		set_flag_z(Memory[address]);
2047		break;
2048
2049	case 0x89: //SAL Absolute X,Y
2050		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2051		LB = fetch();
2052		HB = fetch();
2053		address = (WORD)((WORD)HB << 8) + LB;
2054		saved_flags = Flags;
2055
2056		if ((Memory[address] & 0x80) == 0x80) {
2057			Flags = Flags | FLAG_C;
2058		}
2059		else {
2060			Flags = Flags & (0xFF - FLAG_C);
2061		}
2062
2063		Memory[address] = (Memory[address] << 1) & 0xFE;
2064
2065		set_flag_n(Memory[address]);
2066		set_flag_z(Memory[address]);
2067		break;
2068
2069	case 0x5A: //SHR Absolute
2070		LB = fetch();
2071		HB = fetch();
2072		address = (WORD)((WORD)HB << 8) + LB;
2073		if ((Memory[address] & 0x01) == 0x01) {
2074			Flags = Flags | FLAG_C;
2075		}
2076		else {
2077			Flags = Flags & (0xFF - FLAG_C);
2078		}
2079		Memory[address] = (Memory[address] >> 1) & 0x7F;
2080
2081		set_flag_n(Memory[address]);
2082		set_flag_z(Memory[address]);
2083		break;
2084
2085	case 0x6A: //SHR Absolute X
2086		address += Index_Registers[REGISTER_X];
2087		LB = fetch();
2088		HB = fetch();
2089		address = (WORD)((WORD)HB << 8) + LB;
2090		if ((Memory[address] & 0x01) == 0x01) {
2091			Flags = Flags | FLAG_C;
2092		}
2093		else {
2094			Flags = Flags & (0xFF - FLAG_C);
2095		}
2096		Memory[address] = (Memory[address] >> 1) & 0x7F;
2097		set_flag_n((BYTE)Memory[address]);
2098		set_flag_z((BYTE)Memory[address]);
2099		break;
2100
2101	case 0x7A: //SHR Absolute Y
2102		address += Index_Registers[REGISTER_Y];
2103		LB = fetch();
2104		HB = fetch();
2105		address = (WORD)((WORD)HB << 8) + LB;
2106		if ((Memory[address] & 0x01) == 0x01) {
2107			Flags = Flags | FLAG_C;
2108		}
2109		else {
2110			Flags = Flags & (0xFF - FLAG_C);
2111		}
2112		Memory[address] = (Memory[address] >> 1) & 0x7F;
2113		set_flag_n((BYTE)Memory[address]);
2114		set_flag_z((BYTE)Memory[address]);
2115
2116		break;
2117
2118	case 0x8A: //SHR Absolute X,Y
2119		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2120		LB = fetch();
2121		HB = fetch();
2122		address = (WORD)((WORD)HB << 8) + LB;
2123		if ((Memory[address] & 0x01) == 0x01) {
2124			Flags = Flags | FLAG_C;
2125		}
2126		else {
2127			Flags = Flags & (0xFF - FLAG_C);
2128		}
2129		Memory[address] = (Memory[address] >> 1) & 0x7F;
2130		set_flag_n((BYTE)Memory[address]);
2131		set_flag_z((BYTE)Memory[address]);
2132		break;
2133
2134	case 0x5C: //NEG Absolute
2135		LB = fetch();
2136		HB = fetch();
2137		address += (WORD)((WORD)HB << 8) + LB;
2138		Memory[address] = 0 - Memory[address];
2139		set_flag_n(Memory[address]);
2140		set_flag_z(Memory[address]);
2141		break;
2142
2143	case 0x6C: //NEG Absolute X
2144		address += Index_Registers[REGISTER_X];
2145
2146		LB = fetch();
2147		HB = fetch();
2148		address += (WORD)((WORD)HB << 8) + LB;
2149		Memory[address] = 0 - Memory[address];
2150		set_flag_n(Memory[address]);
2151		set_flag_z(Memory[address]);
2152		break;
2153
2154	case 0x7C: //NEG Absolute Y
2155		address += Index_Registers[REGISTER_Y];
2156
2157		LB = fetch();
2158		HB = fetch();
2159		address += (WORD)((WORD)HB << 8) + LB;
2160		
2161		Memory[address] = 0 - Memory[address];
2162		set_flag_n(Memory[address]);
2163		set_flag_z(Memory[address]);
2164		break;
2165
2166	case 0x8C: //NEG Absolute X,Y
2167		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2168		LB = fetch();
2169		HB = fetch();
2170		address += (WORD)((WORD)HB << 8) + LB;
2171		Memory[address] = 0 - Memory[address];
2172		
2173		set_flag_n(Memory[address]);
2174		set_flag_z(Memory[address]);
2175		break;
2176
2177	case 0x02: //SWI (IMPL)
2178		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
2179			StackPointer--;
2180			Memory[StackPointer] = Registers[REGISTER_A];
2181		}
2182		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
2183			StackPointer--;
2184			Memory[StackPointer] = (BYTE)ProgramCounter;
2185		}
2186		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
2187			StackPointer--;
2188			Memory[StackPointer] = (BYTE)(ProgramCounter >> 8);
2189		}
2190		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
2191			StackPointer--;
2192			Memory[StackPointer] = Flags;
2193		}
2194		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
2195			StackPointer--;
2196			Memory[StackPointer] = Registers[REGISTER_B];
2197		}
2198		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
2199			StackPointer--;
2200			Memory[StackPointer] = Registers[REGISTER_C];
2201		}
2202		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
2203			StackPointer--;
2204			Memory[StackPointer] = Registers[REGISTER_L];
2205		}
2206		if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
2207			StackPointer--;
2208			Memory[StackPointer] = Registers[REGISTER_H];
2209		}
2210		
2211		break;
2212
2213	case 0x03: //RTI (IMPL)
2214		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
2215			Registers[REGISTER_H] = Memory[StackPointer];
2216			StackPointer++;
2217		}
2218		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
2219			Registers[REGISTER_L] = Memory[StackPointer];
2220			StackPointer++;
2221		}
2222		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
2223			Registers[REGISTER_C] = Memory[StackPointer];
2224			StackPointer++;
2225		}
2226		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
2227			Registers[REGISTER_B] = Memory[StackPointer];
2228			StackPointer++;
2229		}
2230		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
2231			Flags = Memory[StackPointer];
2232			StackPointer++;
2233		}
2234		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
2235			ProgramCounter = (WORD)(Memory[StackPointer] <<8);
2236			StackPointer++;
2237		}
2238		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
2239			ProgramCounter += Memory[StackPointer];
2240			StackPointer++;
2241		}
2242		if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
2243			Registers[REGISTER_A] = Memory[StackPointer];
2244			StackPointer++;
2245		}
2246		break;
2247
2248	case 0x98: //RCLA
2249		saved_flags = Flags;
2250		
2251		if ((Registers[REGISTER_A] & 0x80) == 0x80) {
2252			Flags = Flags | FLAG_C;
2253		}
2254		else {
2255			Flags = Flags & (0xFF - FLAG_C);
2256		}
2257		Registers[REGISTER_A] = (Registers[REGISTER_A] <<1) & 0xFE;
2258
2259		if ((saved_flags & FLAG_C) == FLAG_C) {
2260			Registers[REGISTER_A] = Registers[REGISTER_A] | 0x01;
2261		}
2262		set_flag_n((BYTE)Registers[REGISTER_A]);
2263		set_flag_z((BYTE)Registers[REGISTER_A]);
2264		break;
2265
2266	case 0x99: //SALA
2267		saved_flags = Flags;
2268
2269		if ((Registers[REGISTER_A] & 0x80) == 0x80) {
2270			Flags = Flags | FLAG_C;
2271		}
2272		else {
2273			Flags = Flags & (0xFF - FLAG_C);
2274		}
2275		Registers[REGISTER_A] = (Registers[REGISTER_A] << 1) & 0xFE;
2276
2277		set_flag_n((BYTE)Registers[REGISTER_A]);
2278		set_flag_z((BYTE)Registers[REGISTER_A]);
2279		break;
2280	
2281	case 0x9A: //SHRA
2282		if ((Registers[REGISTER_A] & 0x01) == 0x01) {
2283			Flags = Flags | FLAG_C;
2284		}
2285		else {
2286			Flags = Flags & (0xFF - FLAG_C);
2287		}
2288		Registers[REGISTER_A] = (Registers[REGISTER_A] >> 1) & 0x7F;
2289		if ((Flags & FLAG_N) == FLAG_N) 
2290		{
2291			Registers[REGISTER_A] = Registers[REGISTER_A] | 0x80;
2292		}
2293		set_flag_n((BYTE)Registers[REGISTER_A]);
2294		set_flag_z((BYTE)Registers[REGISTER_A]);
2295		break;
2296	case 0x17: //NOP
2297		break;
2298
2299	case 0x18: //WAI
2300		halt = true;
2301		break;
2302	case 0x1C: //ADI Immediate
2303		data = fetch();
2304		temp_word = (WORD)Registers[REGISTER_A] + data;
2305		if ((Flags & FLAG_C) != 0)
2306		{
2307			temp_word++;
2308		}
2309		if (temp_word >= 0x100)
2310		{
2311			Flags = Flags | FLAG_C;
2312		}
2313		else
2314		{
2315			Flags = Flags & (0xFF - FLAG_C);
2316		}
2317		set_flag_n((BYTE)temp_word);
2318		set_flag_z((BYTE)temp_word);
2319		Registers[REGISTER_A] = (BYTE)temp_word;
2320		break;
2321	case 0x1D: //CPI Immediate
2322		
2323		temp_word = (WORD)Registers[REGISTER_A] - fetch();
2324		if (temp_word >= 0x100) {
2325			Flags = Flags | FLAG_C; // Set carry flag
2326		}
2327		else {
2328			Flags = Flags & (0xFF - FLAG_C); // Clear carry flag
2329		}
2330		set_flag_n((BYTE)temp_word);
2331		set_flag_z((BYTE)temp_word);
2332		
2333		break;
2334	case 0x1E: //ANI Immediate
2335		data = fetch();
2336		temp_word = (WORD)Registers[REGISTER_A] & data;
2337		
2338		if (temp_word >= 0x100)
2339		{
2340			Flags = Flags | FLAG_C;
2341		}
2342		else
2343		{
2344			Flags = Flags & (0xFF - FLAG_C);
2345		}
2346		set_flag_n((BYTE)temp_word);
2347		set_flag_z((BYTE)temp_word);
2348		Registers[REGISTER_A] = (BYTE)temp_word;
2349		
2350		break;
2351	case 0x94: //TESTA Register A
2352		set_flag_n(Registers[REGISTER_A]);
2353		set_flag_z(Registers[REGISTER_A]);
2354		break;
2355	case 0x96: //DECA Register A
2356		Registers[REGISTER_A]--;
2357		set_flag_n(Registers[REGISTER_A]);
2358		set_flag_z(Registers[REGISTER_A]);
2359		break;
2360	case 0x57: //RR Absolute
2361		LB = fetch();
2362		HB = fetch();
2363		address += (WORD)((WORD)HB << 8) + LB;
2364		saved_flags = Flags;
2365
2366		if ((Memory[address] & 0x01) == 0x01) {
2367			Flags = Flags | FLAG_C;
2368		}
2369		else {
2370			Flags = Flags & (0xFF - FLAG_C);
2371		}
2372		Memory[address] = (Memory[address] >> 1) & 0x7F;
2373
2374		if ((saved_flags & FLAG_C) == FLAG_C) {
2375			Memory[address] = Memory[address] | 0x80;
2376		}
2377		set_flag_n((BYTE)Memory[address]);
2378		set_flag_z((BYTE)Memory[address]);
2379		break;
2380	case 0x67: //RR Absolute X
2381		address += Index_Registers[REGISTER_X];
2382
2383		LB = fetch();
2384		HB = fetch();
2385		address += (WORD)((WORD)HB << 8) + LB;
2386		saved_flags = Flags;
2387
2388		if ((Memory[address] & 0x01) == 0x01) {
2389			Flags = Flags | FLAG_C;
2390		}
2391		else {
2392			Flags = Flags & (0xFF - FLAG_C);
2393		}
2394		Memory[address] = (Memory[address] >> 1) & 0x7F;
2395
2396		if ((saved_flags & FLAG_C) == FLAG_C) {
2397			Memory[address] = Memory[address] | 0x80;
2398		}
2399		set_flag_n((BYTE)Memory[address]);
2400		set_flag_z((BYTE)Memory[address]);
2401		
2402		break;
2403	case 0x77: //RR Absolute Y
2404		address += Index_Registers[REGISTER_Y];
2405
2406		LB = fetch();
2407		HB = fetch();
2408		address += (WORD)((WORD)HB << 8) + LB;
2409		saved_flags = Flags;
2410
2411		if ((Memory[address] & 0x01) == 0x01) {
2412			Flags = Flags | FLAG_C;
2413		}
2414		else {
2415			Flags = Flags & (0xFF - FLAG_C);
2416		}
2417		Memory[address] = (Memory[address] >> 1) & 0x7F;
2418
2419		if ((saved_flags & FLAG_C) == FLAG_C) {
2420			Memory[address] = Memory[address] | 0x80;
2421		}
2422		set_flag_n((BYTE)Memory[address]);
2423		set_flag_z((BYTE)Memory[address]);
2424		
2425		break;
2426	case 0x87: //RR Absolute X,Y
2427		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2428		LB = fetch();
2429		HB = fetch();
2430		address += (WORD)((WORD)HB << 8) + LB;
2431		saved_flags = Flags;
2432
2433		if ((Memory[address] & 0x01) == 0x01) {
2434			Flags = Flags | FLAG_C;
2435		}
2436		else {
2437			Flags = Flags & (0xFF - FLAG_C);
2438		}
2439		Memory[address] = (Memory[address] >> 1) & 0x7F;
2440
2441		if ((saved_flags & FLAG_C) == FLAG_C) {
2442			Memory[address] = Memory[address] | 0x80;
2443		}
2444		set_flag_n((BYTE)Memory[address]);
2445		set_flag_z((BYTE)Memory[address]);
2446		
2447		break;
2448	case 0x97: //RRA Register A
2449		saved_flags = Flags;
2450
2451		if ((Registers[REGISTER_A] & 0x01) == 0x01) {
2452			Flags = Flags | FLAG_C;
2453		}
2454		else {
2455			Flags = Flags & (0xFF - FLAG_C);
2456		}
2457		Registers[REGISTER_A] = (Registers[REGISTER_A] >> 1) & 0x7F;
2458
2459		if ((saved_flags & FLAG_C) == FLAG_C) {
2460			Registers[REGISTER_A] = Registers[REGISTER_A] | 0x80;
2461		}
2462		set_flag_n((BYTE)Registers[REGISTER_A]);
2463		set_flag_z((BYTE)Registers[REGISTER_A]);
2464		break;
2465	case 0x58: //RCL Absolute
2466		LB = fetch();
2467		HB = fetch();
2468		address += (WORD)((WORD)HB << 8) + LB;
2469		saved_flags = Flags;
2470
2471		if ((Memory[address] & 0x80) == 0x80) {
2472			Flags = Flags | FLAG_C;
2473		}
2474		else {
2475			Flags = Flags & (0xFF - FLAG_C);
2476		}
2477		Memory[address] = (Memory[address] << 1) & 0xFE;
2478
2479		if ((saved_flags & FLAG_C) == FLAG_C) {
2480			Memory[address] = Memory[address] | 0x01;
2481		}
2482		set_flag_n((BYTE)Memory[address]);
2483		set_flag_z((BYTE)Memory[address]);
2484		break;
2485	case 0x68: //RCL Absolute X
2486		address += Index_Registers[REGISTER_X];
2487
2488		LB = fetch();
2489		HB = fetch();
2490		address += (WORD)((WORD)HB << 8) + LB;
2491		saved_flags = Flags;
2492
2493		if ((Memory[address] & 0x80) == 0x80) {
2494			Flags = Flags | FLAG_C;
2495		}
2496		else {
2497			Flags = Flags & (0xFF - FLAG_C);
2498		}
2499		Memory[address] = (Memory[address] << 1) & 0xFE;
2500
2501		if ((saved_flags & FLAG_C) == FLAG_C) {
2502			Memory[address] = Memory[address] | 0x01;
2503		}
2504		set_flag_n((BYTE)Memory[address]);
2505		set_flag_z((BYTE)Memory[address]);
2506		break;
2507	case 0x78: //RCL Absolute Y
2508		address += Index_Registers[REGISTER_Y];
2509
2510		LB = fetch();
2511		HB = fetch();
2512		address += (WORD)((WORD)HB << 8) + LB;
2513		saved_flags = Flags;
2514
2515		if ((Memory[address] & 0x80) == 0x80) {
2516			Flags = Flags | FLAG_C;
2517		}
2518		else {
2519			Flags = Flags & (0xFF - FLAG_C);
2520		}
2521		Memory[address] = (Memory[address] << 1) & 0xFE;
2522
2523		if ((saved_flags & FLAG_C) == FLAG_C) {
2524			Memory[address] = Memory[address] | 0x01;
2525		}
2526		set_flag_n((BYTE)Memory[address]);
2527		set_flag_z((BYTE)Memory[address]);
2528		break;
2529	case 0x88: //RCL Absolute X,Y
2530		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2531
2532		LB = fetch();
2533		HB = fetch();
2534		address += (WORD)((WORD)HB << 8) + LB;
2535		saved_flags = Flags;
2536
2537		if ((Memory[address] & 0x80) == 0x80) {
2538			Flags = Flags | FLAG_C;
2539		}
2540		else {
2541			Flags = Flags & (0xFF - FLAG_C);
2542		}
2543		Memory[address] = (Memory[address] << 1) & 0xFE;
2544
2545		if ((saved_flags & FLAG_C) == FLAG_C) {
2546			Memory[address] = Memory[address] | 0x01;
2547		}
2548		set_flag_n((BYTE)Memory[address]);
2549		set_flag_z((BYTE)Memory[address]);
2550		break;
2551	case 0x5B: //COM Absolute
2552		LB = fetch();
2553		HB = fetch();
2554		address += (WORD)((WORD)HB << 8) + LB;
2555		Memory[address] = Memory[address] ^ 0xFFFF;
2556		
2557		Flags = Flags | FLAG_C;
2558		set_flag_n(Memory[address]);
2559		set_flag_z(Memory[address]);
2560		break;
2561	case 0x6B: //COM Absolute X
2562		address += Index_Registers[REGISTER_X];
2563
2564		LB = fetch();
2565		HB = fetch();
2566		address += (WORD)((WORD)HB << 8) + LB;
2567		Memory[address] = Memory[address] ^ 0xFFFF;
2568
2569		Flags = Flags | FLAG_C;
2570		set_flag_n(Memory[address]);
2571		set_flag_z(Memory[address]);
2572		break;
2573	case 0x7B: //COM Absolute Y
2574		address += Index_Registers[REGISTER_Y];
2575
2576		LB = fetch();
2577		HB = fetch();
2578		address += (WORD)((WORD)HB << 8) + LB;
2579		Memory[address] = Memory[address] ^ 0xFFFF;
2580
2581		Flags = Flags | FLAG_C;
2582		set_flag_n(Memory[address]);
2583		set_flag_z(Memory[address]);
2584		break;
2585	case 0x8B: //COM Absolute X,Y
2586		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2587		LB = fetch();
2588		HB = fetch();
2589		address += (WORD)((WORD)HB << 8) + LB;
2590		Memory[address] = Memory[address] ^ 0xFFFF;
2591
2592		Flags = Flags | FLAG_C;
2593		set_flag_n(Memory[address]);
2594		set_flag_z(Memory[address]);
2595		break;
2596	case 0x9C: //NEGA Register A
2597		Registers[REGISTER_A] = Registers[REGISTER_A] ^ 0xFF;
2598		Registers[REGISTER_A]++;
2599		
2600		
2601		set_flag_n(Registers[REGISTER_A]);
2602		set_flag_z(Registers[REGISTER_A]);
2603
2604		break;
2605	case 0x5D: //RAL Absolute
2606		LB = fetch();
2607		HB = fetch();
2608		address += (WORD)((WORD)HB << 8) + LB;
2609		
2610		saved_flags = Flags;
2611
2612		if ((Memory[address] & 0x80) == 0x80) {
2613			Flags = Flags | FLAG_C;
2614		}
2615		else {
2616			Flags = Flags & (0xFF - FLAG_C);
2617		}
2618		Memory[address] = (Memory[address] << 1) & 0xFE;
2619
2620		if ((Flags & FLAG_C) == FLAG_C) {
2621			Memory[address] = Memory[address] | 0x01;
2622		}
2623		Flags = saved_flags;
2624		set_flag_n((BYTE)Memory[address]);
2625		set_flag_z((BYTE)Memory[address]);
2626		break;
2627	case 0x6D: //RAL Absolute X
2628		address += Index_Registers[REGISTER_X];
2629
2630		LB = fetch();
2631		HB = fetch();
2632		address += (WORD)((WORD)HB << 8) + LB;
2633
2634		saved_flags = Flags;
2635
2636		if ((Memory[address] & 0x80) == 0x80) {
2637			Flags = Flags | FLAG_C;
2638		}
2639		else {
2640			Flags = Flags & (0xFF - FLAG_C);
2641		}
2642		Memory[address] = (Memory[address] << 1) & 0xFE;
2643
2644		if ((Flags & FLAG_C) == FLAG_C) {
2645			Memory[address] = Memory[address] | 0x01;
2646		}
2647		Flags = saved_flags;
2648		set_flag_n((BYTE)Memory[address]);
2649		set_flag_z((BYTE)Memory[address]);
2650		break;
2651	case 0x7D: //RAL Absolute Y
2652		address += Index_Registers[REGISTER_Y];
2653
2654		LB = fetch();
2655		HB = fetch();
2656		address += (WORD)((WORD)HB << 8) + LB;
2657
2658		saved_flags = Flags;
2659
2660		if ((Memory[address] & 0x80) == 0x80) {
2661			Flags = Flags | FLAG_C;
2662		}
2663		else {
2664			Flags = Flags & (0xFF - FLAG_C);
2665		}
2666		Memory[address] = (Memory[address] << 1) & 0xFE;
2667
2668		if ((Flags & FLAG_C) == FLAG_C) {
2669			Memory[address] = Memory[address] | 0x01;
2670		}
2671		Flags = saved_flags;
2672		set_flag_n((BYTE)Memory[address]);
2673		set_flag_z((BYTE)Memory[address]);
2674		break;
2675	case 0x8D: //RAL Absolute X,Y
2676		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2677		LB = fetch();
2678		HB = fetch();
2679		address += (WORD)((WORD)HB << 8) + LB;
2680
2681		saved_flags = Flags;
2682
2683		if ((Memory[address] & 0x80) == 0x80) {
2684			Flags = Flags | FLAG_C;
2685		}
2686		else {
2687			Flags = Flags & (0xFF - FLAG_C);
2688		}
2689		Memory[address] = (Memory[address] << 1) & 0xFE;
2690
2691		if ((Flags & FLAG_C) == FLAG_C) {
2692			Memory[address] = Memory[address] | 0x01;
2693		}
2694		Flags = saved_flags;
2695		set_flag_n((BYTE)Memory[address]);
2696		set_flag_z((BYTE)Memory[address]);
2697		break;
2698	case 0x9D: //RALA Register A
2699		saved_flags = Flags;
2700
2701		if ((Registers[REGISTER_A] & 0x80) == 0x80) {
2702			Flags = Flags | FLAG_C;
2703		}
2704		else {
2705			Flags = Flags & (0xFF - FLAG_C);
2706		}
2707		Registers[REGISTER_A] = (Registers[REGISTER_A] << 1) & 0xFE;
2708
2709		if ((Flags & FLAG_C) == FLAG_C) {
2710			Registers[REGISTER_A] = Registers[REGISTER_A] | 0x01;
2711		}
2712		Flags = saved_flags;
2713		set_flag_n((BYTE)Registers[REGISTER_A]);
2714		set_flag_z((BYTE)Registers[REGISTER_A]);
2715		break;
2716	case 0x5E: //ROR Absolute
2717		LB = fetch();
2718		HB = fetch();
2719		address += (WORD)((WORD)HB << 8) + LB;
2720		saved_flags = Flags;
2721
2722		if ((Memory[address] & 0x01) == 0x01) {
2723			Flags = Flags | FLAG_C;
2724		}
2725		else {
2726			Flags = Flags & (0xFF - FLAG_C);
2727		}
2728		Memory[address] = (Memory[address] >> 1) & 0x7F;
2729
2730		if ((Flags & FLAG_C) == FLAG_C) {
2731			Memory[address] = Memory[address] | 0x80;
2732		}
2733		Flags = saved_flags;
2734		set_flag_n((BYTE)Memory[address]);
2735		set_flag_z((BYTE)Memory[address]);
2736		break;
2737	case 0x6E: //ROR Absolute X
2738		address += Index_Registers[REGISTER_X];
2739
2740		LB = fetch();
2741		HB = fetch();
2742		address += (WORD)((WORD)HB << 8) + LB;
2743		saved_flags = Flags;
2744
2745		if ((Memory[address] & 0x01) == 0x01) {
2746			Flags = Flags | FLAG_C;
2747		}
2748		else {
2749			Flags = Flags & (0xFF - FLAG_C);
2750		}
2751		Memory[address] = (Memory[address] >> 1) & 0x7F;
2752
2753		if ((Flags & FLAG_C) == FLAG_C) {
2754			Memory[address] = Memory[address] | 0x80;
2755		}
2756		Flags = saved_flags;
2757		set_flag_n((BYTE)Memory[address]);
2758		set_flag_z((BYTE)Memory[address]);
2759		break;
2760	case 0x7E: //ROR Absolute Y
2761		address += Index_Registers[REGISTER_Y];
2762
2763		LB = fetch();
2764		HB = fetch();
2765		address += (WORD)((WORD)HB << 8) + LB;
2766		saved_flags = Flags;
2767
2768		if ((Memory[address] & 0x01) == 0x01) {
2769			Flags = Flags | FLAG_C;
2770		}
2771		else {
2772			Flags = Flags & (0xFF - FLAG_C);
2773		}
2774		Memory[address] = (Memory[address] >> 1) & 0x7F;
2775
2776		if ((Flags & FLAG_C) == FLAG_C) {
2777			Memory[address] = Memory[address] | 0x80;
2778		}
2779		Flags = saved_flags;
2780		set_flag_n((BYTE)Memory[address]);
2781		set_flag_z((BYTE)Memory[address]);
2782		break;
2783	case 0x8E: //ROR Absolute X,Y
2784		address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2785		LB = fetch();
2786		HB = fetch();
2787		address += (WORD)((WORD)HB << 8) + LB;
2788		saved_flags = Flags;
2789
2790		if ((Memory[address] & 0x01) == 0x01) {
2791			Flags = Flags | FLAG_C;
2792		}
2793		else {
2794			Flags = Flags & (0xFF - FLAG_C);
2795		}
2796		Memory[address] = (Memory[address] >> 1) & 0x7F;
2797
2798		if ((Flags & FLAG_C) == FLAG_C) {
2799			Memory[address] = Memory[address] | 0x80;
2800		}
2801		Flags = saved_flags;
2802		set_flag_n((BYTE)Memory[address]);
2803		set_flag_z((BYTE)Memory[address]);
2804
2805		break;
2806	case 0x9E: //RORA Register A
2807		saved_flags = Flags;
2808
2809		if ((Registers[REGISTER_A] & 0x01) == 0x01) {
2810			Flags = Flags | FLAG_C;
2811		}
2812		else {
2813			Flags = Flags & (0xFF - FLAG_C);
2814		}
2815		Registers[REGISTER_A] = (Registers[REGISTER_A] >> 1) & 0x7F;
2816
2817		if ((Flags & FLAG_C) == FLAG_C) {
2818			Registers[REGISTER_A] = Registers[REGISTER_A] | 0x80;
2819		}
2820		Flags = saved_flags;
2821		set_flag_n((BYTE)Registers[REGISTER_A]);
2822		set_flag_z((BYTE)Registers[REGISTER_A]);
2823		break;
2824	}
2825}
2826
2827void Group_2_Move(BYTE opcode) {
2828
2829	BYTE source = opcode >> 4;
2830	BYTE destination = opcode & 0x0F;
2831	WORD address = 0;
2832
2833	int destReg = 0;
2834	int sourceReg = 0;
2835
2836	switch (destination)
2837	{
2838	case 0x00:
2839		destReg = REGISTER_A;
2840		break;
2841
2842	case 0x01:
2843		destReg = REGISTER_B;
2844		break;
2845
2846	case 0x02:
2847		destReg = REGISTER_C;
2848		break;
2849
2850	case 0x03:
2851		destReg = REGISTER_L;
2852		break;
2853
2854	case 0x04:
2855		destReg = REGISTER_H;
2856		break;
2857
2858	case 0x05:
2859		destReg = REGISTER_M;
2860		break;
2861
2862	case 0xA0:
2863		destReg = REGISTER_A;
2864		break;
2865
2866	case 0xB0:
2867		destReg = REGISTER_A;
2868		break;
2869
2870	case 0xC0:
2871		destReg = REGISTER_A;
2872		break;
2873
2874	case 0xD0:
2875		destReg = REGISTER_A;
2876		break;
2877
2878	case 0xE0:
2879		destReg = REGISTER_A;
2880		break;
2881
2882	case 0xF0:
2883		destReg = REGISTER_A;
2884		break;
2885
2886	case 0xA1:
2887		destReg = REGISTER_B;
2888		break;
2889
2890	case 0xB1:
2891		destReg = REGISTER_B;
2892		break;
2893
2894	case 0xC1:
2895		destReg = REGISTER_B;
2896		break;
2897
2898	case 0xD1:
2899		destReg = REGISTER_B;
2900		break;
2901
2902	case 0xE1:
2903		destReg = REGISTER_B;
2904		break;
2905
2906	case 0xF1:
2907		destReg = REGISTER_B;
2908		break;
2909
2910	case 0xA2:
2911		destReg = REGISTER_C;
2912		break;
2913
2914	case 0xB2:
2915		destReg = REGISTER_C;
2916		break;
2917
2918	case 0xC2:
2919		destReg = REGISTER_C;
2920		break;
2921
2922	case 0xD2:
2923		destReg = REGISTER_C;
2924		break;
2925
2926	case 0xE2:
2927		destReg = REGISTER_C;
2928		break;
2929
2930	case 0xF2:
2931		destReg = REGISTER_C;
2932		break;
2933
2934	case 0xA3:
2935		destReg = REGISTER_L;
2936		break;
2937
2938	case 0xB3:
2939		destReg = REGISTER_L;
2940		break;
2941
2942	case 0xC3:
2943		destReg = REGISTER_L;
2944		break;
2945
2946	case 0xD3:
2947		destReg = REGISTER_L;
2948		break;
2949
2950	case 0xE3:
2951		destReg = REGISTER_L;
2952		break;
2953
2954	case 0xF3:
2955		destReg = REGISTER_L;
2956		break;
2957
2958	case 0xA4:
2959		destReg = REGISTER_H;
2960		break;
2961
2962	case 0xB4:
2963		destReg = REGISTER_H;
2964		break;
2965
2966	case 0xC4:
2967		destReg = REGISTER_H;
2968		break;
2969
2970	case 0xD4:
2971		destReg = REGISTER_H;
2972		break;
2973
2974	case 0xE4:
2975		destReg = REGISTER_H;
2976		break;
2977
2978	case 0xF4:
2979		destReg = REGISTER_H;
2980		break;
2981
2982	case 0xA5:
2983		destReg = REGISTER_M;
2984		break;
2985
2986	case 0xB5:
2987		destReg = REGISTER_M;
2988		break;
2989
2990	case 0xC5:
2991		destReg = REGISTER_M;
2992		break;
2993
2994	case 0xD5:
2995		destReg = REGISTER_M;
2996		break;
2997
2998	case 0xE5:
2999		destReg = REGISTER_M;
3000		break;
3001	}
3002
3003	switch (source)
3004	{
3005	case 0xA0:
3006		sourceReg = REGISTER_A;
3007		break;
3008
3009	case 0xA1:
3010		sourceReg = REGISTER_A;
3011		break;
3012
3013	case 0xA2:
3014		sourceReg = REGISTER_A;
3015		break;
3016
3017	case 0xA3:
3018		sourceReg = REGISTER_A;
3019		break;
3020
3021	case 0xA4:
3022		sourceReg = REGISTER_A;
3023		break;
3024
3025	case 0xA5:
3026		sourceReg = REGISTER_A;
3027		break;
3028
3029	case 0xB0:
3030		sourceReg = REGISTER_B;
3031		break;
3032
3033	case 0xB1:
3034		sourceReg = REGISTER_B;
3035		break;
3036
3037	case 0xB2:
3038		sourceReg = REGISTER_B;
3039		break;
3040
3041	case 0xB3:
3042		sourceReg = REGISTER_B;
3043		break;
3044
3045	case 0xB4:
3046		sourceReg = REGISTER_B;
3047		break;
3048
3049	case 0xB5:
3050		sourceReg = REGISTER_B;
3051		break;
3052
3053	case 0xC0:
3054		sourceReg = REGISTER_C;
3055		break;
3056
3057	case 0xC1:
3058		sourceReg = REGISTER_C;
3059		break;
3060
3061	case 0xC2:
3062		sourceReg = REGISTER_C;
3063		break;
3064
3065	case 0xC3:
3066		sourceReg = REGISTER_C;
3067		break;
3068
3069	case 0xC4:
3070		sourceReg = REGISTER_C;
3071		break;
3072
3073	case 0xC5:
3074		sourceReg = REGISTER_C;
3075		break;
3076
3077	case 0xD0:
3078		sourceReg = REGISTER_L;
3079		break;
3080
3081	case 0xD1:
3082		sourceReg = REGISTER_L;
3083		break;
3084
3085	case 0xD2:
3086		sourceReg = REGISTER_L;
3087		break;
3088
3089	case 0xD3:
3090		sourceReg = REGISTER_L;
3091		break;
3092
3093	case 0xD4:
3094		sourceReg = REGISTER_L;
3095		break;
3096
3097	case 0xD5:
3098		sourceReg = REGISTER_L;
3099		break;
3100
3101	case 0xE0:
3102		sourceReg = REGISTER_H;
3103		break;
3104
3105	case 0xE1:
3106		sourceReg = REGISTER_H;
3107		break;
3108
3109	case 0xE2:
3110		sourceReg = REGISTER_H;
3111		break;
3112
3113	case 0xE3:
3114		sourceReg = REGISTER_H;
3115		break;
3116
3117	case 0xE4:
3118		sourceReg = REGISTER_H;
3119		break;
3120
3121	case 0xE5:
3122		sourceReg = REGISTER_H;
3123		break;
3124
3125	case 0xF0:
3126		sourceReg = REGISTER_M;
3127		break;
3128
3129	case 0xF1:
3130		sourceReg = REGISTER_M;
3131		break;
3132
3133	case 0xF2:
3134		sourceReg = REGISTER_M;
3135		break;
3136
3137	case 0xF3:
3138		sourceReg = REGISTER_M;
3139		break;
3140
3141	case 0xF4:
3142		sourceReg = REGISTER_M;
3143		break;
3144
3145	case 0x0A:
3146		sourceReg = REGISTER_A;
3147		break;
3148
3149	case 0x0B:
3150		sourceReg = REGISTER_B;
3151		break;
3152
3153	case 0x0C:
3154		sourceReg = REGISTER_C;
3155		break;
3156
3157	case 0x0D:
3158		sourceReg = REGISTER_L;
3159		break;
3160
3161	case 0x0E:
3162		sourceReg = REGISTER_H;
3163		break;
3164
3165	case 0x0F:
3166		sourceReg = REGISTER_M;
3167		break;
3168	}
3169
3170	if (sourceReg == REGISTER_M) {
3171
3172		address = Registers[REGISTER_L];
3173		address += (WORD)Registers[REGISTER_H] << 8;
3174
3175		if (address >= 0 && address <= MEMORY_SIZE) {
3176
3177			Registers[REGISTER_M] = Memory[address];
3178
3179		}
3180	}
3181
3182	if (destReg == REGISTER_M) {
3183
3184		address = Registers[REGISTER_L];
3185		address += (WORD)Registers[REGISTER_H] << 8;
3186
3187		if (address >= 0 && address <= MEMORY_SIZE) {
3188
3189			Memory[address] = Registers[sourceReg];
3190
3191		}
3192	}
3193	else {
3194		Registers[destReg] = Registers[sourceReg];
3195	}
3196}
3197
3198void execute(BYTE opcode)
3199{
3200
3201	BYTE source = opcode >> 4;
3202	BYTE destination = opcode & 0x0F;
3203
3204	if (((source >= 0x0A) && (source <= 0xF5)) && ((destination >= 0x00) && (destination <= 0x05))) {
3205		Group_2_Move(opcode);
3206	}
3207	else
3208	{
3209		Group_1(opcode);
3210	}
3211}
3212
3213void emulate()
3214{
3215	BYTE opcode;
3216	int sanity;
3217
3218	ProgramCounter = 0;
3219	halt = false;
3220	memory_in_range = true;
3221	sanity = 0;
3222
3223	printf("                    A  B  C  L  H  X  Y  SP\n");
3224
3225	while ((!halt) && (memory_in_range)) {
3226		printf("%04X ", ProgramCounter);           // Print current address
3227		opcode = fetch();
3228		execute(opcode);
3229
3230		printf("%s  ", opcode_mneumonics[opcode]);  // Print current opcode
3231
3232		printf("%02X ", Registers[REGISTER_A]);
3233		printf("%02X ", Registers[REGISTER_B]);
3234		printf("%02X ", Registers[REGISTER_C]);
3235		printf("%02X ", Registers[REGISTER_L]);
3236		printf("%02X ", Registers[REGISTER_H]);
3237		printf("%02X ", Index_Registers[REGISTER_X]);
3238		printf("%02X ", Index_Registers[REGISTER_Y]);
3239		printf("%04X ", StackPointer);              // Print Stack Pointer
3240
3241		if ((Flags & FLAG_Z) == FLAG_Z)
3242		{
3243			printf("Z=1 ");
3244		}
3245		else
3246		{
3247			printf("Z=0 ");
3248		}
3249		if ((Flags & FLAG_I) == FLAG_I)
3250		{
3251			printf("I=1 ");
3252		}
3253		else
3254		{
3255			printf("I=0 ");
3256		}
3257		if ((Flags & FLAG_N) == FLAG_N)
3258		{
3259			printf("N=1 ");
3260		}
3261		else
3262		{
3263			printf("N=0 ");
3264		}
3265		if ((Flags & FLAG_C) == FLAG_C)
3266		{
3267			printf("C=1 ");
3268		}
3269		else
3270		{
3271			printf("C=0 ");
3272		}
3273
3274		printf("\n");  // New line
3275		sanity++;
3276		if (sanity > 200) halt = true;
3277
3278	}
3279
3280	printf("\n");  // New line
3281}
3282
3283
3284////////////////////////////////////////////////////////////////////////////////
3285//                            Simulator/Emulator (End)                        //
3286////////////////////////////////////////////////////////////////////////////////
3287
3288
3289void initialise_filenames() {
3290	int i;
3291
3292	for (i = 0; i < MAX_FILENAME_SIZE; i++) {
3293		hex_file[i] = '\0';
3294		trc_file[i] = '\0';
3295	}
3296}
3297
3298
3299
3300
3301int find_dot_position(char *filename) {
3302	int  dot_position;
3303	int  i;
3304	char chr;
3305
3306	dot_position = 0;
3307	i = 0;
3308	chr = filename[i];
3309
3310	while (chr != '\0') {
3311		if (chr == '.') {
3312			dot_position = i;
3313		}
3314		i++;
3315		chr = filename[i];
3316	}
3317
3318	return (dot_position);
3319}
3320
3321
3322int find_end_position(char *filename) {
3323	int  end_position;
3324	int  i;
3325	char chr;
3326
3327	end_position = 0;
3328	i = 0;
3329	chr = filename[i];
3330
3331	while (chr != '\0') {
3332		end_position = i;
3333		i++;
3334		chr = filename[i];
3335	}
3336
3337	return (end_position);
3338}
3339
3340
3341bool file_exists(char *filename) {
3342	bool exists;
3343	FILE *ifp;
3344
3345	exists = false;
3346
3347	if ((ifp = fopen(filename, "r")) != NULL) {
3348		exists = true;
3349
3350		fclose(ifp);
3351	}
3352
3353	return (exists);
3354}
3355
3356
3357
3358void create_file(char *filename) {
3359	FILE *ofp;
3360
3361	if ((ofp = fopen(filename, "w")) != NULL) {
3362		fclose(ofp);
3363	}
3364}
3365
3366
3367
3368bool getline(FILE *fp, char *buffer) {
3369	bool rc;
3370	bool collect;
3371	char c;
3372	int  i;
3373
3374	rc = false;
3375	collect = true;
3376
3377	i = 0;
3378	while (collect) {
3379		c = getc(fp);
3380
3381		switch (c) {
3382		case EOF:
3383			if (i > 0) {
3384				rc = true;
3385			}
3386			collect = false;
3387			break;
3388
3389		case '\n':
3390			if (i > 0) {
3391				rc = true;
3392				collect = false;
3393				buffer[i] = '\0';
3394			}
3395			break;
3396
3397		default:
3398			buffer[i] = c;
3399			i++;
3400			break;
3401		}
3402	}
3403
3404	return (rc);
3405}
3406
3407
3408
3409
3410
3411
3412void load_and_run(int args, _TCHAR** argv) {
3413	char chr;
3414	int  ln;
3415	int  dot_position;
3416	int  end_position;
3417	long i;
3418	FILE *ifp;
3419	long address;
3420	long load_at;
3421	int  code;
3422
3423	// Prompt for the .hex file
3424
3425	printf("\n");
3426	printf("Enter the hex filename (.hex): ");
3427
3428	if (args == 2) {
3429		ln = 0;
3430		chr = argv[1][ln];
3431		while (chr != '\0')
3432		{
3433			if (ln < MAX_FILENAME_SIZE)
3434			{
3435				hex_file[ln] = chr;
3436				trc_file[ln] = chr;
3437				ln++;
3438			}
3439			chr = argv[1][ln];
3440		}
3441	}
3442	else {
3443		ln = 0;
3444		chr = '\0';
3445		while (chr != '\n') {
3446			chr = getchar();
3447
3448			switch (chr) {
3449			case '\n':
3450				break;
3451			default:
3452				if (ln < MAX_FILENAME_SIZE) {
3453					hex_file[ln] = chr;
3454					trc_file[ln] = chr;
3455					ln++;
3456				}
3457				break;
3458			}
3459		}
3460
3461	}
3462	// Tidy up the file names
3463
3464	dot_position = find_dot_position(hex_file);
3465	if (dot_position == 0) {
3466		end_position = find_end_position(hex_file);
3467
3468		hex_file[end_position + 1] = '.';
3469		hex_file[end_position + 2] = 'h';
3470		hex_file[end_position + 3] = 'e';
3471		hex_file[end_position + 4] = 'x';
3472		hex_file[end_position + 5] = '\0';
3473	}
3474	else {
3475		hex_file[dot_position + 0] = '.';
3476		hex_file[dot_position + 1] = 'h';
3477		hex_file[dot_position + 2] = 'e';
3478		hex_file[dot_position + 3] = 'x';
3479		hex_file[dot_position + 4] = '\0';
3480	}
3481
3482	dot_position = find_dot_position(trc_file);
3483	if (dot_position == 0) {
3484		end_position = find_end_position(trc_file);
3485
3486		trc_file[end_position + 1] = '.';
3487		trc_file[end_position + 2] = 't';
3488		trc_file[end_position + 3] = 'r';
3489		trc_file[end_position + 4] = 'c';
3490		trc_file[end_position + 5] = '\0';
3491	}
3492	else {
3493		trc_file[dot_position + 0] = '.';
3494		trc_file[dot_position + 1] = 't';
3495		trc_file[dot_position + 2] = 'r';
3496		trc_file[dot_position + 3] = 'c';
3497		trc_file[dot_position + 4] = '\0';
3498	}
3499
3500	if (file_exists(hex_file)) {
3501		// Clear Registers and Memory
3502
3503		Registers[REGISTER_A] = 0;
3504		Registers[REGISTER_B] = 0;
3505		Registers[REGISTER_C] = 0;
3506		Registers[REGISTER_L] = 0;
3507		Registers[REGISTER_H] = 0;
3508		Index_Registers[REGISTER_X] = 0;
3509		Index_Registers[REGISTER_Y] = 0;
3510		Flags = 0;
3511		ProgramCounter = 0;
3512		StackPointer = 0;
3513
3514		for (i = 0; i < MEMORY_SIZE; i++) {
3515			Memory[i] = 0x00;
3516		}
3517
3518		// Load hex file
3519
3520		if ((ifp = fopen(hex_file, "r")) != NULL) {
3521			printf("Loading file...\n\n");
3522
3523			load_at = 0;
3524
3525			while (getline(ifp, InputBuffer)) {
3526				if (sscanf(InputBuffer, "L=%x", &address) == 1) {
3527					load_at = address;
3528				}
3529				else if (sscanf(InputBuffer, "%x", &code) == 1) {
3530					if ((load_at >= 0) && (load_at <= MEMORY_SIZE)) {
3531						Memory[load_at] = (BYTE)code;
3532					}
3533					load_at++;
3534				}
3535				else {
3536					printf("ERROR> Failed to load instruction: %s \n", InputBuffer);
3537				}
3538			}
3539
3540			fclose(ifp);
3541		}
3542
3543		// Emulate
3544
3545		emulate();
3546	}
3547	else {
3548		printf("\n");
3549		printf("ERROR> Input file %s does not exist!\n", hex_file);
3550		printf("\n");
3551	}
3552}
3553
3554void building(int args, _TCHAR** argv) {
3555	char buffer[1024];
3556	load_and_run(args, argv);
3557	sprintf(buffer, "0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X",
3558		Memory[TEST_ADDRESS_1],
3559		Memory[TEST_ADDRESS_2],
3560		Memory[TEST_ADDRESS_3],
3561		Memory[TEST_ADDRESS_4],
3562		Memory[TEST_ADDRESS_5],
3563		Memory[TEST_ADDRESS_6],
3564		Memory[TEST_ADDRESS_7],
3565		Memory[TEST_ADDRESS_8],
3566		Memory[TEST_ADDRESS_9],
3567		Memory[TEST_ADDRESS_10],
3568		Memory[TEST_ADDRESS_11],
3569		Memory[TEST_ADDRESS_12]
3570	);
3571	sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
3572}
3573
3574
3575
3576void test_and_mark() {
3577	char buffer[1024];
3578	bool testing_complete;
3579	int  len = sizeof(SOCKADDR);
3580	char chr;
3581	int  i;
3582	int  j;
3583	bool end_of_program;
3584	long address;
3585	long load_at;
3586	int  code;
3587	int  mark;
3588	int  passed;
3589
3590	printf("\n");
3591	printf("Automatic Testing and Marking\n");
3592	printf("\n");
3593
3594	testing_complete = false;
3595
3596	sprintf(buffer, "Test Student %s", STUDENT_NUMBER);
3597	sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
3598
3599	while (!testing_complete) {
3600		memset(buffer, '\0', sizeof(buffer));
3601
3602		if (recvfrom(sock, buffer, sizeof(buffer) - 1, 0, (SOCKADDR *)&client_addr, &len) != SOCKET_ERROR) {
3603			printf("Incoming Data: %s \n", buffer);
3604
3605			//if (strcmp(buffer, "Testing complete") == 1)
3606			if (sscanf(buffer, "Testing complete %d", &mark) == 1) {
3607				testing_complete = true;
3608				printf("Current mark = %d\n", mark);
3609
3610			}
3611			else if (sscanf(buffer, "Tests passed %d", &passed) == 1) {
3612				//testing_complete = true;
3613				printf("Passed = %d\n", passed);
3614
3615			}
3616			else if (strcmp(buffer, "Error") == 0) {
3617				printf("ERROR> Testing abnormally terminated\n");
3618				testing_complete = true;
3619			}
3620			else {
3621				// Clear Registers and Memory
3622
3623				Registers[REGISTER_A] = 0;
3624				Registers[REGISTER_B] = 0;
3625				Registers[REGISTER_C] = 0;
3626				Registers[REGISTER_L] = 0;
3627				Registers[REGISTER_H] = 0;
3628				Index_Registers[REGISTER_X] = 0;
3629				Index_Registers[REGISTER_Y] = 0;
3630				Flags = 0;
3631				ProgramCounter = 0;
3632				StackPointer = 0;
3633				for (i = 0; i < MEMORY_SIZE; i++) {
3634					Memory[i] = 0;
3635				}
3636
3637				// Load hex file
3638
3639				i = 0;
3640				j = 0;
3641				load_at = 0;
3642				end_of_program = false;
3643				FILE *ofp;
3644				fopen_s(&ofp, "branch.txt", "a");
3645
3646				while (!end_of_program) {
3647					chr = buffer[i];
3648					switch (chr) {
3649					case '\0':
3650						end_of_program = true;
3651
3652					case ',':
3653						if (sscanf(InputBuffer, "L=%x", &address) == 1) {
3654							load_at = address;
3655						}
3656						else if (sscanf(InputBuffer, "%x", &code) == 1) {
3657							if ((load_at >= 0) && (load_at <= MEMORY_SIZE)) {
3658								Memory[load_at] = (BYTE)code;
3659								fprintf(ofp, "%02X\n", (BYTE)code);
3660							}
3661							load_at++;
3662						}
3663						else {
3664							printf("ERROR> Failed to load instruction: %s \n", InputBuffer);
3665						}
3666						j = 0;
3667						break;
3668
3669					default:
3670						InputBuffer[j] = chr;
3671						j++;
3672						break;
3673					}
3674					i++;
3675				}
3676				fclose(ofp);
3677				// Emulate
3678
3679				if (load_at > 1) {
3680					emulate();
3681					// Send and store results
3682					sprintf(buffer, "%02X%02X %02X%02X %02X%02X %02X%02X %02X%02X %02X%02X",
3683						Memory[TEST_ADDRESS_1],
3684						Memory[TEST_ADDRESS_2],
3685						Memory[TEST_ADDRESS_3],
3686						Memory[TEST_ADDRESS_4],
3687						Memory[TEST_ADDRESS_5],
3688						Memory[TEST_ADDRESS_6],
3689						Memory[TEST_ADDRESS_7],
3690						Memory[TEST_ADDRESS_8],
3691						Memory[TEST_ADDRESS_9],
3692						Memory[TEST_ADDRESS_10],
3693						Memory[TEST_ADDRESS_11],
3694						Memory[TEST_ADDRESS_12]
3695					);
3696					sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
3697				}
3698			}
3699		}
3700	}
3701}
3702
3703
3704
3705int _tmain(int argc, _TCHAR* argv[])
3706{
3707	char chr;
3708	char dummy;
3709
3710	printf("\n");
3711	printf("Microprocessor Emulator\n");
3712	printf("UWE Computer and Network Systems Assignment 1\n");
3713	printf("\n");
3714
3715	initialise_filenames();
3716
3717	if (WSAStartup(MAKEWORD(2, 2), &data) != 0) return(0);
3718
3719	sock = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP);  // Here we create our socket, which will be a UDP socket (SOCK_DGRAM).
3720	if (!sock) {
3721		// Creation failed! 
3722	}
3723
3724	memset(&server_addr, 0, sizeof(SOCKADDR_IN));
3725	server_addr.sin_family = AF_INET;
3726	server_addr.sin_addr.s_addr = inet_addr(IP_ADDRESS_SERVER);
3727	server_addr.sin_port = htons(PORT_SERVER);
3728
3729	memset(&client_addr, 0, sizeof(SOCKADDR_IN));
3730	client_addr.sin_family = AF_INET;
3731	client_addr.sin_addr.s_addr = inet_addr("127.0.0.1");
3732	client_addr.sin_port = htons(PORT_CLIENT);
3733
3734	chr = '\0';
3735	while ((chr != 'e') && (chr != 'E'))
3736	{
3737		printf("\n");
3738		printf("Please select option\n");
3739		printf("L - Load and run a hex file\n");
3740		printf("T - Have the server test and mark your emulator\n");
3741		printf("E - Exit\n");
3742		if (argc == 2) { building(argc, argv); exit(0); }
3743		printf("Enter option: ");
3744		chr = getchar();
3745		if (chr != 0x0A)
3746		{
3747			dummy = getchar();  // read in the <CR>
3748		}
3749		printf("\n");
3750
3751		switch (chr)
3752		{
3753		case 'L':
3754		case 'l':
3755			load_and_run(argc, argv);
3756			break;
3757
3758		case 'T':
3759		case 't':
3760			test_and_mark();
3761			break;
3762
3763		default:
3764			break;
3765		}
3766	}
3767
3768	closesocket(sock);
3769	WSACleanup();
3770
3771
3772	return 0;
3773}