· 8 years ago · Feb 21, 2018, 07:30 PM
1
2#include "stdafx.h"
3#include <winsock2.h>
4
5#pragma comment(lib, "wsock32.lib")
6
7
8#define STUDENT_NUMBER "17028593"
9
10#define IP_ADDRESS_SERVER "127.0.0.1"
11
12#define PORT_SERVER 0x1984 // We define a port that we are going to use.
13#define PORT_CLIENT 0x1985 // We define a port that we are going to use.
14
15#define WORD unsigned short
16#define DWORD unsigned long
17#define BYTE unsigned char
18
19#define MAX_FILENAME_SIZE 500
20#define MAX_BUFFER_SIZE 500
21
22SOCKADDR_IN server_addr;
23SOCKADDR_IN client_addr;
24
25SOCKET sock; // This is our socket, it is the handle to the IO address to read/write packets
26
27WSADATA data;
28
29char InputBuffer[MAX_BUFFER_SIZE];
30
31char hex_file[MAX_BUFFER_SIZE];
32char trc_file[MAX_BUFFER_SIZE];
33
34//////////////////////////
35// Registers //
36//////////////////////////
37
38#define FLAG_I 0x10
39#define FLAG_V 0x08
40#define FLAG_N 0x04
41#define FLAG_Z 0x02
42#define FLAG_C 0x01
43#define REGISTER_A 5
44#define REGISTER_F 4
45#define REGISTER_E 3
46#define REGISTER_D 2
47#define REGISTER_C 1
48#define REGISTER_B 0
49#define REGISTER_X 0
50#define REGISTER_Y 1
51BYTE Index_Registers[2];
52
53BYTE Registers[6];
54BYTE Flags;
55WORD ProgramCounter;
56WORD StackPointer;
57
58
59////////////
60// Memory //
61////////////
62
63#define MEMORY_SIZE 65536
64
65BYTE Memory[MEMORY_SIZE];
66
67#define TEST_ADDRESS_1 0x01FA
68#define TEST_ADDRESS_2 0x01FB
69#define TEST_ADDRESS_3 0x01FC
70#define TEST_ADDRESS_4 0x01FD
71#define TEST_ADDRESS_5 0x01FE
72#define TEST_ADDRESS_6 0x01FF
73#define TEST_ADDRESS_7 0x0200
74#define TEST_ADDRESS_8 0x0201
75#define TEST_ADDRESS_9 0x0202
76#define TEST_ADDRESS_10 0x0203
77#define TEST_ADDRESS_11 0x0204
78#define TEST_ADDRESS_12 0x0205
79
80
81///////////////////////
82// Control variables //
83///////////////////////
84
85bool memory_in_range = true;
86bool halt = false;
87
88
89///////////////////////
90// Disassembly table //
91///////////////////////
92
93char opcode_mneumonics[][14] =
94{
95 "ILLEGAL ",
96 "ILLEGAL ",
97 "STX abs ",
98 "ILLEGAL ",
99 "ILLEGAL ",
100 "ILLEGAL ",
101 "ILLEGAL ",
102 "MV #,B ",
103 "MV #,C ",
104 "MV #,D ",
105 "MV #,E ",
106 "MV #,F ",
107 "MAY impl ",
108 "MYA impl ",
109 "MAS impl ",
110 "CSA impl ",
111
112 "ILLEGAL ",
113 "ILLEGAL ",
114 "STX abs,X ",
115 "ILLEGAL ",
116 "ILLEGAL ",
117 "ILLEGAL ",
118 "SWI impl ",
119 "RTI impl ",
120 "CLC impl ",
121 "SEC impl ",
122 "CLI impl ",
123 "STI impl ",
124 "STV impl ",
125 "CLV impl ",
126 "ILLEGAL ",
127 "ILLEGAL ",
128
129 "ILLEGAL ",
130 "ILLEGAL ",
131 "STX abs,Y ",
132 "ADD A,B ",
133 "SUB A,B ",
134 "CMP A,B ",
135 "OR A,B ",
136 "AND A,B ",
137 "EOR A,B ",
138 "BT A,B ",
139 "LD A,A ",
140 "LD B,A ",
141 "LD C,A ",
142 "LD D,A ",
143 "LD E,A ",
144 "LD F,A ",
145
146 "ILLEGAL ",
147 "LDX # ",
148 "STX abs,XY ",
149 "ADD A,C ",
150 "SUB A,C ",
151 "CMP A,C ",
152 "OR A,C ",
153 "AND A,C ",
154 "EOR A,C ",
155 "BT A,C ",
156 "LD A,B ",
157 "LD B,B ",
158 "LD C,B ",
159 "LD D,B ",
160 "LD E,B ",
161 "LD F,B ",
162
163 "ILLEGAL ",
164 "LDX abs ",
165 "STX (ind),XY ",
166 "ADD A,D ",
167 "SUB A,D ",
168 "CMP A,D ",
169 "OR A,D ",
170 "AND A,D ",
171 "EOR A,D ",
172 "BT A,D ",
173 "LD A,C ",
174 "LD B,C ",
175 "LD C,C ",
176 "LD D,C ",
177 "LD E,C ",
178 "LD F,C ",
179
180 "ILLEGAL ",
181 "LDX abs,X ",
182 "ILLEGAL ",
183 "ADD A,E ",
184 "SUB A,E ",
185 "CMP A,E ",
186 "OR A,E ",
187 "AND A,E ",
188 "EOR A,E ",
189 "BT A,E ",
190 "LD A,D ",
191 "LD B,D ",
192 "LD C,D ",
193 "LD D,D ",
194 "LD E,D ",
195 "LD F,D ",
196
197 "ILLEGAL ",
198 "LDX abs,Y ",
199 "ILLEGAL ",
200 "ADD A,F ",
201 "SUB A,F ",
202 "CMP A,F ",
203 "OR A,F ",
204 "AND A,F ",
205 "EOR A,F ",
206 "BT A,F ",
207 "LD A,E ",
208 "LD B,E ",
209 "LD C,E ",
210 "LD D,E ",
211 "LD E,E ",
212 "LD F,E ",
213
214 "ILLEGAL ",
215 "LDX abs,XY ",
216 "ILLEGAL ",
217 "NOP impl ",
218 "HLT impl ",
219 "ILLEGAL ",
220 "ILLEGAL ",
221 "ILLEGAL ",
222 "ILLEGAL ",
223 "ILLEGAL ",
224 "LD A,F ",
225 "LD B,F ",
226 "LD C,F ",
227 "LD D,F ",
228 "LD E,F ",
229 "LD F,F ",
230
231 "ILLEGAL ",
232 "LDX (ind),XY ",
233 "ADI # ",
234 "SBI # ",
235 "CPI # ",
236 "ORI # ",
237 "ANI # ",
238 "XRI # ",
239 "ILLEGAL ",
240 "ILLEGAL ",
241 "ILLEGAL ",
242 "ILLEGAL ",
243 "ILLEGAL ",
244 "ILLEGAL ",
245 "ILLEGAL ",
246 "ILLEGAL ",
247
248 "LDA # ",
249 "TST abs ",
250 "INC abs ",
251 "DEC abs ",
252 "RCR abs ",
253 "RLC abs ",
254 "ASL abs ",
255 "SAR abs ",
256 "COM abs ",
257 "RAL abs ",
258 "ROR abs ",
259 "LX #,A ",
260 "ILLEGAL ",
261 "LODS # ",
262 "PUSH ,A ",
263 "POP A, ",
264
265 "LDA abs ",
266 "TST abs,X ",
267 "INC abs,X ",
268 "DEC abs,X ",
269 "RCR abs,X ",
270 "RLC abs,X ",
271 "ASL abs,X ",
272 "SAR abs,X ",
273 "COM abs,X ",
274 "RAL abs,X ",
275 "ROR abs,X ",
276 "ILLEGAL ",
277 "STO abs ",
278 "LODS abs ",
279 "PUSH ,s ",
280 "POP s, ",
281
282 "LDA abs,X ",
283 "TST abs,Y ",
284 "INC abs,Y ",
285 "DEC abs,Y ",
286 "RCR abs,Y ",
287 "RLC abs,Y ",
288 "ASL abs,Y ",
289 "SAR abs,Y ",
290 "COM abs,Y ",
291 "RAL abs,Y ",
292 "ROR abs,Y ",
293 "ILLEGAL ",
294 "STO abs,X ",
295 "LODS abs,X ",
296 "PUSH ,B ",
297 "POP B, ",
298
299 "LDA abs,Y ",
300 "TST abs,XY ",
301 "INC abs,XY ",
302 "DEC abs,XY ",
303 "RCR abs,XY ",
304 "RLC abs,XY ",
305 "ASL abs,XY ",
306 "SAR abs,XY ",
307 "COM abs,XY ",
308 "RAL abs,XY ",
309 "ROR abs,XY ",
310 "ILLEGAL ",
311 "STO abs,Y ",
312 "LODS abs,Y ",
313 "PUSH ,C ",
314 "POP C, ",
315
316 "LDA abs,XY ",
317 "TSTA A,A ",
318 "INCA A,A ",
319 "DECA A,A ",
320 "RCRA A,A ",
321 "RLCA A,A ",
322 "ASLA A,A ",
323 "SARA A,A ",
324 "COMA A,A ",
325 "RALA A,A ",
326 "RORA A,A ",
327 "RTN impl ",
328 "STO abs,XY ",
329 "LODS abs,XY ",
330 "PUSH ,D ",
331 "POP D, ",
332
333 "LDA (ind),XY ",
334 "DEX impl ",
335 "INX impl ",
336 "DEY impl ",
337 "INCY impl ",
338 "ILLEGAL ",
339 "ILLEGAL ",
340 "ILLEGAL ",
341 "ILLEGAL ",
342 "JSR abs ",
343 "JMP abs ",
344 "ILLEGAL ",
345 "STO (ind),XY ",
346 "LODS (ind),XY",
347 "PUSH ,E ",
348 "POP E, ",
349
350 "BRA rel ",
351 "BCC rel ",
352 "BCS rel ",
353 "BNE rel ",
354 "BEQ rel ",
355 "BVC rel ",
356 "BVS rel ",
357 "BMI rel ",
358 "BPL rel ",
359 "BGE rel ",
360 "BLE rel ",
361 "BGT rel ",
362 "BLT rel ",
363 "ILLEGAL ",
364 "PUSH ,F ",
365 "POP F, ",
366
367};
368
369////////////////////////////////////////////////////////////////////////////////
370// Simulator/Emulator (Start) //
371////////////////////////////////////////////////////////////////////////////////
372
373BYTE fetch()
374{
375 BYTE byte = 0;
376
377 if ((ProgramCounter >= 0) && (ProgramCounter <= MEMORY_SIZE))
378 {
379 memory_in_range = true;
380 byte = Memory[ProgramCounter];
381 ProgramCounter++;
382 }
383 else
384 {
385 memory_in_range = false;
386 }
387 return byte;
388}
389
390
391void set_flag_n(BYTE inReg)
392{
393 BYTE reg;
394 reg = inReg;
395
396 if ((reg & 0x80) != 0) // msbit set
397 {
398 Flags = Flags | FLAG_N;
399 }
400 else
401 {
402 Flags = Flags & (0xFF - FLAG_N);
403 }
404}
405
406void set_flag_z(BYTE inReg)
407{
408 BYTE reg;
409 reg = inReg;
410
411 if (reg = 0)
412 {
413 Flags = Flags | FLAG_Z;
414 }
415 else
416 {
417 Flags = Flags & (0xFF - FLAG_Z);
418 }
419}
420
421void set_flag_v(BYTE in1, BYTE in2, BYTE out1) //overflow
422
423{
424
425 BYTE reg1in;
426
427 BYTE reg2in;
428
429 BYTE regOut;
430
431
432
433 reg1in = in1;
434
435 reg2in = in2;
436
437 regOut = out1;
438
439
440
441 if ((((reg1in & 0x80) == 0x80) && ((reg2in & 0x80) == 0x80) && ((regOut & 0x80) != 0x80)) //Overflow
442
443 || (((reg1in & 0x80) != 0x80) && ((reg2in & 0x80) != 0x80) && ((regOut & 0x80) == 0x80))) //Overflow
444
445 {
446
447 Flags = Flags | FLAG_V;
448
449 }
450
451 else
452
453 {
454
455 Flags = Flags & (0xFF - FLAG_V);
456
457 }
458
459}
460
461void Group_1(BYTE opcode)
462{
463 BYTE LB = 0;
464 BYTE HB = 0;
465 WORD saved_flags;
466 WORD address = 0;
467 WORD data = 0;
468 WORD temp_word = 0;
469 WORD offset;
470
471
472 switch (opcode)
473 {
474 case 0x90: //LDA Immed
475 data = fetch();
476 Registers[REGISTER_A] = data;
477 set_flag_n(Registers[REGISTER_A]);
478 set_flag_z(Registers[REGISTER_A]);
479
480 break;
481
482 case 0xA0: //LDA Abs
483 HB = fetch();
484 LB = fetch();
485 address += (WORD)((WORD)HB << 8) + LB;
486 if (address >= 0 && address < MEMORY_SIZE) {
487 Registers[REGISTER_A] = Memory[address];
488 }
489 set_flag_n(Registers[REGISTER_A]);
490 set_flag_z(Registers[REGISTER_A]);
491 break;
492
493 case 0xB0: //LDA Abs Index X
494 address += Index_Registers[REGISTER_X];
495 HB = fetch();
496 LB = fetch();
497 address += (WORD)((WORD)HB << 8) + LB;
498 if (address >= 0 && address < MEMORY_SIZE) {
499 Registers[REGISTER_A] = Memory[address];
500 }
501 set_flag_n(Registers[REGISTER_A]);
502 set_flag_z(Registers[REGISTER_A]);
503 break;
504
505 case 0xC0: //LDA Abs Index Y
506 address += Index_Registers[REGISTER_Y];
507 HB = fetch();
508 LB = fetch();
509 address += (WORD)((WORD)HB << 8) + LB;
510 if (address >= 0 && address < MEMORY_SIZE) {
511 Registers[REGISTER_A] = Memory[address];
512 }
513 set_flag_n(Registers[REGISTER_A]);
514 set_flag_z(Registers[REGISTER_A]);
515 break;
516
517 case 0xD0: //LDA Abs Index XY
518 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
519 HB = fetch();
520 LB = fetch();
521 address += (WORD)((WORD)HB << 8) + LB;
522 if (address >= 0 && address < MEMORY_SIZE) {
523 Registers[REGISTER_A] = Memory[address];
524 }
525 set_flag_n(Registers[REGISTER_A]);
526 set_flag_z(Registers[REGISTER_A]);
527 break;
528
529 case 0xE0: //LDA Ind XY
530 HB = fetch();
531 LB = fetch();
532 address = (WORD)((WORD)HB << 8) + LB;
533 HB = Memory[address];
534 LB = Memory[address + 1];
535 address = (WORD)((WORD)HB << 8) + LB;
536 address += Index_Registers[REGISTER_X];
537 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8);
538 if (address >= 0 && address < MEMORY_SIZE) {
539 Registers[REGISTER_A] = Memory[address];
540 }
541 set_flag_n(Registers[REGISTER_A]);
542 set_flag_z(Registers[REGISTER_A]);
543 break;
544
545
546 ///////////////////////////////////////////
547 // END LDA //
548 //////////////////////////////////////////
549
550 case 0x31: //LDX Immed
551 data = fetch();
552 Memory[address] = Registers[REGISTER_X];
553 set_flag_n(Registers[REGISTER_X]);
554 set_flag_z(Registers[REGISTER_X]);
555 break;
556
557 case 0x41: //LDX Abs
558 HB = fetch();
559 LB = fetch();
560 address += (WORD)((WORD)HB << 8) + LB;
561 if (address >= 0 && address < MEMORY_SIZE) {
562 Memory[address] = Registers[REGISTER_X];
563 }
564 set_flag_n(Registers[REGISTER_X]);
565 set_flag_z(Registers[REGISTER_X]);
566 break;
567
568 case 0x51: //LDX Abs Index X
569 address += Index_Registers[REGISTER_X];
570 HB = fetch();
571 LB = fetch();
572 address += (WORD)((WORD)HB << 8) + LB;
573 if (address >= 0 && address < MEMORY_SIZE) {
574 Memory[address] = Registers[REGISTER_X];
575 }
576 set_flag_n(Registers[REGISTER_X]);
577 set_flag_z(Registers[REGISTER_X]);
578 break;
579
580 case 0x61: //LDX Abs Index Y
581 address += Index_Registers[REGISTER_Y];
582 HB = fetch();
583 LB = fetch();
584 address += (WORD)((WORD)HB << 8) + LB;
585 if (address >= 0 && address < MEMORY_SIZE) {
586 Memory[address] = Registers[REGISTER_X];
587 }
588 set_flag_n(Registers[REGISTER_X]);
589 set_flag_z(Registers[REGISTER_X]);
590 break;
591
592 case 0x71: //LDX Abs Index XY
593 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
594 HB = fetch();
595 LB = fetch();
596 address += (WORD)((WORD)HB << 8) + LB;
597 if (address >= 0 && address < MEMORY_SIZE) {
598 Memory[address] = Registers[REGISTER_X];
599 }
600 set_flag_n(Registers[REGISTER_X]);
601 set_flag_z(Registers[REGISTER_X]);
602 break;
603
604 case 0x81: //LDX Ind XY
605 HB = fetch();
606 LB = fetch();
607 address = (WORD)((WORD)HB << 8) + LB;
608 HB = Memory[address];
609 LB = Memory[address + 1];
610 address = (WORD)((WORD)HB << 8) + LB;
611 address += Index_Registers[REGISTER_X];
612 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8);
613 if (address >= 0 && address < MEMORY_SIZE) {
614 Memory[address] = Registers[REGISTER_X];
615 }
616 set_flag_n(Registers[REGISTER_X]);
617 set_flag_z(Registers[REGISTER_X]);
618 break;
619
620 ///////////////////////////////////////////
621 // END LDX //
622 //////////////////////////////////////////
623
624 case 0x0C: //MAY
625 Index_Registers[REGISTER_Y] = Registers[REGISTER_A];
626 set_flag_n((BYTE)Registers[REGISTER_A]);
627 break;
628
629 ///////////////////////////////////////////
630 // END MAY //
631 //////////////////////////////////////////
632
633 case 0x0D: //MYA
634 Registers[REGISTER_A] = Index_Registers[REGISTER_Y];
635 set_flag_n((BYTE)Registers[REGISTER_A]);
636 set_flag_z((BYTE)Registers[REGISTER_A]);
637
638 ///////////////////////////////////////////
639 // END MYA //
640 //////////////////////////////////////////
641
642 case 0xAC: //STO Abs
643 HB = fetch();
644 LB = fetch();
645 address += (WORD)((WORD)HB << 8) + LB;
646 if (address >= 0 && address < MEMORY_SIZE) {
647 Memory[address] = Registers[REGISTER_A];
648 }
649 set_flag_n((BYTE)Registers[REGISTER_A]);
650 set_flag_z((BYTE)Registers[REGISTER_A]);
651 break;
652
653 case 0xBC: //STO Abs X
654 address += Index_Registers[REGISTER_X];
655 HB = fetch();
656 LB = fetch();
657 address += (WORD)((WORD)HB << 8) + LB;
658 if (address >= 0 && address < MEMORY_SIZE) {
659 Memory[address] = Registers[REGISTER_A];
660 }
661 set_flag_n((BYTE)Registers[REGISTER_A]);
662 set_flag_z((BYTE)Registers[REGISTER_A]);
663 break;
664
665 case 0xCC: //STO Abs Y
666 address += Index_Registers[REGISTER_Y];
667 HB = fetch();
668 LB = fetch();
669 address += (WORD)((WORD)HB << 8) + LB;
670 if (address >= 0 && address < MEMORY_SIZE) {
671 Memory[address] = Registers[REGISTER_A];
672 }
673 set_flag_n((BYTE)Registers[REGISTER_A]);
674 set_flag_z((BYTE)Registers[REGISTER_A]);
675 break;
676
677 case 0xDC: //STO Abs XY
678 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
679 HB = fetch();
680 LB = fetch();
681 address += (WORD)((WORD)HB << 8) + LB;
682 if (address >= 0 && address < MEMORY_SIZE) {
683 Memory[address] = Registers[REGISTER_A];
684 }
685 set_flag_n((BYTE)Registers[REGISTER_A]);
686 set_flag_z((BYTE)Registers[REGISTER_A]);
687 break;
688
689 case 0xEC: //STO Ind XY
690 HB = fetch();
691 LB = fetch();
692 address = (WORD)((WORD)HB << 8) + LB;
693 HB = Memory[address];
694 LB = Memory[address + 1];
695 address = (WORD)((WORD)HB << 8) + LB;
696 address += Index_Registers[REGISTER_X];
697 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8);
698 if (address >= 0 && address < MEMORY_SIZE) {
699 Memory[address] = Registers[REGISTER_A];
700 }
701 set_flag_n((BYTE)Registers[REGISTER_A]);
702 set_flag_z((BYTE)Registers[REGISTER_A]);
703 break;
704
705 ///////////////////////////////////////////
706 // END STO //
707 //////////////////////////////////////////
708
709 case 0x07: //MV Register B
710 data = fetch();
711 Registers[REGISTER_B] = data;
712 set_flag_n(Registers[REGISTER_B]);
713 set_flag_z(Registers[REGISTER_B]);
714 break;
715
716 case 0x08: //MV Register C
717 data = fetch();
718 Registers[REGISTER_C] = data;
719 set_flag_n(Registers[REGISTER_C]);
720 set_flag_z(Registers[REGISTER_C]);
721 break;
722
723 case 0x09: //MV Register D
724 data = fetch();
725 Registers[REGISTER_D] = data;
726 set_flag_n(Registers[REGISTER_D]);
727 set_flag_z(Registers[REGISTER_D]);
728 break;
729
730 case 0x0A: //MV Register E
731 data = fetch();
732 Registers[REGISTER_E] = data;
733 set_flag_n(Registers[REGISTER_E]);
734 set_flag_z(Registers[REGISTER_E]);
735 break;
736
737 case 0x0B: //MV Register F
738 data = fetch();
739 Registers[REGISTER_F] = data;
740 set_flag_n(Registers[REGISTER_F]);
741 set_flag_z(Registers[REGISTER_F]);
742 break;
743
744 ///////////////////////////////////////////
745 // END MV //
746 //////////////////////////////////////////
747
748 case 0x18:
749 Flags = Flags & (0xFF - FLAG_C);
750 break;
751
752 ///////////////////////////////////////////
753 // END CLC //
754 //////////////////////////////////////////
755
756 case 0x19:
757 Flags = Flags | FLAG_C;
758 break;
759
760 ///////////////////////////////////////////
761 // END SEC //
762 //////////////////////////////////////////
763
764 case 0x1A:
765 Flags = Flags & (0xFF - FLAG_I);
766 break;
767
768 ///////////////////////////////////////////
769 // END CLI //
770 //////////////////////////////////////////
771
772 case 0x1B:
773 Flags = Flags | FLAG_I;
774 break;
775
776 ///////////////////////////////////////////
777 // END STI //
778 //////////////////////////////////////////
779
780 case 0x1C:
781 Flags = Flags & (0xFF - FLAG_V);
782
783 ///////////////////////////////////////////
784 // END STV //
785 //////////////////////////////////////////
786
787 case 0x1D:
788 Flags = Flags & (0xFF - FLAG_V); //Implment Overflag here
789 break;
790 ///////////////////////////////////////////
791 // END CLV //
792 //////////////////////////////////////////
793
794 case 0x9D: //LODS Immed
795 data = fetch();
796 StackPointer = data << 8;
797 StackPointer += fetch();
798 break;
799
800 case 0xAD: //LODS Abs
801 HB = fetch();
802 LB = fetch();
803 address = (WORD)((WORD)HB << 8) + LB;
804 if (address >= 0 && address < MEMORY_SIZE - 1) {
805 StackPointer = (WORD)Memory[address] << 8;
806 StackPointer += Memory[address + 1];
807 }
808 break;
809
810 case 0xBD: //LODS Abs Index X
811 address += Index_Registers[REGISTER_X];
812 HB = fetch();
813 LB = fetch();
814 address = (WORD)((WORD)HB << 8) + LB;
815 if (address >= 0 && address < MEMORY_SIZE - 1) {
816 StackPointer = (WORD)Memory[address] << 8;
817 StackPointer += Memory[address + 1];
818 }
819 break;
820
821 case 0xCD: //LODS Abs Index Y
822 address += Index_Registers[REGISTER_Y];
823 HB = fetch();
824 LB = fetch();
825 address = (WORD)((WORD)HB << 8) + LB;
826 if (address >= 0 && address < MEMORY_SIZE - 1) {
827 StackPointer = (WORD)Memory[address] << 8;
828 StackPointer += Memory[address + 1];
829 }
830 break;
831
832 case 0xDD: //LODS Abs Index XY
833 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
834 HB = fetch();
835 LB = fetch();
836 address = (WORD)((WORD)HB << 8) + LB;
837 if (address >= 0 && address < MEMORY_SIZE - 1) {
838 StackPointer = (WORD)Memory[address] << 8;
839 StackPointer += Memory[address + 1];
840 }
841 break;
842
843 case 0xED: //LODS Ind Index XY
844 HB = fetch();
845 LB = fetch();
846 address = (WORD)((WORD)HB << 8) + LB;
847 HB = Memory[address];
848 LB = Memory[address + 1];
849 address = (WORD)((WORD)HB << 8) + LB;
850 address += Index_Registers[REGISTER_X];
851 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8);
852 if (address >= 0 && address < MEMORY_SIZE - 1) {
853 StackPointer = (WORD)Memory[address] << 8;
854 StackPointer += Memory[address + 1];
855 }
856 break;
857
858 ///////////////////////////////////////////
859 // END LODS //
860 //////////////////////////////////////////
861
862 case 0x23: //ADD AB
863 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_B];
864 if ((Flags & FLAG_C) != 0) {
865 temp_word++;
866 }
867
868 if (temp_word >= 0x100) {
869 //Set carry flag
870 Flags = Flags | FLAG_C;
871 }
872 else {
873 //Clear carry flag
874 Flags = Flags & (0xFF - FLAG_C);
875 }
876 set_flag_n((BYTE)temp_word);
877 set_flag_z((BYTE)temp_word);
878 set_flag_v(Registers[REGISTER_A], Registers[REGISTER_B], (BYTE)temp_word);
879 Registers[REGISTER_A] = (BYTE)temp_word;
880 break;
881
882 case 0x33: //ADD AC
883 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_C];
884 if ((Flags & FLAG_C) != 0) {
885 temp_word++;
886 }
887
888 if (temp_word >= 0x100) {
889 //Set carry flag
890 Flags = Flags | FLAG_C;
891 }
892 else {
893 //Clear carry flag
894 Flags = Flags & (0xFF - FLAG_C);
895 }
896 set_flag_n((BYTE)temp_word);
897 set_flag_z((BYTE)temp_word);
898 set_flag_v(Registers[REGISTER_A], Registers[REGISTER_C], (BYTE)temp_word);
899 Registers[REGISTER_A] = (BYTE)temp_word;
900 break;
901
902 case 0x43: //ADD AD
903 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_D];
904 if ((Flags & FLAG_C) != 0) {
905 temp_word++;
906 }
907
908 if (temp_word >= 0x100) {
909 //Set carry flag
910 Flags = Flags | FLAG_C;
911 }
912 else {
913 //Clear carry flag
914 Flags = Flags & (0xFF - FLAG_C);
915 }
916 set_flag_n((BYTE)temp_word);
917 set_flag_z((BYTE)temp_word);
918 set_flag_v(Registers[REGISTER_A], Registers[REGISTER_D], (BYTE)temp_word);
919 Registers[REGISTER_A] = (BYTE)temp_word;
920 break;
921
922 case 0x53: //ADD AE
923 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_E];
924 if ((Flags & FLAG_C) != 0) {
925 temp_word++;
926 }
927
928 if (temp_word >= 0x100) {
929 //Set carry flag
930 Flags = Flags | FLAG_C;
931 }
932 else {
933 //Clear carry flag
934 Flags = Flags & (0xFF - FLAG_C);
935 }
936 set_flag_n((BYTE)temp_word);
937 set_flag_z((BYTE)temp_word);
938 set_flag_v(Registers[REGISTER_A], Registers[REGISTER_E], (BYTE)temp_word);
939 Registers[REGISTER_A] = (BYTE)temp_word;
940 break;
941
942 case 0x63: //ADD AF
943 temp_word = (WORD)Registers[REGISTER_A] + (WORD)Registers[REGISTER_F];
944 if ((Flags & FLAG_C) != 0) {
945 temp_word++;
946 }
947
948 if (temp_word >= 0x100) {
949 //Set carry flag
950 Flags = Flags | FLAG_C;
951 }
952 else {
953 //Clear carry flag
954 Flags = Flags & (0xFF - FLAG_C);
955 }
956 set_flag_n((BYTE)temp_word);
957 set_flag_z((BYTE)temp_word);
958 set_flag_v(Registers[REGISTER_A], Registers[REGISTER_F], (BYTE)temp_word);
959 Registers[REGISTER_A] = (BYTE)temp_word;
960 break;
961
962 ///////////////////////////////////////////
963 // END ADD //
964 //////////////////////////////////////////
965
966 case 0x24: //SUB AB
967 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_B];
968 if ((Flags & FLAG_C) != 0) {
969 temp_word--;
970 }
971
972 if (temp_word >= 0x100) {
973 //Set carry flag
974 Flags = Flags | FLAG_C;
975 }
976 else {
977 //Clear carry flag
978 Flags = Flags & (0xFF - FLAG_C);
979 }
980 set_flag_n((BYTE)temp_word);
981 set_flag_z((BYTE)temp_word);
982 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_B], (BYTE)temp_word);
983 Registers[REGISTER_A] = (BYTE)temp_word;
984 break;
985
986 case 0x34: //SUB AC
987 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_C];
988 if ((Flags & FLAG_C) != 0) {
989 temp_word--;
990 }
991
992 if (temp_word >= 0x100) {
993 //Set carry flag
994 Flags = Flags | FLAG_C;
995 }
996 else {
997 //Clear carry flag
998 Flags = Flags & (0xFF - FLAG_C);
999 }
1000 set_flag_n((BYTE)temp_word);
1001 set_flag_z((BYTE)temp_word);
1002 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_C], (BYTE)temp_word);
1003 Registers[REGISTER_A] = (BYTE)temp_word;
1004 break;
1005
1006 case 0x44: //SUB AD
1007 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_D];
1008 if ((Flags & FLAG_C) != 0) {
1009 temp_word--;
1010 }
1011
1012 if (temp_word >= 0x100) {
1013 //Set carry flag
1014 Flags = Flags | FLAG_C;
1015 }
1016 else {
1017 //Clear carry flag
1018 Flags = Flags & (0xFF - FLAG_C);
1019 }
1020 set_flag_n((BYTE)temp_word);
1021 set_flag_z((BYTE)temp_word);
1022 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_D], (BYTE)temp_word);
1023 Registers[REGISTER_A] = (BYTE)temp_word;
1024 break;
1025
1026 case 0x54: //SUB AE
1027 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_E];
1028 if ((Flags & FLAG_C) != 0) {
1029 temp_word--;
1030 }
1031
1032 if (temp_word >= 0x100) {
1033 //Set carry flag
1034 Flags = Flags | FLAG_C;
1035 }
1036 else {
1037 //Clear carry flag
1038 Flags = Flags & (0xFF - FLAG_C);
1039 }
1040 set_flag_n((BYTE)temp_word);
1041 set_flag_z((BYTE)temp_word);
1042 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_E], (BYTE)temp_word);
1043 Registers[REGISTER_A] = (BYTE)temp_word;
1044 break;
1045
1046 case 0x64: //SUB AF
1047 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_F];
1048 if ((Flags & FLAG_C) != 0) {
1049 temp_word--;
1050 }
1051
1052 if (temp_word >= 0x100) {
1053 //Set carry flag
1054 Flags = Flags | FLAG_C;
1055 }
1056 else {
1057 //Clear carry flag
1058 Flags = Flags & (0xFF - FLAG_C);
1059 }
1060 set_flag_n((BYTE)temp_word);
1061 set_flag_z((BYTE)temp_word);
1062 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_F], (BYTE)temp_word);
1063 Registers[REGISTER_A] = (BYTE)temp_word;
1064 break;
1065
1066 ///////////////////////////////////////////
1067 // END SUB //
1068 //////////////////////////////////////////
1069
1070 case 0x25: //CMP AB
1071 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_B];
1072 if ((Flags & FLAG_C) != 0) {
1073 temp_word++;
1074 }
1075
1076 if (temp_word >= 0x100) {
1077 //Set carry flag
1078 Flags = Flags | FLAG_C;
1079 }
1080 else {
1081 //Clear carry flag
1082 Flags = Flags & (0xFF - FLAG_C);
1083 }
1084 set_flag_n((BYTE)temp_word);
1085 set_flag_z((BYTE)temp_word);
1086 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_B], (BYTE)temp_word);
1087 break;
1088
1089 case 0x35: //CMP AC
1090 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_C];
1091 if ((Flags & FLAG_C) != 0) {
1092 temp_word++;
1093 }
1094
1095 if (temp_word >= 0x100) {
1096 //Set carry flag
1097 Flags = Flags | FLAG_C;
1098 }
1099 else {
1100 //Clear carry flag
1101 Flags = Flags & (0xFF - FLAG_C);
1102 }
1103 set_flag_n((BYTE)temp_word);
1104 set_flag_z((BYTE)temp_word);
1105 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_C], (BYTE)temp_word);
1106 break;
1107
1108 case 0x45: //CMP AD
1109 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_D];
1110 if ((Flags & FLAG_C) != 0) {
1111 temp_word++;
1112 }
1113
1114 if (temp_word >= 0x100) {
1115 //Set carry flag
1116 Flags = Flags | FLAG_C;
1117 }
1118 else {
1119 //Clear carry flag
1120 Flags = Flags & (0xFF - FLAG_C);
1121 }
1122 set_flag_n((BYTE)temp_word);
1123 set_flag_z((BYTE)temp_word);
1124 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_D], (BYTE)temp_word);
1125 break;
1126
1127 case 0x55: //CMP AE
1128 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_E];
1129 if ((Flags & FLAG_C) != 0) {
1130 temp_word++;
1131 }
1132
1133 if (temp_word >= 0x100) {
1134 //Set carry flag
1135 Flags = Flags | FLAG_C;
1136 }
1137 else {
1138 //Clear carry flag
1139 Flags = Flags & (0xFF - FLAG_C);
1140 }
1141 set_flag_n((BYTE)temp_word);
1142 set_flag_z((BYTE)temp_word);
1143 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_E], (BYTE)temp_word);
1144 break;
1145
1146 case 0x65: //CMP AF
1147 temp_word = (WORD)Registers[REGISTER_A] - (WORD)Registers[REGISTER_F];
1148 if ((Flags & FLAG_C) != 0) {
1149 temp_word++;
1150 }
1151
1152 if (temp_word >= 0x100) {
1153 //Set carry flag
1154 Flags = Flags | FLAG_C;
1155 }
1156 else {
1157 //Clear carry flag
1158 Flags = Flags & (0xFF - FLAG_C);
1159 }
1160 set_flag_n((BYTE)temp_word);
1161 set_flag_z((BYTE)temp_word);
1162 set_flag_v(Registers[REGISTER_A], -Registers[REGISTER_F], (BYTE)temp_word);
1163 break;
1164
1165 ///////////////////////////////////////////
1166 // END CMP //
1167 //////////////////////////////////////////
1168
1169 case 0x0F: //CSA
1170 Registers[REGISTER_A] = Flags;
1171 break;
1172
1173 ///////////////////////////////////////////
1174 // END CSA //
1175 //////////////////////////////////////////
1176
1177 case 0x0E:
1178 Flags = Registers[REGISTER_A];
1179 break;
1180
1181 ///////////////////////////////////////////
1182 // END MAS //
1183 //////////////////////////////////////////
1184
1185 case 0x26: //OR AB
1186 temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_B];
1187 set_flag_n((BYTE)temp_word);
1188 set_flag_z((BYTE)temp_word);
1189 Registers[REGISTER_A] = (BYTE)temp_word;
1190 Flags = Flags & (0xFF - FLAG_V);
1191 break;
1192
1193 case 0x36: //OR AC
1194 temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_C];
1195 set_flag_n((BYTE)temp_word);
1196 set_flag_z((BYTE)temp_word);
1197 Registers[REGISTER_A] = (BYTE)temp_word;
1198 Flags = Flags & (0xFF - FLAG_V);
1199 break;
1200
1201 case 0x46: //OR AD
1202 temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_D];
1203 set_flag_n((BYTE)temp_word);
1204 set_flag_z((BYTE)temp_word);
1205 Registers[REGISTER_A] = (BYTE)temp_word;
1206 Flags = Flags & (0xFF - FLAG_V);
1207 break;
1208
1209 case 0x56: //OR AE
1210 temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_E];
1211 set_flag_n((BYTE)temp_word);
1212 set_flag_z((BYTE)temp_word);
1213 Registers[REGISTER_A] = (BYTE)temp_word;
1214 Flags = Flags & (0xFF - FLAG_V);
1215 break;
1216
1217 case 0x66: //OR AF
1218 temp_word = (WORD)Registers[REGISTER_A] | (WORD)Registers[REGISTER_F];
1219 set_flag_n((BYTE)temp_word);
1220 set_flag_z((BYTE)temp_word);
1221 Registers[REGISTER_A] = (BYTE)temp_word;
1222 Flags = Flags & (0xFF - FLAG_V);
1223 break;
1224
1225 ///////////////////////////////////////////
1226 // END OR //
1227 //////////////////////////////////////////
1228
1229 case 0x28: //EOR AB
1230 temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_B];
1231 set_flag_n((BYTE)temp_word);
1232 set_flag_z((BYTE)temp_word);
1233 Registers[REGISTER_A] = (BYTE)temp_word;
1234 Flags = Flags & (0xFF - FLAG_V);
1235 break;
1236
1237 case 0x38: //EOR AC
1238 temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_C];
1239 set_flag_n((BYTE)temp_word);
1240 set_flag_z((BYTE)temp_word);
1241 Registers[REGISTER_A] = (BYTE)temp_word;
1242 Flags = Flags & (0xFF - FLAG_V);
1243 break;
1244
1245 case 0x48: //EOR AD
1246 temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_D];
1247 set_flag_n((BYTE)temp_word);
1248 set_flag_z((BYTE)temp_word);
1249 Registers[REGISTER_A] = (BYTE)temp_word;
1250 Flags = Flags & (0xFF - FLAG_V);
1251 break;
1252
1253 case 0x58: //EOR AE
1254 temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_E];
1255 set_flag_n((BYTE)temp_word);
1256 set_flag_z((BYTE)temp_word);
1257 Registers[REGISTER_A] = (BYTE)temp_word;
1258 Flags = Flags & (0xFF - FLAG_V);
1259 break;
1260
1261 case 0x68: //EOR AF
1262 temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)Registers[REGISTER_F];
1263 set_flag_n((BYTE)temp_word);
1264 set_flag_z((BYTE)temp_word);
1265 Registers[REGISTER_A] = (BYTE)temp_word;
1266 Flags = Flags & (0xFF - FLAG_V);
1267 break;
1268
1269 ///////////////////////////////////////////
1270 // END EOR //
1271 //////////////////////////////////////////
1272
1273 case 0x02: //STX Abs
1274 HB = fetch();
1275 LB = fetch();
1276 address += (WORD)((WORD)HB << 8) + LB;
1277 if (address >= 0 && address < MEMORY_SIZE) {
1278 Memory[address] = Registers[REGISTER_X];
1279 }
1280 set_flag_n(Memory[address]);
1281 set_flag_z(Memory[address]);
1282 break;
1283
1284 case 0x12: //STX Abs Index X
1285 address += Index_Registers[REGISTER_X];
1286 HB = fetch();
1287 LB = fetch();
1288 address += (WORD)((WORD)HB << 8) + LB;
1289 if (address >= 0 && address < MEMORY_SIZE) {
1290 Memory[address] = Registers[REGISTER_X];
1291 }
1292 set_flag_n(Memory[address]);
1293 set_flag_z(Memory[address]);
1294 break;
1295
1296 case 0x22: //STX Abs Index Y
1297 address += Index_Registers[REGISTER_Y];
1298 HB = fetch();
1299 LB = fetch();
1300 address += (WORD)((WORD)HB << 8) + LB;
1301 if (address >= 0 && address < MEMORY_SIZE) {
1302 Memory[address] = Registers[REGISTER_X];
1303 }
1304 set_flag_n(Memory[address]);
1305 set_flag_z(Memory[address]);
1306 break;
1307
1308 case 0x32: //STX Abs Index abs xy
1309 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1310 HB = fetch();
1311 LB = fetch();
1312 address += (WORD)((WORD)HB << 8) + LB;
1313 if (address >= 0 && address < MEMORY_SIZE) {
1314 Memory[address] = Registers[REGISTER_X];
1315 }
1316 set_flag_n(Memory[address]);
1317 set_flag_z(Memory[address]);
1318 break;
1319
1320 case 0x42: //STX Abs Index xy
1321 HB = fetch();
1322 LB = fetch();
1323 address = (WORD)((WORD)HB << 8) + LB;
1324 HB = Memory[address];
1325 LB = Memory[address + 1];
1326 address = (WORD)((WORD)HB << 8) + LB;
1327 address += Index_Registers[REGISTER_X];
1328 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8);
1329 if (address >= 0 && address < MEMORY_SIZE) {
1330 Memory[address] = Registers[REGISTER_X];
1331 }
1332 set_flag_n(Memory[address]);
1333 set_flag_z(Memory[address]);
1334 break;
1335
1336 ///////////////////////////////////////////
1337 // END STX //
1338 //////////////////////////////////////////
1339
1340 case 0x9E:
1341
1342 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1343 Memory[StackPointer] = Registers[REGISTER_A];
1344 StackPointer--;
1345 }
1346 break;
1347
1348 case 0xAE:
1349 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1350 Memory[StackPointer] = Flags;
1351 StackPointer--;
1352 }
1353 break;
1354
1355 case 0xBE:
1356
1357 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1358 Memory[StackPointer] = Registers[REGISTER_B];
1359 StackPointer--;
1360 }
1361 break;
1362
1363 case 0xCE:
1364
1365 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1366 Memory[StackPointer] = Registers[REGISTER_C];
1367 StackPointer--;
1368 }
1369 break;
1370
1371 case 0xDE:
1372
1373 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1374 Memory[StackPointer] = Registers[REGISTER_D];
1375 StackPointer--;
1376 }
1377 break;
1378
1379 case 0xEE:
1380
1381 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1382 Memory[StackPointer] = Registers[REGISTER_E];
1383 StackPointer--;
1384 }
1385 break;
1386
1387 case 0xFE:
1388
1389 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1390 Memory[StackPointer] = Registers[REGISTER_F];
1391 StackPointer--;
1392 }
1393 break;
1394
1395 ///////////////////////////////////////////
1396 // END PUSH //
1397 //////////////////////////////////////////
1398
1399 case 0x9F:
1400 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1401 StackPointer++;
1402 Registers[REGISTER_A] = Memory[StackPointer];
1403 }
1404 break;
1405
1406 case 0xAF:
1407 if ((StackPointer >= 1) && (StackPointer < MEMORY_SIZE)) {
1408 StackPointer++;
1409 Flags = Memory[StackPointer];
1410 }
1411 break;
1412
1413 case 0xBF:
1414 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1415 StackPointer++;
1416 Registers[REGISTER_B] = Memory[StackPointer];
1417 }
1418 break;
1419
1420 case 0xCF:
1421 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1422 StackPointer++;
1423 Registers[REGISTER_C] = Memory[StackPointer];
1424 }
1425 break;
1426
1427 case 0xDF:
1428 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1429 StackPointer++;
1430 Registers[REGISTER_D] = Memory[StackPointer];
1431 }
1432 break;
1433
1434 case 0xEF:
1435 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1436 StackPointer++;
1437 Registers[REGISTER_E] = Memory[StackPointer];
1438 }
1439 break;
1440
1441 case 0xFF:
1442 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 1)) {
1443 StackPointer++;
1444 Registers[REGISTER_F] = Memory[StackPointer];
1445 }
1446 break;
1447
1448 ///////////////////////////////////////////
1449 // END POP //
1450 //////////////////////////////////////////
1451
1452 case 0x92: //INC Abs
1453 HB = fetch();
1454 LB = fetch();
1455 address += (WORD)((WORD)HB << 8) + LB;
1456 if (address >= 0 && address < MEMORY_SIZE)
1457 {
1458 Memory[address]++;
1459 }
1460 set_flag_n(Memory[address]);
1461 set_flag_z(Memory[address]);
1462 break;
1463
1464 case 0xA2: //INC Abs X
1465 address += Index_Registers[REGISTER_X];
1466 HB = fetch();
1467 LB = fetch();
1468 address += (WORD)((WORD)HB << 8) + LB;
1469 if (address >= 0 && address < MEMORY_SIZE)
1470 {
1471 Memory[address]++;
1472 }
1473 set_flag_n(Memory[address]);
1474 set_flag_z(Memory[address]);
1475 break;
1476
1477 case 0xB2: //INC Abs Y
1478 address += Index_Registers[REGISTER_Y];
1479 HB = fetch();
1480 LB = fetch();
1481 address += (WORD)((WORD)HB << 8) + LB;
1482 if (address >= 0 && address < MEMORY_SIZE)
1483 {
1484 Memory[address]++;
1485 }
1486 set_flag_n(Memory[address]);
1487 set_flag_z(Memory[address]);
1488 break;
1489
1490 case 0xC2: //INC Abs XY
1491 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1492 HB = fetch();
1493 LB = fetch();
1494 address += (WORD)((WORD)HB << 8) + LB;
1495 if (address >= 0 && address < MEMORY_SIZE)
1496 {
1497 Memory[address]++;
1498 }
1499 set_flag_n(Memory[address]);
1500 set_flag_z(Memory[address]);
1501 break;
1502
1503 ///////////////////////////////////////////
1504 // END INC //
1505 //////////////////////////////////////////
1506
1507 case 0xEA:
1508 HB - fetch();
1509 LB = fetch();
1510 address = ((WORD)HB << 8) + (WORD)LB;
1511 ProgramCounter = address;
1512 break;
1513
1514 ///////////////////////////////////////////
1515 // END JMP //
1516 //////////////////////////////////////////
1517
1518 case 0xE9: //JSR ABS
1519 HB - fetch();
1520 LB = fetch();
1521 address = ((WORD)HB << 8) + (WORD)LB;
1522 if ((StackPointer >= 3) && (StackPointer < MEMORY_SIZE)) {
1523 Memory[StackPointer] = (BYTE)(ProgramCounter & 0xFF);
1524 StackPointer--;
1525 Memory[StackPointer] = (BYTE)(ProgramCounter >> 8) & 0xFF;
1526 StackPointer--;
1527 }
1528 ProgramCounter = address;
1529 break;
1530
1531 ///////////////////////////////////////////
1532 // END JSR //
1533 //////////////////////////////////////////
1534
1535 case 0x9B:
1536 data = fetch();
1537 Registers[REGISTER_A] = data;
1538 set_flag_n(Registers[REGISTER_A]);
1539 set_flag_z(Registers[REGISTER_A]);
1540 data = fetch();
1541 Registers[REGISTER_B] = data;
1542 set_flag_n(Registers[REGISTER_B]);
1543 set_flag_z(Registers[REGISTER_B]);
1544 break;
1545
1546 ///////////////////////////////////////////
1547 // END LX //
1548 //////////////////////////////////////////
1549
1550 case 0xDB:
1551 if ((StackPointer >= 0) && (StackPointer < MEMORY_SIZE - 2)) {
1552 StackPointer++;
1553 HB = Memory[StackPointer];
1554 StackPointer++;
1555 LB = Memory[StackPointer];
1556 ProgramCounter = ((WORD)HB << 8) + (WORD)LB;
1557 }
1558 break;
1559
1560 ///////////////////////////////////////////
1561 // END RTN //
1562 //////////////////////////////////////////
1563
1564 case 0xF0://BRA rel
1565 HB = fetch();
1566 LB = fetch();
1567 offset = (WORD)LB;
1568 if ((offset & 0x80) != 0) {
1569 offset = offset + 0xFF00;
1570 } address = ProgramCounter + offset;
1571 ProgramCounter = address;
1572 break;
1573
1574 ///////////////////////////////////////////
1575 // END BRA //
1576 //////////////////////////////////////////
1577
1578 case 0xD2:
1579 ++Registers[REGISTER_A];
1580 set_flag_n(Registers[REGISTER_A]);
1581 set_flag_z(Registers[REGISTER_A]);
1582 break;
1583
1584 ///////////////////////////////////////////
1585 // END INCA //
1586 //////////////////////////////////////////
1587
1588 case 0xD3:
1589 --Registers[REGISTER_A];
1590 set_flag_n(Registers[REGISTER_A]);
1591 set_flag_z(Registers[REGISTER_A]);
1592 break;
1593
1594 ///////////////////////////////////////////
1595 // END DECA //
1596 //////////////////////////////////////////
1597
1598 case 0xE1:
1599 --Index_Registers[REGISTER_A];
1600 set_flag_z(Index_Registers[REGISTER_X]);
1601 break;
1602
1603 ///////////////////////////////////////////
1604 // END DEX //
1605 //////////////////////////////////////////
1606
1607 case 0xE2:
1608 ++Index_Registers[REGISTER_A];
1609 set_flag_z(Index_Registers[REGISTER_X]);
1610 break;
1611
1612 ///////////////////////////////////////////
1613 // END INX //
1614 //////////////////////////////////////////
1615
1616 case 0xE3:
1617 --Index_Registers[REGISTER_A];
1618 set_flag_z(Index_Registers[REGISTER_Y]);
1619 break;
1620
1621 ///////////////////////////////////////////
1622 // END DEY //
1623 //////////////////////////////////////////
1624
1625 case 0xE4:
1626 ++Index_Registers[REGISTER_A];
1627 set_flag_z(Index_Registers[REGISTER_Y]);
1628 break;
1629
1630 ///////////////////////////////////////////
1631 // END INCY //
1632 //////////////////////////////////////////
1633
1634 case 0x93: //DEC Abs
1635 HB = fetch();
1636 LB = fetch();
1637 address += (WORD)((WORD)HB << 8) + LB;
1638 --Memory[address];
1639 set_flag_n(Memory[address]);
1640 set_flag_z(Memory[address]);
1641 break;
1642
1643 case 0xA3: //DEC Abs X
1644 address += Index_Registers[REGISTER_X];
1645 HB = fetch();
1646 LB = fetch();
1647 address += (WORD)((WORD)HB << 8) + LB;
1648 --Memory[address];
1649 set_flag_n(Memory[address]);
1650 set_flag_z(Memory[address]);
1651 break;
1652
1653 case 0xB3: //DEC Abs Y
1654 address += Index_Registers[REGISTER_Y];
1655 HB = fetch();
1656 LB = fetch();
1657 address += (WORD)((WORD)HB << 8) + LB;
1658 --Memory[address];
1659 set_flag_n(Memory[address]);
1660 set_flag_z(Memory[address]);
1661 break;
1662
1663 case 0xC3: //DEC Abs XY
1664 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1665 HB = fetch();
1666 LB = fetch();
1667 address += (WORD)((WORD)HB << 8) + LB;
1668 --Memory[address];
1669 set_flag_n(Memory[address]);
1670 set_flag_z(Memory[address]);
1671 break;
1672
1673 ///////////////////////////////////////////
1674 // END DEC //
1675 //////////////////////////////////////////
1676
1677 case 0x27:
1678
1679 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_B];
1680 Flags = Flags & (0xFF - FLAG_V);
1681 set_flag_n((BYTE)temp_word);
1682 set_flag_z((BYTE)temp_word);
1683
1684 Registers[REGISTER_A] = (BYTE)temp_word;
1685 break;
1686
1687 case 0x37: //AND- a-c
1688 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_C];
1689 Flags = Flags & (0xFF - FLAG_V);
1690 set_flag_n((BYTE)temp_word);
1691 set_flag_z((BYTE)temp_word);
1692
1693 Registers[REGISTER_A] = (BYTE)temp_word;
1694 break;
1695
1696 case 0x47: //AND- a-d
1697 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_D];
1698 Flags = Flags & (0xFF - FLAG_V);
1699 set_flag_n((BYTE)temp_word);
1700 set_flag_z((BYTE)temp_word);
1701
1702 Registers[REGISTER_A] = (BYTE)temp_word;
1703 break;
1704
1705 case 0x57:
1706 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_E];
1707 Flags = Flags & (0xFF - FLAG_V);
1708 set_flag_n((BYTE)temp_word);
1709 set_flag_z((BYTE)temp_word);
1710
1711 Registers[REGISTER_A] = (BYTE)temp_word;
1712 break;
1713
1714 case 0x67: //AND- a-f
1715 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_F];
1716 Flags = Flags & (0xFF - FLAG_V);
1717 set_flag_n((BYTE)temp_word);
1718 set_flag_z((BYTE)temp_word);
1719
1720 Registers[REGISTER_A] = (BYTE)temp_word;
1721 break;
1722
1723 ///////////////////////////////////////////
1724 // END AND //
1725 //////////////////////////////////////////
1726
1727 case 0x29: //BT
1728 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_B];
1729 set_flag_n((BYTE)temp_word);
1730 set_flag_z((BYTE)temp_word);
1731 Flags = Flags & (0xFF - FLAG_V);
1732 break;
1733
1734 case 0x39: //BT
1735 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_C];
1736 set_flag_n((BYTE)temp_word);
1737 set_flag_z((BYTE)temp_word);
1738 Flags = Flags & (0xFF - FLAG_V);
1739 break;
1740
1741 case 0x49: //BT
1742 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_D];
1743 set_flag_n((BYTE)temp_word);
1744 set_flag_z((BYTE)temp_word);
1745 Flags = Flags & (0xFF - FLAG_V);
1746 break;
1747
1748 case 0x59: //BT
1749 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_E];
1750 set_flag_n((BYTE)temp_word);
1751 set_flag_z((BYTE)temp_word);
1752 Flags = Flags & (0xFF - FLAG_V);
1753 break;
1754
1755 case 0x69: //BT
1756 temp_word = (WORD)Registers[REGISTER_A] & (WORD)Registers[REGISTER_F];
1757 set_flag_n((BYTE)temp_word);
1758 set_flag_z((BYTE)temp_word);
1759 Flags = Flags & (0xFF - FLAG_V);
1760 break;
1761
1762 ///////////////////////////////////////////
1763 // END BT //
1764 //////////////////////////////////////////
1765
1766 case 0x94: //RCR Abs
1767 HB = fetch();
1768 LB = fetch();
1769 address += (WORD)((WORD)HB << 8) + LB;
1770 saved_flags = Flags;
1771 if ((Memory[address] & 0x01) == 0x01) {
1772 Flags = Flags | FLAG_C;
1773 }
1774 else {
1775 Flags = Flags & (0xFF - FLAG_C);
1776 }
1777 Memory[address] = (Memory[address] >> 1) & 0x7F;
1778 if ((saved_flags & FLAG_C) == FLAG_C) {
1779 Memory[address] = Memory[address] | 0x01;
1780 }
1781 set_flag_n(Memory[address]);
1782 set_flag_z(Memory[address]);
1783 break;
1784
1785 case 0xA4: //RCR Abs X
1786 address += Index_Registers[REGISTER_X];
1787 HB = fetch();
1788 LB = fetch();
1789 address += (WORD)((WORD)HB << 8) + LB;
1790 saved_flags = Flags;
1791 if ((Memory[address] & 0x01) == 0x01) {
1792 Flags = Flags | FLAG_C;
1793 }
1794 else {
1795 Flags = Flags & (0xFF - FLAG_C);
1796 }
1797 Memory[address] = (Memory[address] >> 1) & 0x7F;
1798 if ((saved_flags & FLAG_C) == FLAG_C) {
1799 Memory[address] = Memory[address] | 0x01;
1800 }
1801 set_flag_n(Memory[address]);
1802 set_flag_z(Memory[address]);
1803 break;
1804
1805 case 0xB4: //RCR Abs Y
1806 address += Index_Registers[REGISTER_Y];
1807 HB = fetch();
1808 LB = fetch();
1809 address += (WORD)((WORD)HB << 8) + LB;
1810 saved_flags = Flags;
1811 if ((Memory[address] & 0x01) == 0x01) {
1812 Flags = Flags | FLAG_C;
1813 }
1814 else {
1815 Flags = Flags & (0xFF - FLAG_C);
1816 }
1817 Memory[address] = (Memory[address] >> 1) & 0x7F;
1818 if ((saved_flags & FLAG_C) == FLAG_C) {
1819 Memory[address] = Memory[address] | 0x01;
1820 }
1821 set_flag_n(Memory[address]);
1822 set_flag_z(Memory[address]);
1823 break;
1824
1825 case 0xC4: //RCR Abs XY
1826 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1827 HB = fetch();
1828 LB = fetch();
1829 address += (WORD)((WORD)HB << 8) + LB;
1830 saved_flags = Flags;
1831 if ((Memory[address] & 0x01) == 0x01) {
1832 Flags = Flags | FLAG_C;
1833 }
1834 else {
1835 Flags = Flags & (0xFF - FLAG_C);
1836 }
1837 Memory[address] = (Memory[address] >> 1) & 0x7F;
1838 if ((saved_flags & FLAG_C) == FLAG_C) {
1839 Memory[address] = Memory[address] | 0x01;
1840 }
1841 set_flag_n(Memory[address]);
1842 set_flag_z(Memory[address]);
1843 break;
1844
1845 ///////////////////////////////////////////
1846 // END RCR //
1847 //////////////////////////////////////////
1848
1849 case 0x95: //RLC Abs
1850 HB = fetch();
1851 LB = fetch();
1852 address += (WORD)((WORD)HB << 8) + LB;
1853 saved_flags = Flags;
1854 if ((Memory[address] & 0x80) == 0x80) {
1855 Flags = Flags | FLAG_C;
1856 }
1857 else {
1858 Flags = Flags & (0xFF - FLAG_C);
1859 }
1860 Memory[address] = (Memory[address] << 1) & 0xFE;
1861 if ((saved_flags & FLAG_C) == FLAG_C) {
1862 Memory[address] = Memory[address] | 0x01;
1863 }
1864 set_flag_n(Memory[address]);
1865 set_flag_z(Memory[address]);
1866 break;
1867
1868 case 0xA5: //RLC Abs X
1869 address += Index_Registers[REGISTER_X];
1870 HB = fetch();
1871 LB = fetch();
1872 address += (WORD)((WORD)HB << 8) + LB;
1873 saved_flags = Flags;
1874 if ((Memory[address] & 0x80) == 0x80) {
1875 Flags = Flags | FLAG_C;
1876 }
1877 else {
1878 Flags = Flags & (0xFF - FLAG_C);
1879 }
1880 Memory[address] = (Memory[address] << 1) & 0xFE;
1881 if ((saved_flags & FLAG_C) == FLAG_C) {
1882 Memory[address] = Memory[address] | 0x01;
1883 }
1884 set_flag_n(Memory[address]);
1885 set_flag_z(Memory[address]);
1886 break;
1887
1888 case 0xB5: //RLC Abs Y
1889 address += Index_Registers[REGISTER_Y];
1890 HB = fetch();
1891 LB = fetch();
1892 address += (WORD)((WORD)HB << 8) + LB;
1893 saved_flags = Flags;
1894 if ((Memory[address] & 0x80) == 0x80) {
1895 Flags = Flags | FLAG_C;
1896 }
1897 else {
1898 Flags = Flags & (0xFF - FLAG_C);
1899 }
1900 Memory[address] = (Memory[address] << 1) & 0xFE;
1901 if ((saved_flags & FLAG_C) == FLAG_C) {
1902 Memory[address] = Memory[address] | 0x01;
1903 }
1904 set_flag_n(Memory[address]);
1905 set_flag_z(Memory[address]);
1906 break;
1907
1908 case 0xC5: //RLC Abs XY
1909 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1910 HB = fetch();
1911 LB = fetch();
1912 address += (WORD)((WORD)HB << 8) + LB;
1913 saved_flags = Flags;
1914 if ((Memory[address] & 0x80) == 0x80) {
1915 Flags = Flags | FLAG_C;
1916 }
1917 else {
1918 Flags = Flags & (0xFF - FLAG_C);
1919 }
1920 Memory[address] = (Memory[address] << 1) & 0xFE;
1921 if ((saved_flags & FLAG_C) == FLAG_C) {
1922 Memory[address] = Memory[address] | 0x01;
1923 }
1924 set_flag_n(Memory[address]);
1925 set_flag_z(Memory[address]);
1926 break;
1927
1928 ///////////////////////////////////////////
1929 // END RLC //
1930 //////////////////////////////////////////
1931
1932 case 0x96: //ASL Abs
1933 HB = fetch();
1934 LB = fetch();
1935 address += (WORD)((WORD)HB << 8) + LB;
1936 Memory[address] = (Memory[address] << 1) & 0xFE;
1937 set_flag_n(Memory[address]);
1938 set_flag_z(Memory[address]);
1939
1940 break;
1941
1942 case 0xA6: //ASL Abs X
1943 address += Index_Registers[REGISTER_X];
1944 HB = fetch();
1945 LB = fetch();
1946 address += (WORD)((WORD)HB << 8) + LB;
1947 Memory[address] = (Memory[address] << 1) & 0xFE;
1948 set_flag_n(Memory[address]);
1949 set_flag_z(Memory[address]);
1950
1951 break;
1952
1953 case 0xB6: //ASL Abs Y
1954 address += Index_Registers[REGISTER_Y];
1955 HB = fetch();
1956 LB = fetch();
1957 address += (WORD)((WORD)HB << 8) + LB;
1958 Memory[address] = (Memory[address] << 1) & 0xFE;
1959 set_flag_n(Memory[address]);
1960 set_flag_z(Memory[address]);
1961
1962 break;
1963
1964 case 0xC6: //ASL Abs XY
1965 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
1966 HB = fetch();
1967 LB = fetch();
1968 address += (WORD)((WORD)HB << 8) + LB;
1969 Memory[address] = (Memory[address] << 1) & 0xFE;
1970 set_flag_n(Memory[address]);
1971 set_flag_z(Memory[address]);
1972
1973 break;
1974
1975 ///////////////////////////////////////////
1976 // END ASL //
1977 //////////////////////////////////////////
1978
1979 case 0x97: //SAR Abs
1980 HB = fetch();
1981 LB = fetch();
1982 address += (WORD)((WORD)HB << 8) + LB;
1983 if ((Memory[address] & 0x01) == 0x01) {
1984 Flags = Flags | FLAG_C;
1985 }
1986 else {
1987 Flags = Flags & (0xFF - FLAG_C);
1988 }
1989 Memory[address] = (Memory[address] >> 1) & 0x7F;
1990 if ((Flags & FLAG_N) == FLAG_N) {
1991 Memory[address] = Memory[address] | 0x80;
1992 }
1993 set_flag_z(Memory[address]);
1994 break;
1995
1996 case 0xA7: //SAR Abs X
1997 address += Index_Registers[REGISTER_X];
1998 HB = fetch();
1999 LB = fetch();
2000 address += (WORD)((WORD)HB << 8) + LB;
2001 if ((Memory[address] & 0x01) == 0x01) {
2002 Flags = Flags | FLAG_C;
2003 }
2004 else {
2005 Flags = Flags & (0xFF - FLAG_C);
2006 }
2007 Memory[address] = (Memory[address] >> 1) & 0x7F;
2008 if ((Flags & FLAG_N) == FLAG_N) {
2009 Memory[address] = Memory[address] | 0x80;
2010 }
2011 set_flag_z(Memory[address]);
2012 break;
2013
2014 case 0xB7: //SAR Abs Y
2015 address += Index_Registers[REGISTER_Y];
2016 HB = fetch();
2017 LB = fetch();
2018 address += (WORD)((WORD)HB << 8) + LB;
2019 if ((Memory[address] & 0x01) == 0x01) {
2020 Flags = Flags | FLAG_C;
2021 }
2022 else {
2023 Flags = Flags & (0xFF - FLAG_C);
2024 }
2025 Memory[address] = (Memory[address] >> 1) & 0x7F;
2026 if ((Flags & FLAG_N) == FLAG_N) {
2027 Memory[address] = Memory[address] | 0x80;
2028 }
2029 set_flag_z(Memory[address]);
2030 break;
2031
2032 case 0xC7: //SAR Abs XY
2033 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2034 HB = fetch();
2035 LB = fetch();
2036 address += (WORD)((WORD)HB << 8) + LB;
2037 if ((Memory[address] & 0x01) == 0x01) {
2038 Flags = Flags | FLAG_C;
2039 }
2040 else {
2041 Flags = Flags & (0xFF - FLAG_C);
2042 }
2043 Memory[address] = (Memory[address] >> 1) & 0x7F;
2044 if ((Flags & FLAG_N) == FLAG_N) {
2045 Memory[address] = Memory[address] | 0x80;
2046 }
2047 set_flag_z(Memory[address]);
2048 break;
2049
2050 ///////////////////////////////////////////
2051 // END SAR //
2052 //////////////////////////////////////////
2053
2054 case 0xD4: //RCRA
2055 saved_flags = Flags;
2056 if ((Registers[REGISTER_A] & 0x01) == 0x01) {
2057 Flags = Flags | FLAG_C;
2058 }
2059 else {
2060 Flags = Flags & (0xFF - FLAG_C);
2061 }
2062 Registers[REGISTER_A] = (Registers[REGISTER_A] >> 1) & 0x7F;
2063 if ((saved_flags & FLAG_C) == FLAG_C) {
2064 Registers[REGISTER_A] = Registers[REGISTER_A] | 0x01;
2065 }
2066 set_flag_n(Registers[REGISTER_A]);
2067 set_flag_z(Registers[REGISTER_A]);
2068
2069 break;
2070
2071 ///////////////////////////////////////////
2072 // END RCRA //
2073 //////////////////////////////////////////
2074
2075 case 0xD5://RLCA
2076 saved_flags = Flags;
2077 if ((Registers[REGISTER_A] & 0x80) == 0x80) {
2078 Flags = Flags | FLAG_C;
2079 }
2080 else {
2081 Flags = Flags & (0xFF - FLAG_C);
2082 }
2083 Registers[REGISTER_A] = (Registers[REGISTER_A] << 1) & 0xFE;
2084 if ((saved_flags & FLAG_C) == FLAG_C) {
2085 Registers[REGISTER_A] = Registers[REGISTER_A] | 0x01;
2086 }
2087 break;
2088
2089 ///////////////////////////////////////////
2090 // END RLCA //
2091 //////////////////////////////////////////
2092
2093 case 0xD6: //ASLA
2094 Registers[REGISTER_A] = (Registers[REGISTER_A] << 1) & 0xFE;
2095 set_flag_n(Registers[REGISTER_A]);
2096 set_flag_z(Registers[REGISTER_A]);
2097 break;
2098
2099 ///////////////////////////////////////////
2100 // END ASLA //
2101 //////////////////////////////////////////
2102
2103 case 0xD7:
2104 if ((Registers[REGISTER_A] & 0x01) == 0x01) {
2105 Flags = Flags | FLAG_C;
2106 }
2107 else {
2108 Flags = Flags & (0xFF - FLAG_C);
2109 }
2110 Registers[REGISTER_A] = (Registers[REGISTER_A] >> 1) & 0x7F;
2111 if ((Flags & FLAG_N) == FLAG_N) {
2112 Registers[REGISTER_A] = Registers[REGISTER_A] | 0x80;
2113 }
2114 break;
2115
2116 ///////////////////////////////////////////
2117 // END SARA //
2118 //////////////////////////////////////////
2119
2120 case 0xD8:
2121 Registers[REGISTER_A] = ~Registers[REGISTER_A];
2122 if (data >= 0x100) {
2123 Flags = Flags | FLAG_C;
2124 }
2125 else
2126 {
2127 Flags = Flags & (0xFF - FLAG_C);
2128 }
2129 set_flag_n((BYTE)data);
2130 set_flag_z((BYTE)data);
2131
2132 Registers[REGISTER_A] = data;
2133 break;
2134
2135 ///////////////////////////////////////////
2136 // END COMA //
2137 //////////////////////////////////////////
2138
2139 case 0x98: //COM Abs
2140 HB = fetch();
2141 LB = fetch();
2142 address += (WORD)((WORD)HB << 8) + LB;
2143 if (address >= 0 && address < MEMORY_SIZE) {
2144 Memory[address] = ~Memory[address];
2145 }
2146 set_flag_n(Memory[address]);
2147 set_flag_z(Memory[address]);
2148 break;
2149
2150 case 0xA8: //COM Abs X
2151 address += Index_Registers[REGISTER_X];
2152 HB = fetch();
2153 LB = fetch();
2154 address += (WORD)((WORD)HB << 8) + LB;
2155 if (address >= 0 && address < MEMORY_SIZE) {
2156 Memory[address] = ~Memory[address];
2157 }
2158 set_flag_n(Memory[address]);
2159 set_flag_z(Memory[address]);
2160 break;
2161
2162 case 0xB8: //COM Abs Y
2163 address += Index_Registers[REGISTER_Y];
2164 HB = fetch();
2165 LB = fetch();
2166 address += (WORD)((WORD)HB << 8) + LB;
2167 if (address >= 0 && address < MEMORY_SIZE) {
2168 Memory[address] = ~Memory[address];
2169 }
2170 set_flag_n(Memory[address]);
2171 set_flag_z(Memory[address]);
2172 break;
2173
2174 case 0xC8: //COM Abs XY
2175 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2176 HB = fetch();
2177 LB = fetch();
2178 address += (WORD)((WORD)HB << 8) + LB;
2179 if (address >= 0 && address < MEMORY_SIZE) {
2180 Memory[address] = ~Memory[address];
2181 }
2182 set_flag_n(Memory[address]);
2183 set_flag_z(Memory[address]);
2184 break;
2185
2186 ///////////////////////////////////////////
2187 // END COM //
2188 //////////////////////////////////////////
2189
2190 case 0x2A:
2191 Registers[REGISTER_A] = Registers[REGISTER_A];
2192 break;
2193
2194 case 0x3A:
2195 Registers[REGISTER_A] = Registers[REGISTER_B];
2196 break;
2197
2198 case 0x4A:
2199 Registers[REGISTER_A] = Registers[REGISTER_C];
2200 break;
2201
2202 case 0x5A:
2203 Registers[REGISTER_A] = Registers[REGISTER_D];
2204 break;
2205
2206 case 0x6A:
2207 Registers[REGISTER_A] = Registers[REGISTER_E];
2208 break;
2209
2210 case 0x7A:
2211 Registers[REGISTER_A] = Registers[REGISTER_F];
2212 break;
2213
2214 case 0x2B:
2215 Registers[REGISTER_B] = Registers[REGISTER_A];
2216 break;
2217
2218 case 0x3B:
2219 Registers[REGISTER_B] = Registers[REGISTER_B];
2220 break;
2221
2222 case 0x4B:
2223 Registers[REGISTER_B] = Registers[REGISTER_C];
2224 break;
2225
2226 case 0x5B:
2227 Registers[REGISTER_B] = Registers[REGISTER_D];
2228 break;
2229
2230 case 0x6B:
2231 Registers[REGISTER_B] = Registers[REGISTER_E];
2232 break;
2233
2234 case 0x7B:
2235 Registers[REGISTER_B] = Registers[REGISTER_F];
2236 break;
2237
2238 case 0x2C:
2239 Registers[REGISTER_C] = Registers[REGISTER_A];
2240 break;
2241
2242 case 0x3C:
2243 Registers[REGISTER_C] = Registers[REGISTER_B];
2244 break;
2245
2246 case 0x4C:
2247 Registers[REGISTER_C] = Registers[REGISTER_C];
2248 break;
2249
2250 case 0x5C:
2251 Registers[REGISTER_C] = Registers[REGISTER_D];
2252 break;
2253
2254 case 0x6C:
2255 Registers[REGISTER_C] = Registers[REGISTER_E];
2256 break;
2257
2258 case 0x7C:
2259 Registers[REGISTER_C] = Registers[REGISTER_F];
2260 break;
2261
2262 case 0x2D:
2263 Registers[REGISTER_D] = Registers[REGISTER_A];
2264 break;
2265
2266 case 0x3D:
2267 Registers[REGISTER_D] = Registers[REGISTER_B];
2268 break;
2269
2270 case 0x4D:
2271 Registers[REGISTER_D] = Registers[REGISTER_C];
2272 break;
2273
2274 case 0x5D:
2275 Registers[REGISTER_D] = Registers[REGISTER_D];
2276 break;
2277
2278 case 0x6D:
2279 Registers[REGISTER_D] = Registers[REGISTER_E];
2280 break;
2281
2282 case 0x7D:
2283 Registers[REGISTER_D] = Registers[REGISTER_F];
2284 break;
2285
2286 case 0x2E:
2287 Registers[REGISTER_E] = Registers[REGISTER_A];
2288 break;
2289
2290 case 0x3E:
2291 Registers[REGISTER_E] = Registers[REGISTER_B];
2292 break;
2293
2294 case 0x4E:
2295 Registers[REGISTER_E] = Registers[REGISTER_C];
2296 break;
2297
2298 case 0x5E:
2299 Registers[REGISTER_E] = Registers[REGISTER_D];
2300 break;
2301
2302 case 0x6E:
2303 Registers[REGISTER_E] = Registers[REGISTER_E];
2304 break;
2305
2306 case 0x7E:
2307 Registers[REGISTER_E] = Registers[REGISTER_F];
2308 break;
2309
2310 case 0x2F:
2311 Registers[REGISTER_F] = Registers[REGISTER_A];
2312 break;
2313
2314 case 0x3F:
2315 Registers[REGISTER_F] = Registers[REGISTER_B];
2316 break;
2317
2318 case 0x4F:
2319 Registers[REGISTER_F] = Registers[REGISTER_C];
2320 break;
2321
2322 case 0x5F:
2323 Registers[REGISTER_F] = Registers[REGISTER_D];
2324 break;
2325
2326 case 0x6F:
2327 Registers[REGISTER_F] = Registers[REGISTER_E];
2328 break;
2329
2330 case 0x7F:
2331 Registers[REGISTER_F] = Registers[REGISTER_F];
2332 break;
2333
2334 ///////////////////////////////////////////
2335 // END LD //
2336 //////////////////////////////////////////
2337
2338 case 0xDA:
2339 data = (Registers[REGISTER_A] << 1);
2340 if ((Registers[REGISTER_A] & 0x01) == 0x01);
2341 {
2342 data = data | 0x80;
2343 }
2344 set_flag_n((BYTE)data);
2345 set_flag_z((BYTE)data);
2346 Registers[REGISTER_A] = data;
2347 break;
2348
2349 ///////////////////////////////////////////
2350 // END RORA //
2351 //////////////////////////////////////////
2352
2353 case 0x82: //ADI
2354 data = fetch();
2355 temp_word = (WORD)Registers[REGISTER_A] + data;
2356 if ((Flags &FLAG_C) != 0) {
2357 temp_word++;
2358 }
2359 if (temp_word >= 0x100) {
2360 Flags = Flags | FLAG_C;
2361 }
2362 set_flag_n((BYTE)temp_word);
2363 set_flag_z((BYTE)temp_word);
2364 set_flag_v(Registers[REGISTER_A], data, (BYTE)temp_word);
2365 Registers[REGISTER_A] = (BYTE)temp_word;
2366 break;
2367
2368 ///////////////////////////////////////////
2369 // END ADI //
2370 //////////////////////////////////////////
2371
2372
2373 case 0x86: // ANI
2374 data = fetch();
2375 temp_word = (WORD)Registers[REGISTER_A] & (WORD)data;
2376 if ((Flags & FLAG_C) != 0)
2377 {
2378 temp_word++;
2379 }
2380 if (temp_word >= 0x100)
2381 {
2382 Flags = Flags | FLAG_C;
2383 }
2384 else
2385 {
2386 Flags = Flags & (0xFF - FLAG_C);
2387 }
2388 set_flag_n((BYTE)temp_word);
2389 set_flag_z((BYTE)temp_word);
2390 Registers[REGISTER_A] = (BYTE)temp_word;
2391 break;
2392
2393
2394 case 0x87: // XRI #
2395 data = fetch();
2396 temp_word = (WORD)Registers[REGISTER_A] ^ (WORD)data;
2397 if ((Flags & FLAG_C) != 0)
2398 {
2399 temp_word++;
2400 }
2401 if (temp_word >= 0x100)
2402 {
2403 Flags = Flags | FLAG_C;
2404 }
2405 else
2406 {
2407 Flags = Flags & (0xFF - FLAG_C);
2408 }
2409 set_flag_n((BYTE)temp_word);
2410 set_flag_z((BYTE)temp_word);
2411 Registers[REGISTER_A] = (BYTE)temp_word;
2412 break;
2413
2414
2415 case 0xF1: // BCC rel
2416 LB = fetch();
2417 offset = (WORD)LB;
2418 if ((offset & 0x80) != 0)
2419 {
2420
2421 offset = offset + 0xFF00;
2422 }
2423 address = ProgramCounter + offset;
2424 if ((Flags & FLAG_C) == 0)
2425 {
2426 ProgramCounter = address;
2427 }
2428 break;
2429
2430 case 0xF2: // BCS rel
2431 LB = fetch();
2432 offset = (WORD)LB;
2433 if ((offset & 0x80) != 0)
2434 {
2435
2436 offset = offset + 0xFF00;
2437 }
2438 address = ProgramCounter + offset;
2439 if ((Flags & FLAG_C) != 0)
2440 {
2441 ProgramCounter = address;
2442 }
2443 break;
2444
2445
2446
2447
2448 case 0xF3: // BNE rel
2449 LB = fetch();
2450 offset = (WORD)LB;
2451 if ((offset & 0x80) != 0)
2452 {
2453
2454 offset = offset + 0xFF00;
2455 }
2456 address = ProgramCounter + offset;
2457 if ((Flags & FLAG_Z) != 0)
2458 {
2459 ProgramCounter = address;
2460 }
2461 break;
2462
2463
2464
2465
2466
2467 case 0xF4: // BEQ rel
2468 LB = fetch();
2469 offset = (WORD)LB;
2470 if ((offset & 0x80) != 0)
2471 {
2472
2473 offset = offset + 0xFF00;
2474 }
2475 address = ProgramCounter + offset;
2476 if ((Flags & FLAG_Z) != 0)
2477 {
2478 ProgramCounter = address;
2479 }
2480 break;
2481
2482 case 0xF6: // BVS rel
2483 LB = fetch();
2484 offset = (WORD)LB;
2485 if ((offset & 0x80) != 0)
2486 {
2487 offset = offset + 0xFF00;
2488 }
2489 address = ProgramCounter + offset;
2490 if ((Flags & FLAG_V) == 1)
2491 {
2492 ProgramCounter = address;
2493 }
2494 break;
2495
2496
2497 case 0xF7: // BMI rel
2498 LB = fetch();
2499 offset = (WORD)LB;
2500 if ((offset & 0x80) != 0)
2501 {
2502
2503 offset = offset + 0xFF00;
2504 }
2505 address = ProgramCounter + offset;
2506 if ((Flags & FLAG_N) == 1)
2507 {
2508 ProgramCounter = address;
2509 }
2510 break;
2511
2512
2513 case 0xF8: // BPL rel
2514 LB = fetch();
2515 offset = (WORD)LB;
2516 if ((offset & 0x80) != 0)
2517 {
2518
2519 offset = offset + 0xFF00;
2520 }
2521 address = ProgramCounter + offset;
2522 if ((Flags & FLAG_N) == 0)
2523 {
2524 ProgramCounter = address;
2525 }
2526 break;
2527
2528
2529
2530
2531
2532 case 0xF9: // BGE rel
2533 LB = fetch();
2534 offset = (WORD)LB;
2535 if ((offset & 0x80) != 0)
2536 {
2537
2538 offset = offset + 0xFF00;
2539 }
2540 address = ProgramCounter + offset;
2541 if ((Flags & FLAG_Z) == 1 || (Flags & FLAG_N) == 1)
2542 {
2543 ProgramCounter = address;
2544 }
2545 break;
2546
2547
2548 case 0x91:// TST abs
2549 HB = fetch();
2550 LB = fetch();
2551
2552 address += (WORD)((WORD)HB << 8) + LB;
2553
2554 temp_word = (WORD)(WORD)Memory[address] - 0x00;
2555
2556 Memory[address] = (BYTE)temp_word;
2557
2558 set_flag_n((BYTE)temp_word);
2559 set_flag_z((BYTE)temp_word);
2560 break;
2561
2562
2563 case 0xA1: // TST abs,X
2564 address += Index_Registers[REGISTER_X];
2565
2566 HB = fetch();
2567 LB = fetch();
2568
2569 address += (WORD)((WORD)HB << 8) + LB;
2570
2571 temp_word = (WORD)(WORD)Memory[address] - 0x00;
2572
2573 Memory[address] = (BYTE)temp_word;
2574
2575 set_flag_n((BYTE)temp_word);
2576 set_flag_z((BYTE)temp_word);
2577 break;
2578
2579
2580 case 0xB1: // TST abs,Y
2581 address += Index_Registers[REGISTER_Y];
2582
2583 HB = fetch();
2584 LB = fetch();
2585
2586 address += (WORD)((WORD)HB << 8) + LB;
2587
2588 temp_word = (WORD)(WORD)Memory[address] - 0x00;
2589
2590 Memory[address] = (BYTE)temp_word;
2591
2592 set_flag_n((BYTE)temp_word);
2593 set_flag_z((BYTE)temp_word);
2594 break;
2595
2596
2597 case 0xC1: // TST abs,XY
2598 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2599
2600 HB = fetch();
2601 LB = fetch();
2602
2603 address += (WORD)((WORD)HB << 8) + LB;
2604
2605 temp_word = (WORD)(WORD)Memory[address] - 0x00;
2606
2607 Memory[address] = (BYTE)temp_word;
2608
2609 set_flag_n((BYTE)temp_word);
2610 set_flag_z((BYTE)temp_word);
2611 break;
2612
2613
2614 case 0xFA: // BLE rel
2615 HB = fetch();
2616 LB = fetch();
2617 address += (WORD)((WORD)HB << 8) + LB;
2618 if (address >= 0 && address < MEMORY_SIZE)
2619 {
2620 if ((Flags & FLAG_N) >= 0)
2621 {
2622 Memory[StackPointer] = ProgramCounter;
2623 StackPointer--;
2624 ProgramCounter = address;
2625 }
2626 }
2627 break;
2628
2629
2630 case 0xFB: // BGT rel
2631 HB = fetch();
2632 LB = fetch();
2633 address += (WORD)((WORD)HB << 8) + LB;
2634 if (address >= 0 && address < MEMORY_SIZE)
2635 {
2636 if ((Flags & FLAG_N) < 0)
2637 {
2638 Memory[StackPointer] = ProgramCounter;
2639 StackPointer--;
2640 ProgramCounter = address;
2641 }
2642 }
2643 break;
2644
2645 case 0x9A: // ROR abs
2646 HB = fetch();
2647 LB = fetch();
2648 address += (WORD)((WORD)HB << 8) + LB;
2649
2650 data = (Memory[address] >> 1);
2651
2652 if ((Memory[address] & 0x01) == 0x01)
2653 {
2654 data = data | 0x80;
2655 }
2656
2657 set_flag_n((BYTE)data);
2658 set_flag_z((BYTE)data);
2659 Memory[address] = data;
2660 break;
2661
2662
2663 case 0xAA: // ROR abs,X
2664 address += Index_Registers[REGISTER_X];
2665
2666 HB = fetch();
2667 LB = fetch();
2668 address += (WORD)((WORD)HB << 8) + LB;
2669
2670 data = (Memory[address] >> 1);
2671
2672 if ((Memory[address] & 0x01) == 0x01)
2673 {
2674 data = data | 0x80;
2675 }
2676
2677 set_flag_n((BYTE)data);
2678 set_flag_z((BYTE)data);
2679 Memory[address] = data;
2680 break;
2681
2682 case 0xBA: // ROR abs,Y
2683 address += Index_Registers[REGISTER_Y];
2684
2685 HB = fetch();
2686 LB = fetch();
2687 address += (WORD)((WORD)HB << 8) + LB;
2688
2689 data = (Memory[address] >> 1);
2690
2691 if ((Memory[address] & 0x01) == 0x01)
2692 {
2693 data = data | 0x80;
2694 }
2695
2696 set_flag_n((BYTE)data);
2697 set_flag_z((BYTE)data);
2698 Memory[address] = data;
2699 break;
2700
2701
2702 case 0xCA: // ROR abs,XY
2703 address += (WORD)((WORD)Index_Registers[REGISTER_Y] << 8) + Index_Registers[REGISTER_X];
2704
2705 HB = fetch();
2706 LB = fetch();
2707 address += (WORD)((WORD)HB << 8) + LB;
2708
2709 data = (Memory[address] >> 1);
2710
2711 if ((Memory[address] & 0x01) == 0x01)
2712 {
2713 data = data | 0x80;
2714 }
2715
2716 set_flag_n((BYTE)data);
2717 set_flag_z((BYTE)data);
2718 Memory[address] = data;
2719 break;
2720 }
2721}
2722
2723///////////////////////////////////////////
2724// END MAIN //
2725//////////////////////////////////////////
2726
2727void Group_2_Move(BYTE opcode)
2728{
2729 BYTE source = opcode >> 4;
2730 BYTE destination = opcode & 0x0F;
2731 int destReg = 0;
2732 int sourceReg = 0;
2733
2734 switch (destination) //MV Destination
2735 {
2736 case 0x0A:
2737 destReg = REGISTER_A;
2738
2739 break;
2740
2741 case 0x0B:
2742 destReg = REGISTER_B;
2743
2744 break;
2745
2746 case 0x0C:
2747 destReg = REGISTER_C;
2748
2749 break;
2750
2751 case 0x0D:
2752 destReg = REGISTER_D;
2753
2754 break;
2755
2756 case 0x0E:
2757 destReg = REGISTER_E;
2758
2759 break;
2760
2761 case 0x0F:
2762 destReg = REGISTER_F;
2763
2764 break;
2765 }
2766
2767 switch (source) //MV Source
2768 {
2769 case 0x02:
2770 sourceReg = REGISTER_A;
2771
2772 break;
2773
2774 case 0x03:
2775 sourceReg = REGISTER_B;
2776
2777 break;
2778
2779 case 0x04:
2780 sourceReg = REGISTER_C;
2781
2782 break;
2783
2784 case 0x05:
2785 sourceReg = REGISTER_D;
2786
2787 break;
2788
2789 case 0x06:
2790 sourceReg = REGISTER_E;
2791
2792 break;
2793
2794 case 0x07:
2795 sourceReg = REGISTER_F;
2796
2797 break;
2798
2799 }
2800 Registers[destReg] = Registers[sourceReg];
2801}
2802
2803////////////////////////////////////////////////////
2804// END MOVEMENT COMPARISON LD //
2805//////////////////////////////////////////////////
2806
2807void execute(BYTE opcode)
2808{
2809 if (((opcode >= 0x2A) && (opcode <= 0x2F))
2810 || ((opcode >= 0x3A) && (opcode <= 0x3F))
2811 || ((opcode >= 0x4A) && (opcode <= 0x4F))
2812 || ((opcode >= 0x5A) && (opcode <= 0x5F))
2813 || ((opcode >= 0x6A) && (opcode <= 0x6F))
2814 || ((opcode >= 0x7A) && (opcode <= 0x7F)))
2815 {
2816 Group_2_Move(opcode);
2817 }
2818 else
2819 {
2820 Group_1(opcode);
2821 }
2822}
2823
2824void emulate()
2825{
2826 BYTE opcode;
2827 int sanity;
2828
2829 sanity = 0;
2830 ProgramCounter = 0;
2831 halt = false;
2832 memory_in_range = true;
2833
2834 //printf(" A B C D E F X Y SP\n");
2835
2836 while ((!halt) && (memory_in_range)) {
2837 sanity++;
2838 if (sanity > 500) halt = true;
2839 //printf("%04X ", ProgramCounter); // Print current address
2840 opcode = fetch();
2841 execute(opcode);
2842
2843 //printf("%s ", opcode_mneumonics[opcode]); // Print current opcode
2844
2845 //printf("%02X ", Registers[REGISTER_A]);
2846 //printf("%02X ", Registers[REGISTER_B]);
2847 //printf("%02X ", Registers[REGISTER_C]);
2848 //printf("%02X ", Registers[REGISTER_D]);
2849 //printf("%02X ", Registers[REGISTER_E]);
2850 //printf("%02X ", Registers[REGISTER_F]);
2851 //printf("%02X ", Index_Registers[REGISTER_X]);
2852 //printf("%02X ", Index_Registers[REGISTER_Y]);
2853 //printf("%04X ", StackPointer); // Print Stack Pointer
2854
2855 //if ((Flags & FLAG_I) == FLAG_I)
2856 //{
2857 // printf("I=1 ");
2858 //}
2859 //else
2860 //{
2861 // printf("I=0 ");
2862 //}
2863 //if ((Flags & FLAG_V) == FLAG_V)
2864 //{
2865 // printf("V=1 ");
2866 //}
2867 //else
2868 //{
2869 // printf("V=0 ");
2870 //}
2871 //if ((Flags & FLAG_N) == FLAG_N)
2872 //{
2873 // printf("N=1 ");
2874 //}
2875 //else
2876 //{
2877 // printf("N=0 ");
2878 //}
2879 //if ((Flags & FLAG_Z) == FLAG_Z)
2880 //{
2881 // printf("Z=1 ");
2882 //}
2883 //else
2884 //{
2885 // printf("Z=0 ");
2886 //}
2887 //if ((Flags & FLAG_C) == FLAG_C)
2888 //{
2889 // printf("C=1 ");
2890 //}
2891 //else
2892 //{
2893 // printf("C=0 ");
2894 //}
2895
2896 //printf("\n"); // New line
2897 }
2898
2899 //printf("\n"); // New line
2900}
2901
2902
2903////////////////////////////////////////////////////////////////////////////////
2904// Simulator/Emulator (End) //
2905////////////////////////////////////////////////////////////////////////////////
2906
2907
2908void initialise_filenames() {
2909 int i;
2910
2911 for (i = 0; i<MAX_FILENAME_SIZE; i++) {
2912 hex_file[i] = '\0';
2913 trc_file[i] = '\0';
2914 }
2915}
2916
2917
2918
2919
2920int find_dot_position(char *filename) {
2921 int dot_position;
2922 int i;
2923 char chr;
2924
2925 dot_position = 0;
2926 i = 0;
2927 chr = filename[i];
2928
2929 while (chr != '\0') {
2930 if (chr == '.') {
2931 dot_position = i;
2932 }
2933 i++;
2934 chr = filename[i];
2935 }
2936
2937 return (dot_position);
2938}
2939
2940
2941int find_end_position(char *filename) {
2942 int end_position;
2943 int i;
2944 char chr;
2945
2946 end_position = 0;
2947 i = 0;
2948 chr = filename[i];
2949
2950 while (chr != '\0') {
2951 end_position = i;
2952 i++;
2953 chr = filename[i];
2954 }
2955
2956 return (end_position);
2957}
2958
2959
2960bool file_exists(char *filename) {
2961 bool exists;
2962 FILE *ifp;
2963
2964 exists = false;
2965
2966 if ((ifp = fopen(filename, "r")) != NULL) {
2967 exists = true;
2968
2969 fclose(ifp);
2970 }
2971
2972 return (exists);
2973}
2974
2975
2976
2977void create_file(char *filename) {
2978 FILE *ofp;
2979
2980 if ((ofp = fopen(filename, "w")) != NULL) {
2981 fclose(ofp);
2982 }
2983}
2984
2985
2986
2987bool getline(FILE *fp, char *buffer) {
2988 bool rc;
2989 bool collect;
2990 char c;
2991 int i;
2992
2993 rc = false;
2994 collect = true;
2995
2996 i = 0;
2997 while (collect) {
2998 c = getc(fp);
2999
3000 switch (c) {
3001 case EOF:
3002 if (i > 0) {
3003 rc = true;
3004 }
3005 collect = false;
3006 break;
3007
3008 case '\n':
3009 if (i > 0) {
3010 rc = true;
3011 collect = false;
3012 buffer[i] = '\0';
3013 }
3014 break;
3015
3016 default:
3017 buffer[i] = c;
3018 i++;
3019 break;
3020 }
3021 }
3022
3023 return (rc);
3024}
3025
3026
3027
3028
3029
3030
3031void load_and_run(int args, _TCHAR** argv) {
3032 char chr;
3033 int ln;
3034 int dot_position;
3035 int end_position;
3036 long i;
3037 FILE *ifp;
3038 long address;
3039 long load_at;
3040 int code;
3041
3042 // Prompt for the .hex file
3043
3044 printf("\n");
3045 printf("Enter the hex filename (.hex): ");
3046
3047 if (args == 2) {
3048 ln = 0;
3049 chr = argv[1][ln];
3050 while (chr != '\0')
3051 {
3052 if (ln < MAX_FILENAME_SIZE)
3053 {
3054 hex_file[ln] = chr;
3055 trc_file[ln] = chr;
3056 ln++;
3057 }
3058 chr = argv[1][ln];
3059 }
3060 }
3061 else {
3062 ln = 0;
3063 chr = '\0';
3064 while (chr != '\n') {
3065 chr = getchar();
3066
3067 switch (chr) {
3068 case '\n':
3069 break;
3070 default:
3071 if (ln < MAX_FILENAME_SIZE) {
3072 hex_file[ln] = chr;
3073 trc_file[ln] = chr;
3074 ln++;
3075 }
3076 break;
3077 }
3078 }
3079
3080 }
3081 // Tidy up the file names
3082
3083 dot_position = find_dot_position(hex_file);
3084 if (dot_position == 0) {
3085 end_position = find_end_position(hex_file);
3086
3087 hex_file[end_position + 1] = '.';
3088 hex_file[end_position + 2] = 'h';
3089 hex_file[end_position + 3] = 'e';
3090 hex_file[end_position + 4] = 'x';
3091 hex_file[end_position + 5] = '\0';
3092 }
3093 else {
3094 hex_file[dot_position + 0] = '.';
3095 hex_file[dot_position + 1] = 'h';
3096 hex_file[dot_position + 2] = 'e';
3097 hex_file[dot_position + 3] = 'x';
3098 hex_file[dot_position + 4] = '\0';
3099 }
3100
3101 dot_position = find_dot_position(trc_file);
3102 if (dot_position == 0) {
3103 end_position = find_end_position(trc_file);
3104
3105 trc_file[end_position + 1] = '.';
3106 trc_file[end_position + 2] = 't';
3107 trc_file[end_position + 3] = 'r';
3108 trc_file[end_position + 4] = 'c';
3109 trc_file[end_position + 5] = '\0';
3110 }
3111 else {
3112 trc_file[dot_position + 0] = '.';
3113 trc_file[dot_position + 1] = 't';
3114 trc_file[dot_position + 2] = 'r';
3115 trc_file[dot_position + 3] = 'c';
3116 trc_file[dot_position + 4] = '\0';
3117 }
3118
3119 if (file_exists(hex_file)) {
3120 // Clear Registers and Memory
3121
3122 Registers[REGISTER_A] = 0;
3123 Registers[REGISTER_B] = 0;
3124 Registers[REGISTER_C] = 0;
3125 Registers[REGISTER_D] = 0;
3126 Registers[REGISTER_E] = 0;
3127 Registers[REGISTER_F] = 0;
3128 Index_Registers[REGISTER_X] = 0;
3129 Index_Registers[REGISTER_Y] = 0;
3130 Flags = 0;
3131 ProgramCounter = 0;
3132 StackPointer = 0;
3133
3134 for (i = 0; i<MEMORY_SIZE; i++) {
3135 Memory[i] = 0x00;
3136 }
3137
3138 // Load hex file
3139
3140 if ((ifp = fopen(hex_file, "r")) != NULL) {
3141 printf("Loading file...\n\n");
3142
3143 load_at = 0;
3144
3145 while (getline(ifp, InputBuffer)) {
3146 if (sscanf(InputBuffer, "L=%x", &address) == 1) {
3147 load_at = address;
3148 }
3149 else if (sscanf(InputBuffer, "%x", &code) == 1) {
3150 if ((load_at >= 0) && (load_at <= MEMORY_SIZE)) {
3151 Memory[load_at] = (BYTE)code;
3152 }
3153 load_at++;
3154 }
3155 else {
3156 printf("ERROR> Failed to load instruction: %s \n", InputBuffer);
3157 }
3158 }
3159
3160 fclose(ifp);
3161 }
3162
3163 // Emulate
3164
3165 emulate();
3166 }
3167 else {
3168 printf("\n");
3169 printf("ERROR> Input file %s does not exist!\n", hex_file);
3170 printf("\n");
3171 }
3172}
3173
3174void building(int args, _TCHAR** argv) {
3175 char buffer[1024];
3176 load_and_run(args, argv);
3177 sprintf(buffer, "0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X,0x%02X",
3178 Memory[TEST_ADDRESS_1],
3179 Memory[TEST_ADDRESS_2],
3180 Memory[TEST_ADDRESS_3],
3181 Memory[TEST_ADDRESS_4],
3182 Memory[TEST_ADDRESS_5],
3183 Memory[TEST_ADDRESS_6],
3184 Memory[TEST_ADDRESS_7],
3185 Memory[TEST_ADDRESS_8],
3186 Memory[TEST_ADDRESS_9],
3187 Memory[TEST_ADDRESS_10],
3188 Memory[TEST_ADDRESS_11],
3189 Memory[TEST_ADDRESS_12]
3190 );
3191 sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
3192}
3193
3194
3195
3196void test_and_mark() {
3197 char buffer[1024];
3198 bool testing_complete;
3199 int len = sizeof(SOCKADDR);
3200 char chr;
3201 int i;
3202 int j;
3203 bool end_of_program;
3204 long address;
3205 long load_at;
3206 int code;
3207 int mark;
3208 int passed;
3209
3210 printf("\n");
3211 printf("Automatic Testing and Marking\n");
3212 printf("\n");
3213
3214 testing_complete = false;
3215
3216 sprintf(buffer, "Test Student %s", STUDENT_NUMBER);
3217 sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
3218
3219 while (!testing_complete) {
3220 memset(buffer, '\0', sizeof(buffer));
3221
3222 if (recvfrom(sock, buffer, sizeof(buffer) - 1, 0, (SOCKADDR *)&client_addr, &len) != SOCKET_ERROR) {
3223 //printf("Incoming Data: %s \n", buffer);
3224
3225 //if (strcmp(buffer, "Testing complete") == 1)
3226 if (sscanf(buffer, "Testing complete %d", &mark) == 1) {
3227 testing_complete = true;
3228 printf("Current mark = %d\n", mark);
3229
3230 }
3231 else if (sscanf(buffer, "Tests passed %d", &passed) == 1) {
3232 //testing_complete = true;
3233 printf("Passed = %d\n", passed);
3234
3235 }
3236 else if (strcmp(buffer, "Error") == 0) {
3237 printf("ERROR> Testing abnormally terminated\n");
3238 testing_complete = true;
3239 }
3240 else {
3241 // Clear Registers and Memory
3242
3243 Registers[REGISTER_A] = 0;
3244 Registers[REGISTER_B] = 0;
3245 Registers[REGISTER_C] = 0;
3246 Registers[REGISTER_D] = 0;
3247 Registers[REGISTER_E] = 0;
3248 Registers[REGISTER_F] = 0;
3249 Index_Registers[REGISTER_X] = 0;
3250 Index_Registers[REGISTER_Y] = 0;
3251 Flags = 0;
3252 ProgramCounter = 0;
3253 StackPointer = 0;
3254 for (i = 0; i<MEMORY_SIZE; i++) {
3255 Memory[i] = 0;
3256 }
3257
3258 // Load hex file
3259
3260 i = 0;
3261 j = 0;
3262 load_at = 0;
3263 end_of_program = false;
3264 FILE *ofp;
3265 fopen_s(&ofp, "branch.txt", "a");
3266
3267 while (!end_of_program) {
3268 chr = buffer[i];
3269 switch (chr) {
3270 case '\0':
3271 end_of_program = true;
3272
3273 case ',':
3274 if (sscanf(InputBuffer, "L=%x", &address) == 1) {
3275 load_at = address;
3276 }
3277 else if (sscanf(InputBuffer, "%x", &code) == 1) {
3278 if ((load_at >= 0) && (load_at <= MEMORY_SIZE)) {
3279 Memory[load_at] = (BYTE)code;
3280 fprintf(ofp, "%02X\n", (BYTE)code);
3281 }
3282 load_at++;
3283 }
3284 else {
3285 printf("ERROR> Failed to load instruction: %s \n", InputBuffer);
3286 }
3287 j = 0;
3288 break;
3289
3290 default:
3291 InputBuffer[j] = chr;
3292 j++;
3293 break;
3294 }
3295 i++;
3296 }
3297 fclose(ofp);
3298 // Emulate
3299
3300 if (load_at > 1) {
3301 emulate();
3302 // Send and store results
3303 sprintf(buffer, "%02X%02X %02X%02X %02X%02X %02X%02X %02X%02X %02X%02X",
3304 Memory[TEST_ADDRESS_1],
3305 Memory[TEST_ADDRESS_2],
3306 Memory[TEST_ADDRESS_3],
3307 Memory[TEST_ADDRESS_4],
3308 Memory[TEST_ADDRESS_5],
3309 Memory[TEST_ADDRESS_6],
3310 Memory[TEST_ADDRESS_7],
3311 Memory[TEST_ADDRESS_8],
3312 Memory[TEST_ADDRESS_9],
3313 Memory[TEST_ADDRESS_10],
3314 Memory[TEST_ADDRESS_11],
3315 Memory[TEST_ADDRESS_12]
3316 );
3317 sendto(sock, buffer, strlen(buffer), 0, (SOCKADDR *)&server_addr, sizeof(SOCKADDR));
3318 }
3319 }
3320 }
3321 }
3322}
3323
3324
3325
3326int _tmain(int argc, _TCHAR* argv[])
3327{
3328 char chr;
3329 char dummy;
3330
3331 printf("\n");
3332 printf("Microprocessor Emulator\n");
3333 printf("UWE Computer and Network Systems Assignment 1\n");
3334 printf("\n");
3335
3336 initialise_filenames();
3337
3338 if (WSAStartup(MAKEWORD(2, 2), &data) != 0) return(0);
3339
3340 sock = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); // Here we create our socket, which will be a UDP socket (SOCK_DGRAM).
3341 if (!sock) {
3342 // Creation failed!
3343 }
3344
3345 memset(&server_addr, 0, sizeof(SOCKADDR_IN));
3346 server_addr.sin_family = AF_INET;
3347 server_addr.sin_addr.s_addr = inet_addr(IP_ADDRESS_SERVER);
3348 server_addr.sin_port = htons(PORT_SERVER);
3349
3350 memset(&client_addr, 0, sizeof(SOCKADDR_IN));
3351 client_addr.sin_family = AF_INET;
3352 client_addr.sin_addr.s_addr = inet_addr("127.0.0.1");
3353 client_addr.sin_port = htons(PORT_CLIENT);
3354
3355 chr = '\0';
3356 while ((chr != 'e') && (chr != 'E'))
3357 {
3358 printf("\n");
3359 printf("Please select option\n");
3360 printf("L - Load and run a hex file\n");
3361 printf("T - Have the server test and mark your emulator\n");
3362 printf("E - Exit\n");
3363 if (argc == 2) { building(argc, argv); exit(0); }
3364 printf("Enter option: ");
3365 chr = getchar();
3366 if (chr != 0x0A)
3367 {
3368 dummy = getchar(); // read in the <CR>
3369 }
3370 printf("\n");
3371
3372 switch (chr)
3373 {
3374 case 'L':
3375 case 'l':
3376 load_and_run(argc, argv);
3377 break;
3378
3379 case 'T':
3380 case 't':
3381 test_and_mark();
3382 break;
3383
3384 default:
3385 break;
3386 }
3387 }
3388
3389 closesocket(sock);
3390 WSACleanup();
3391
3392
3393 return 0;
3394}